S PDS202A SP Digital Recorder Preliminary MAY. 17, 2001 Version 0.4 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. Preliminary SPDS202A Table of Contents PAGE 1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3. FEATURES.................................................................................................................................................................................................. 3 4. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 4 5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 6 5.1. PARALLEL CONTROL/DATA I/O INTERFACE .............................................................................................................................................. 6 5.2. PLL ...................................................................................................................................................................................................... 7 5.3. ADC & DAC ......................................................................................................................................................................................... 7 5.4. FLASH INTERFACE ................................................................................................................................................................................ 10 5.5. UART INTERFACE................................................................................................................................................................................ 10 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 11 6.1. ABSOLUTE MAXIMUM RATINGS ..............................................................................................................................................................11 6.2. DC CHARACTERISTICS (VDD = 3.3V, TA = 25) ..................................................................................................................................11 7. APPLICATION CIRCUIT ........................................................................................................................................................................... 12 8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 13 8.1. PAD ASSIGNMENT ............................................................................................................................................................................... 13 8.2. ORDERING INFORMATION ..................................................................................................................................................................... 13 8.3. PAD LOCATIONS .................................................................................................................................................................................. 14 8.4. PACKAGE CONFIGURATION ................................................................................................................................................................... 15 8.5. PACKAGE INFORMATION ....................................................................................................................................................................... 16 9. DISCLAIMER............................................................................................................................................................................................. 17 10. REVISION HISTORY ................................................................................................................................................................................. 18 (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 2 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A DIGITAL RECORDER 1. GENERAL DESCRIPTION 3. FEATURES The SPDS202A is a single-chip microprocessor optimized for ! Single chip digital audio/speech encoder/decoder speech/audio digital recording. Base on SACM_S480 or SACM_S3200 It is based on the SACM_S480 or 8.0KHz sampling rate SACM_S3200 algorithm to encode/decode speech/audio, with low Low compressed data rate: 4.8Kbps or 32Kbps data rates for storage at 4.8Kbps and 32Kbps respectively, while retaining the good resolution of the original speech/audio. A high ! Digital sound control Digital volume control quality 10-bit 8KHz sampling rate CODEC (DAC/ADC) is embedded for speech/audio record/playback to achieve a better cost/performance ratio. ! Flexible flash control interface Connect up to 4 Flash chips The encoded data can be stored Internal Flash database manipulation into/retrieved from external Flash memory through a flexible Flash interface. A Receiver/Transmitter) UART (Universal interface is also Asynchronous supported ! UART interface Receive/Transmit data from/to PC and other RS232 to transmit/receive data to/from PC or any other RS-232 compatible devices. compatible devices Host processors can easily command the SPDS202A by using a parallel IO/control interface. designed for 3.3V applications. ! Parallel data IO and control interfaces Easy for the host processor to command The SPDS202A is Fabricated in the sub-micron ! Programmable serial interface Suitable for future feature extension triple metal CMOS process, the high performance SPDS202A processor can operate at 22MHz and dissipate low power. A ! PLL embedded built-in PLL is able to supply the system clock from a 32768Hz 22MHz system clock automatically synthesized crystal oscillator source. Requires only 32768Hz crystal, resistors, and capacitors Host processors can command the SPDS202A into the extremely low power consumption idle mode, ! Built-in DAC & ADC High quality 10-bit 8KHz DAC & ADC while not encoding/decoding, as an important feature for portable systems. ! Low power consumption In addition to it's low power consumption in the normal operation mode, nearly no power is consumed in the 2. BLOCK DIAGRAM specially designed idle mode. ! Characteristics TADSEL1 TADSEL0 DT1 DR1 Supply voltage: 2.8V - 3.6V TADCE Package: chip form, 100-pin LQFP Host Interface UART AIN ATO VM Power consumption: less than 100mW @ 3.3V TADD[7:0] CODEC (DAC & ADC) SPP SPN Encoder & Decoder A common implementation utilizing the SPDS202A is presented XO XI PDIFF VCOIN below: PLL & Crystal Oscillator FLASH Memory Controller PC RS232 Compatible Device RS-232 Line Driver FR_B FRD FWR FALE FCLE FCEB1 FCEB2 Microphone FCEB3 MDATA[7:0] Speaker FCEB4 8KHz 10bit SPDS202A 32768Hz SUNPLUS SPLXX LCD Key Scan Flash Digital Recorder System Block Diagram (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 3 3.3V DC-DC Converter MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 4. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type VDD 1 I Digital power NC 2 O Unused 32KOUT 3 O 32768Hz AVSS2 4 I Analog power for PLL AVDD2 5 I Analog power for PLL VCOIN 6 I PLL - VCO control signal PDIFF 7 NC NC 8 Description O PLL - Phase detector output O Unused O Unused NC 9 O Unused NC 10 O Unused VSS 11 I Digital power XI 12 I 32768Hz crystal XO 13 O 32768Hz crystal VDD 14 I Digital power NC 15 O Unused NC 16 O Unused NC 17 O Unused NC 18 O Unused FCEB4 19 O Flash memory chip 4 enable FCEB3 20 O Flash memory chip 3 enable FCEB2 21 O Flash memory chip 2 enable FCEB1 22 O Flash memory chip 1 enable VSS 23 I Digital power VDD 24 I Digital power FR-B 25 I Flash ready/busy FRD 26 O Flash read FWR 27 O Flash write FALE 28 O Flash address latch FCLE 29 O Flash command latch FWP 30 O Flash write protection NC 31 O Unused NC 32 O Unused NC 33 O Unused NC 34 O Unused NC O Unused NC O Unused VSS 35 I Digital power VDD 36 I Digital power MDATA7 37 I/O MDATA6 38 I/O Memory data bit 6 MDATA5 39 I/O Memory data bit 5 MDATA4 40 I/O Memory data bit 4 (c) Sunplus Technology Co., Ltd. Proprietary & Confidential Memory data bit 7 4 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A Mnemonic PIN No. Type Description MDATA3 41 I/O Memory data bit 3 MDATA2 42 I/O Memory data bit 2 MDATA1 43 I/O Memory data bit 1 MDATA0 44 I/O Memory data bit 0 VSS 45 I Digital power VDD 46 I Digital power TADCE 47 I Host control interface TADSEL1 48 I Host control interface TADSEL0 49 I Host control interface TADD7 50 I/O Host interface data bit 7 TADD6 51 I/O Host interface data bit 6 TADD5 52 I/O Host interface data bit 5 TADD4 53 I/O Host interface data bit 4 TADD3 54 I/O Host interface data bit 3 TADD2 55 I/O Host interface data bit 2 TADD1 56 I/O Host interface data bit 1 TADD0 57 I/O VSS 58 I Digital power VDD 59 I Digital power NC 60 I Unused NC 61 I Unused DR1 62 I Serial data receive NC 63 I/O Unused DT1 64 O Serial data transmit VSS 65 I Digital power VDD 66 I Digital power NC 67 I/O Unused NC 68 I/O Unused NC 69 I Unused NC 70 I/O Unused NC 71 O Unused AVSS1 72 I Analog power for CODEC AIN 73 I Negative input of ADC ATO 74 O Output of the transmit input amplifier SPP 75 O Positive output of DAC Host interface data bit 0 SPN 76 O Negative output of DAC VM 77 O 1/2 AVDD1(pin 78) AVDD1 78 I Analog power for CODEC NC 79 I Unused RESET 80 I System reset; low active VSS 81 I External oscillator NC 82 I Unused NC 83 I Unused VSS 84 I Digital power (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 5 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 5. FUNCTIONAL DESCRIPTIONS 2). 01: READ STATUS: The content of the SPDS202A status The SPDS202A is a single-chip CMOS microprocessor optimized register is output on TADD[7:0] by for real-time speech/audio digital recording. SPDS202A for the host processor to read. The SPDS202A, based on the SACM_S480 and SACM_S3200 algorithms, can encode/decode speech/audio according to commands passed through the Parallel Control/Data I/O When the selection is set to read status and the read pulse is Interface by the host processor (refer to the SPDS202A asserted through the TADCE pin, data in the status register of programming guide for command definitions). the SPDS202A is output onto the data bus for the host processor Speech/Audio is to read. first sampled at 8KHz by the on-chip ADC into 10-bit digital words. After encoding, the datum is compressed at a data rate of 4.8Kbps or 32Kbps. During playback, the decoded audio/speech can TADSEL [1:0] output directly to the speaker through the on-chip DAC. 00 (or 01) TASR T AHR TADCE SPDS202A can efficiently manage the encoded audio/speech with T Flash memory by using Flash Interface, or communicate the data using a PC through the UART Interface. The embedded PLL is RP TADD[7:0] T RDD capable of providing the 22MHz system clock from a 32768Hz T RDH clock source. 1). Timing requirements 5.1. Parallel Control/Data I/O Interface Parameter SPDS202A accepts the commands of the external host processor through this interface, 11 pins are included in this interface, as TASR listed below: TAHR PIN 47 - TADCE : command enable, low active TRP PIN [48,49] - TADSEL [1,0]: command selection TADSEL setup before TADCE falls low TADSEL hold after TADCE rises high TADCE pulse width low Min. Max. Unit 2.0 - ns 2.0 - ns 5.0 - ns Min. Max. Unit - 5.0 * ns 0 - ns PIN [50:57] - TADD [7:0]: data/command I/O bus 2). Switching characteristics 5.1.1. TADSEL[1,0] Parameter Using combinations of TADSEL[1,0] command selections (when TRDD TADCE is active low), one of four different functions can be carried out: TRDH 1). 00: READ DO: The host processor reads the data on TADCE TADD hold after TADCE rises high 3). 10: WRITE DI: The host processor writes data/ command on TADD[7:0] for SPDS202A to read. command) first, if bit 0 (DO_ack) is high, it signifies that valid data The host processor may use this write DI selection to transmit Then the host data or commands into SPDS202A; the transferred data or processor sets the selection to read do and asserts the read pulse commands on the data bus are latched into SPDS202A on the Data in the DO register is then output rising edge of TADCE . into the data bus for the host processor to read; After the read After the successful completion of write DI, bit 1 (DI_ack) of the SPDS202A status register goes to high operation, the status bit (DO_ack) is automatically cleared to low by the hardware. to TADD valid The host processor reads the status register (using the read status through the TADCE pin. low * P.s. loads on TADD pins < 40Pf TADD[7:0] output by SPDS202A. is ready to be read in the SPDS202A DO register. falls under the control of SPDS202A hardware to indicate that valid The status bit will be high again only when data from the host processor is in the DI register ready for another valid data is written to the DO register by the SPDS202A. SPDS202A to read. Only when the data in the DI register is read by SPDS202A will the status bit (DI_ack) fall to low. "DI_ack is low" also permits the host processor to write DI again. (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 6 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A TADSEL [1:0] pin 7 PDIFF 10 470K TASR TAHR pin 6 VCOIN TADD[7:0] 10 K 0.01F TRP TADCE 0.1F Low Pass Filter for PLL 1). Timing requirements Parameter Min. Max. Unit 0 - ns 2.0 - ns 2.0 - ns TADSEL & TADD setup TASR before TADCE falls low TADSEL & TADD hold TAHR after TADCE rises high pin 13 XO pin 12 XI 32768Hz Crystal TADCE pulse width low TRP 12 pF 12 pF 4). 11: RESET: the host processor resets SPDS202A. Oscillation Circuit In this selection, the TADCE pin functions just like pin 80 RESET . 5.3. ADC & DAC The SPDS202A is reset when TADCE is active (low). The SPDS202A has an audio-band sigma-delta analog-to-digital and digital-to-analog converter so as to meet the requirement of TADSEL [1:0] 11 TASR the digital recorder application. TAHR The circuit of converter consists of three main blocks: the analog-to-digital converter (ADC), the TADCE digital-to-analog converter (DAC), and internal reference and bias TRP voltage. The analog-to-digital conversion chain consists of a microphone 1). Timing requirements Parameter TASR TAHR TRP TADSEL setup before TADCE falls low TADSEL hold after TADCE rises high TADCE pulse width low For the latter, it is 15-bit format with 10-bit resolution. Min. Max. Unit 2.0 - ns amplifier (M.A.), a programmable gain amplifier (PGA), an analog oversampled modulator, and the decimation digital filter. The PGA has gain step from -12dB to 12dB (-12, -6, 0, 6, 12dB). The modulator is a sigma-delta feedback loop, which oversamples the 2.0 - ns 100 - ns signal at 1.024MHz and provides second-order noise shaping. It performs the conversion of the differential analog input signal to a pulse-density-modulated single-bit digital output. When a maximum positive differential input voltage is applied at the input 5.2. PLL of modulator, the resulting code at the output of the modulator is An independent analog power is applied through pin 4 AVSS2 and all ones. pin 5 AVDD2 to supply power for the internal PLL. An external low-pass filter is provided at pin 7 PDIFF and pin 6 VCOIN. The decimation digital filter consists of a comb filter and a half-band filter. The comb filter is a third-order comb filter. Finally the encoder implements the half-band filter and data An compression by software. external oscillation circuit is also provided at pin 12 XI and pin 13 XO. (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 7 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A The digital-to-analog conversion chain consists of the interpolation pulse-density-modulated single-bit digital output. digital filter, a digital oversampled modulator, an analog lowpass sampled at 1.024MHz from a digital oversampled modulator, is the filter, a smoothing filter, and the audio driver. input of the analog lowpass filter. The interpolation The input, It converses the single-bit digital filter consists of an interpolation half-band filter and an digital output to the differential analog output signal. interpolation smoothing filter is a second-order lowpass filter with a cutoff comb filter. The decoder interpolation half-band filter by software. filter is a second-order comb filter. implements the frequency of typically 10KHz. The interpolation comb (-12, -6, 0dB). The digital oversampled modulator is a second-order noise shaping. It performs the The It has gain step from -12B to 0B The audio driver is supported to drive the 8 or 16 speaker directly without needing any external amplifiers. conversion of the output data of the interpolation comb filter to a 5.3.1. ADC & DAC electrical characteristics (VDD = 3.3V, TA = 25C) Parameter Condition Min. Typ. Max. Unit - - 0.25*VDD Vpp MA gain = 0dB, ATO: Input Voltage PGA gain = 6dB Default: 6dB PGA: Gain Range -12 - 12 dB Step Size - 6.0 - dB Step Variation - 0.5 - dB -12 - 0 dB Step Size - 6.0 - dB Step Variation - 0.5 - dB Smoothing filter PGA: Default: -6dB Gain Range Audio Driver: Fully Differential (SPP-SPN) Full Swing With 8 load - - 0.7 VPP Single Ended (SPP or SPN) Full Swing With 8 load - - 0.35 VPP 0.45VDD 0.5VDD 0.55VDD VPP Voltage Reference: Output Voltage (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 8 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A A/D converter P.G.A. (-12,-6,0, 6,12dB) Microphone Amplifier ATO Controller IO port Smoothing filter Analog reference voltage generator 1 SPN SPP VM AIN 10F 400pF 100K AVSS1 Speaker 10K 5K 0.1F 5.1K M 47F 1 Audio Driver Microphone AVSS1 5.3.2. ADC & DAC path characteristics Parameter ADC: Signal to noise ratio Condition Min. Typ. Max. Unit - 60 - dB - 62 - dB FIN = 1KHz, PGA gain is 12dB ATO is full swing Without data compression DAC: Signal to noise ratio FOUT = 512Hz, Output (SPP-SPN) is 1.5Vpp No load Without data compression (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 9 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 5.4. Flash Interface 5.4.3. Chip enable pins This interface consists of 5 control pins, 8 data pins and 4 pins for Pin[19:22] - FCEB[4:1]: Device selection control pins; up to four component selection. A total of 17pins are included. Flash Flash components can be used as compressed memories of 8M, 16M, 32M and 64M can be used up to four speech/audio storage. components can be connected, the maximum storage capacity is For example; Four 16M bits Flash can be connected in the 256M bits. recording system. 5.4.1. Control pins Using SACM_S480, we can get a maximum speech duration of: Pin25 - FR_B (ready/busyb): An input pin to indicate the status of 6Mb * 4 / 4.8Kbps = 13,333s = 3.7hr the Flash device operation Pin26 - FRD (read enable): A data-out control. If using SACM_S3200, the duration is reduced to: It drives data 16Mb * 4 / 32Kbps from Flash into the data bus when active. Pin27 - FWR (write enable): Bits on the data bus are latched into = 2000s = 0.56hr 5.5. UART Interface Flash on the rising edge of this pin PC or other RS232 compatible devices may use this interface to Pin28 - FALE (address latch enable): When active, addresses are down-load/up-load data using SPDS202A. latched into Flash address registers. A program written in C-language is provided, to be executed on a PC. Pin29 - FCLE (command latch enable): when active, commands This eases the transfer process work load into some simple commands. are latched into Flash command registers. The maximum transfer rate is up to 115,200 bps. Pin30 - FWP (write protection): 0: To protect Flash from being written 1: Write is allowed 5.4.2. Data pins Pin[37:44] - MDATA[7:0]: To output data, address and command during write; and to input data during read. (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 10 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 6. ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings Characteristics Symbol Value Unit VDD 0.0 ~ 3.6 V Input Voltage Range VIN -0.3 ~ VDD + 0.3 V Operating Temperature TA 0 ~ 60 TSTO -55 ~ 125 DC Supply Voltage Storage Temperature Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 6.2. DC Characteristics (VDD = 3.3V, TA = 25) Characteristics Symbol Limit Unit Test Condition Min. Typ. Max. VDD 2.8 3.3 3.6 V VIL - - 0.2VDD V VDD = 3.3V Input High Voltage VIH 0.8VDD - - V VDD = 3.3V Output High Voltage VOH 2.4 - VDD V IOH = -4mA, VDD = 3.3V Output Low Voltage VOL - 0.3 0.6 V IOL = 4mA, VDD = 3.3V Power Supply Current IDD 23.0 28 33 mA Audio no load @ 22MHz Power-down Mode Current IPD - 5.5 9.0 A VDD = 3.3V Supply Voltage Input Low Voltage (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 11 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 7. APPLICATION CIRCUIT Microphone M 47F 5K 1F 5K 10K 100K 400pF Controller I/O Port 0.01F VDD 5K 12pF 10K 470K 0.01F Speaker 0.01F SPDS202A Application Circuit AVSS2 SPP SPN 75 76 77 78 79 80 81 82 83 84 1 2 3 4 AVDD2 VCOIN PDIFF VSS VDD RESET VSS AVDD1 5 6 7 8 9 10 32768Hz Crystal COB-84 SPDS202A 12pF RS-232 Line Driver DD5 DD6 TADD7 TADSEL0 TADSEL1 TADCE VDD VSS MDATA0 MDATA1 MDATA2 MDATA3 MDATA4 MDATA5 MDATA6 MDATA7 VDD VSS Flash 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PC RS232 Compatible Device Host Processor Preliminary Version: 0.4 Proprietary & Confidential FCEB4 FCEB3 FCEB2 FCEB1 VSS VDD FR_B FRD FWR FALE FCLE FWP MAY. 17, 2001 12 (c) Sunplus Technology Co., Ltd. ATO 74 AIN 73 AVSS1 72 71 70 69 68 67 VDD 66 VSS 65 DT1 64 63 DR1 62 61 60 VDD 59 VSS 58 TADD0 57 TADD1 56 TADD2 55 TADD3 54 TADD4 53 VSS XI XO VDD 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Preliminary SPDS202A 8. PACKAGE/PAD LOCATIONS 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 ATO AIN AVSS1 NC NC NC NC NC VDD VSS DT1 NC DR1 NC NC VDD VSS TADD0 TADD1 TADD2 TADD3 TADD4 8.1. PAD Assignment 75 76 77 78 79 80 81 82 83 84 1 2 3 4 AVDD2 VCOIN PDIFF NC NC NC NC 5 6 7 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 8 9 10 34 33 TADD5 TADD6 TADD7 TADSEL0 TADSEL1 TADCE VDD VSS MDATA0 MDATA1 MDATA2 MDATA3 MDATA4 MDATA5 MDATA6 MDATA7 VDD VSS NC NC NC NC VSS XI XO VDD NC NC NC NC FCEB4 FCEB3 FCEB2 FCEB1 VSS VDD FR_B FRD FWR FALE FCLE FWP NC NC 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SPP SPN VM AVDD1 NC RESET VSS NC NC VSS VDD NC 32KOUT AVSS2 Chip Size: 3810m x 3810m This IC substrate should be connected to VSS Note1: Chip size included scribe line. Note2: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note3: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible. 8.2. Ordering Information Product Number Package Type SPDS202A-nnnnV-C Chip form SPDS202A-nnnnV-P Package form (100-pin LQFP) Note1: Code number (nnnnV) is assigned for the customer. Note2: Code number (nnnn=0000 - 9999); version (V = A - Z). (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 13 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 8.3. PAD Locations PAD No. PAD Name X Y PAD No. PAD Name X Y 1 VDD 83.00 1884.93 42 MDATA2 3617.00 1916.32 2 NC 83.00 1749.12 43 MDATA1 3617.00 2048.98 3 32KOUT 83.00 1613.32 44 MDATA0 3617.00 2181.65 4 AVSS2 83.00 1477.50 45 VSS 3617.00 2314.30 5 AVDD2 83.00 1250.20 46 VDD 3617.00 2446.98 6 VCOIN 83.00 1125.20 47 TADCE 3617.00 2579.65 7 PDIFF 83.00 1000.20 48 TADSEL1 3617.00 2712.30 NC 83.00 864.40 49 TADSEL0 3617.00 2844.98 8 NC 83.00 728.60 50 TADD7 3617.00 2977.65 9 NC 83.00 592.80 51 TADD6 3617.00 3110.30 10 NC 83.00 457.00 52 TADD5 3617.00 3243.00 11 VSS 447.05 82.50 53 TADD4 3242.50 3617.50 12 XI 572.05 82.50 54 TADD3 3109.88 3617.50 13 XO 697.05 82.50 55 TADD2 2977.25 3617.50 14 VDD 822.05 82.50 56 TADD1 2844.62 3617.50 15 NC 947.05 82.50 57 TADD0 2712.00 3617.50 16 NC 1081.70 82.50 58 VSS 2579.40 3617.50 17 NC 1216.75 82.50 59 VDD 2446.78 3617.50 18 NC 1351.80 82.50 60 NC 2314.15 3617.50 19 FCEB4 1486.85 82.50 61 NC 2181.52 3617.50 20 FCEB3 1621.90 82.50 62 DR1 2048.93 3617.50 21 FCEB2 1756.95 82.50 63 NC 1916.30 3617.50 22 FCEB1 1892.00 82.50 64 DT1 1783.68 3617.50 23 VSS 2027.05 82.50 65 VSS 1651.05 3617.50 24 VDD 2162.10 82.50 66 VDD 1518.45 3617.50 25 FR-B 2297.15 82.50 67 NC 1393.45 3617.50 26 FRD 2432.20 82.50 68 NC 1268.45 3617.50 27 FWR 2567.25 82.50 69 NC 1143.45 3617.50 28 FALE 2702.30 82.50 70 NC 1018.45 3617.50 29 FCLE 2837.35 82.50 71 NC 893.45 3617.50 30 FWP 2972.40 82.50 72 AVSS1 760.70 3617.50 31 NC 3107.45 82.50 73 AIN 635.70 3617.50 32 NC 3242.50 82.50 74 ATO 510.70 3617.50 33 NC 3617.00 457.00 75 SPP 83.00 3442.55 34 NC 3617.00 589.65 76 SPN 83.00 3227.05 NC 3617.00 722.33 77 VM 83.00 2954.80 NC 3617.00 854.97 78 AVDD1 83.00 2829.80 35 VSS 3617.00 987.65 79 NC 83.00 2699.75 36 VDD 3617.00 1120.33 80 RESET 83.00 2563.95 37 MDATA7 3617.00 1252.97 81 VSS 83.00 2428.15 38 MDATA6 3617.00 1385.65 82 NC 83.00 2292.35 39 MDATA5 3617.00 1518.32 83 NC 83.00 2156.52 40 MDATA4 3617.00 1650.97 84 VSS 83.00 2020.72 41 MDATA3 3617.00 1783.65 (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 14 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 8.4. Package Configuration 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC NC NC TADD5 TADD6 TADD7 TADSEL0 TADSEL1 TADCE VDD VSS MDATA0 MDATA1 MDATA2 MDATA3 MDATA4 MDATA5 MDATA6 MDATA7 VDD VSS NC NC NC NC NC NC NC NC LQFP 100L Top View 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SPDS202A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 NC FWP FCLE FALE FWR FRD FR_B VDD VSS FCEB1 FCEB2 FCEB3 FCEB4 NC NC NC NC VDD XO XI NC SPP NC SPN NC VM NC AVDD1 NC RESET VSS NC NC VSS VDD NC 32KOUT AVSS2 AVDD2 VCOIN PDIFF NC NC NC NC NC NC NC NC VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TADD4 TADD3 TADD2 TADD1 TADD0 VSS VDD NC NC DR1 NC DT1 VSS VDD NC AVSS1 NC AIN NC ATO (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 15 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 8.5. Package Information Unit: inch/mm LQFP 100L Outline Dimensions D D1 D2 e E E1 E2 b c A2 L1 Symbol A1 A Min. Nom. Max. D - 22 - D1 - 20 - D2 - 18.85 - E - 16 - E1 - 14 - E2 - 12.35 - e - 0.65 - b 0.22 0.30 0.38 A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 c 0.09 - 0.20 L1 - 1.0 - Unit: millimeter (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 16 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 9. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. FURTHER, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 17 MAY. 17, 2001 Preliminary Version: 0.4 Preliminary SPDS202A 10. REVISION HISTORY Date Revision # Description Page OCT. 16, 1999 0.1 Original DEC. 15, 1999 0.2 1. Modify Stop :0 Pause : 0 normal recording or request for statusStop : 0 Pause : 1 Pause 10 Stop : 1 Pause : 0 stopStop : 1 Pause : 1 reserved 2. Add data-bit3 0:disable low-pass filter, 1:enable low-pass filter 18 3. Add Time of clearing flash is longer than 0.5sec. 19 4. CELP -> SACM_S480 5. ADPCM -> SACM_S3200 FEB. 29, 2000 0.3 1. Modify the following pin Name(Pin No.) to "NC" and modify the description to unused PLLOUT(2), ROMCE, RAS(8), ARAMOE(9), ARAMCE(10), CAS4-1(15-18), ADDR4-8(30-34), ADDR9, ADDR10, TFS1(60), RFS1(61), SCLK1(63), TFS0(67), RFS0(68), DR0(69), SCLK0(70), DT0(71), CLKSEL(79), TEST(82), PINSET(83) 2. Modify 12-bit to 1-bit thronghout the document 3. Modify the contents of ADC&DAC 4. Modify 2.7V to 2.8V 5. Modify the testing figures MAY. 16, 2001 0.4 1. Modify the element value of the microphone application circuit 9 2. Modify the element value of the microphone application circuit 12 3. Correct chip size 13 4. Add Note1 and Note in the "8.1 PAD Assignmnet" 13 5. Add "10.REVISION HISTORY" 18 6. Renew to a new document format (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 18 MAY. 17, 2001 Preliminary Version: 0.4