MC100ES8111
Rev 2, 09/2004
Freescale Semiconductor
Technical Data
Freescale Confidential Proprietary, NDA Required / Preliminary
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Low Voltage 1:10 Differential HSTL
Clock Fanout Buffer
The MC100ES8111 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES8111
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver are high performance
clock distribution in computing, networking and telecommunication systems.
Features
• 1:10 differential clock fanout buffer
• 80 ps maximum device skew
• SiGe technology
• Supports DC to 625 MHz operation of clock or data signals
• HSTL compatible differential clock outputs
• PECL and HSTL compatible differential clock inputs
• 3.3 V power supply for device core, 1.5 V or 1.8 V HSTL output supply
• Supports industrial temperature range
• Standard 32 lead LQFP package
Functional Des cription
The MC100ES8111 is designed for low skew clock distribution systems and
supports clock frequencies up to 625 MHz. The device acce pts two clock
sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts
PECL compatible signals. The selected input signal is distributed to 10 identical,
differential HSTL compatible outputs.
In order to meet the tight skew specification of the device, both outputs of a
differential output pair should be terminated, even if only one output is used. In
the case where not all 10 outputs are used, the output pairs on the same package
side as the parts being used on that side should be terminated.
The HSTL compatible output levels are generated with an open emitter
architecture. This minimizes part-t o-part and output-to-output skew. The
open-emitter outputs require a 50 Ω DC te rmination to GND (0 V). The output
supply voltage can be either 1.5 V or 1.8 V, the core voltage supply is 3.3 V. The
output enable control is synchronized internally preventing output runt pulse
generation. Outputs are only disabled or enabled when the outputs are already
in logic low state (true outputs logic low , inverted outputs logic high). The internal
synchronizer eliminates the setup and hold time requirements for the external
clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP
package.
MC100ES8111
LOW-VOLTAGE 1:10
DIFFERENTIAL
HSTL CLOCK
FANOUT BUFFER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
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Figure 1. MC100ES8111 Logic Diagram Figure 2. 23-Lead Package Pinout (Top View)
0
1
CLK0
CLK0
CLK1
CLK1
CLK_SEL
VCC
VCC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
OE
OE
Q8
V
CCO
Q2
Q1
Q0
V
CC0
Q7
Q9
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
V
CC
CLK_SEL
CLK0
CLK0
OE
CLK1
CLK1
GND
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17 16
MC100ES8111
V
CCO
V
CCO
Q2
Q1
Q0
Q7
Q8
Q9
Table 1. Pin Configuration(1)
1. Input pull-up/pull-down resistors have a value of 75 kΩ.
Pin I/O Type Function
CLK0, CLK0 Input HSTL Differential HSTL reference clock signal input
CLK1, CLK1 Input PECL Differential PECL reference clock signal input
CLK_SEL Input LVCMOS Reference clock input select
OE Input LVCMOS Output enable/disable. OE is synchronous to tlhe input reference clock which
eliminates possible output runt pulses when the OE state is changed.
Q[0-9], Q[0-9] Output HSTL Differential clock outputs
GND Supply Negative power supply
VCC Supply Positive power supply of the device core (3.3 V)
VCCO Supply Positive power supply of the HSTL outputs. All VCCO pins must be connected to the
positive power supply (1.5 V or 1.8 V) for correct DC and AC operation.
Table 2. Function Table
Control Default 0 1
CLK_SEL 0CLK0, CLK0 (HSTL) is the active differential clock
input CLK1, CLK1 (PECL) is the active differential clock
input
OE 0Q[0-9], Q[0-9] are active. Deasser t ion of OE can be
asynchronous to the reference clock without
generation of output runt pulses.
Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock
without generation of output runt pulses.
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Table 3. Abso lute Maximum Ratings(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol Characteristics Min Max Unit Condition
VCC Supply Voltage –0.3 3.6 V
VCCO Supply Voltage –0.3 3.1 V
VIN DC Input Voltage –0.3 VCC + 0.3 V
VOUT DC Output Voltage –0.3 VCC + 0.3 V
IIN DC Input Current ±20 mA
IOUT DC Output Current ±50 mA
TSStorage Temperature –65 125 °C
TFunc Functional Temperature Range TA = –40 TJ = +110 °C
Table 4. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
VTT Output termination voltage 0 V
MM ESD Protection (Machine model) 200 V
HBM ESD Protection (Human body model) 2000 V
CDM ESD Protection (Charged device model) 2000 V
LU Latch-up Immunity 200 mA
CIN Input Capacitance 4.0 pF Inputs
θJA Thermal resistance junction to ambient
JESD 51-3, single layer test board
JESD 51-6, 2S2P multilayer test board
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
θJC Thermal Resistance Junction to Case 23.0 26.3 °C/W MIL-SPEC 883E
Method 1012.1
TJOperating Junction Temperature(1)
(continuous operation)MTBF = 9.1 years
1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected
according to the application life time requirements (See application note AN1545 and the application section in this datasheet for more
information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MC100ES8111 to be used
in applications requiring industrial temperature range. It is recommended that users of the MC100ES8111 employ thermal modeling
analysis to assist in applying the junction temperature specifications to their particular application.
110 °C
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Table 5. DC Characteristics (VCC = 3.3 V ± 5%, VCCO = 1.5 V ± 0.1 V or VCCO = 1.8 V ± 0.1 V), TJ = 0°C to +110°C
Symbol Characteristics Min Typ Max Unit Condition
Clock Input Pair CLK0, CLK0 (HSTL differential signals)
VDIF Differential Input Voltage(1)
1. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality.
0.2 V
VX, IN Differential Cross Point Voltage(2)
2. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC)
range and the input swing lies within the VPP (DC) specification.
0.25 0.68 - 0.9 VCC-1.3 V
VIH Input High Voltage VX+0.1 V
VIL Input Low Voltage VX-0.1 V
IIN Input Current ±150 µA VIN = VX ± 0.1 V
Clock Input Pair CLK1, CLK1 (PECL differential signals)
VPP Differential Input Voltage(3)
3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
0.15 1.0 VDifferential operation
VCMR Differential Cross Point Voltage(4)
4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
1.0 VCC-0.6 VDifferential operation
VIH Input Voltage High VCC-1.165 VCC-0.880 V
VIL Input Voltage Low VCC-1.810 VCC-1.475 V
IIN Input Current ±150 µA VIN = VIH or VIN
LVCMOS Control Inputs OE, CLK_SEL
VIL Input Voltage Low 0.8 V
VIH Input Voltage High 2.0 V
IIN Input Current ±150 µA VIN = VIH or VIN
HSTL Clock Outputs (Q[0-9], Q[0-9])
VX, OUT Output Differential Crosspoint 0.68 0.75 0.9 V
VOH Output High Voltage 1.0 V
VOL Output Low Voltage 0.4 V
Supply Current
ICC Maximum Supply Current without output
termination current 80 105 mA VCC pin (core)
ICCO(5)
5. ICC includes current through the output resistors (all outputs terminated to VTT). See also “Power Consumption and Junction Temperature”
on page 6.
Maximum Supply Current, outputs
terminated 50 Ω to VTT
350 410 mA VCCO pins (outputs)
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Table 6. AC Characteristic s (VCC = 3.3 V ± 5%, VCCO = 1.5 V ± 0.1 V or VCCO = 1.8 V ± 0.1 V), TJ = 0°C to +110°C(1)
1. AC characteristics apply for parallel output termination of 50 Ω to VTT (GND).
Symbol Characteristics Min Typ Max Unit Condition
REF_SEL= 0, Active Clock Input Pair CLK0, CLK0 (HSTL differential signals)
VDIF Differential Input Voltage(2) (Peak-to-Peak)
2. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality.
0.4 V
VX, IN Differential Cross Point Voltage(3)
3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC)
range and the input swing lies within the VDIF (DC) specification.
0.68 0.9 V
fCLK Input Frequency 0625 MHz
tPD Propagation Delay CLK0 to Qn VCCO = 1.8 V
VCCO = 1.5 V 700
700 990
1030 1270
1420 ps
ps Differential
tSK(PP) Output-to-Output Skew (Part-to-Part) VCCO = 1.8 V
VCCO = 1.5 V 570
720 ps
ps Differential
tSK(P) Output Pulse Skew(4) VCCO = 1.8 V
VCCO = 1.5 V
4. Output duty cycle is DC = (0.5 ± 150 ps · fOUT) · 100%. E.g. the DC range at fOUT = 100 MHz is 48.5% < DC < 51.5%.
100
150 ps
ps
REF_SEL = 1, Active Clock Input Pair CLK1, CLK1 (PECL differential signals)
VPP Differential Input Voltage(5) (Peak-to-Peak)
5. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device
skew.
0.2 1.0 V
VCMR Differential Input Crosspoint Voltage(6)
6. VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
(AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation
delay, device and part-to-part skew.
1.0 VCC-0.6 V
fCLK Input Frequency 0625 MHz Differential
tPD Propagation Delay CLK1 to Qn VCCO = 1.8 V
VCCO = 1.5 V 590
590 860
910 1220
1360 ps
ps Differential
tSK(PP) Output-to-Output Skew (Part-to-Part) VCCO = 1.8 V
VCCO = 1.5 V 630
770 ps
ps Differential
tSK(P) Output Pulse Skew(7) VCCO = 1.8 V
VCCO = 1.5 V
7. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. The output duty cycle is DC = (0.5 ± 200 ps ·
fOUT) · 100%. E.g. the DC range at fOUT = 100 MHz an d VCCO = 1.5 V is 48.0% < DC < 52.0%.
150
200 ps
ps
HSTL Clock Outputs (Qn, Qn)
VX, OUT Output Differential Crosspoint 0.68 0.91 1.1 V
VOH Output High Voltage VCCO = 1.8 V
VCCO = 1.5 V VCCO-0.8 V
VCCO-0.5 V 1.5
1.5 V
V
VOL Output Low Voltage 0.2 0.8 V
VO(P-P) Differential Output Voltage (Peak-to-Peak) VCCO = 1.8 V
VCCO = 1.5 V 0.45
0.40 1.0
1.0 V
V
tSK(O) Output-to-Output Skew VCCO = 1.8 V
VCCO = 1.5 V 37
60 80
105 ps
ps Differential
tJIT(CC) Output Cycle-to-Cycle Jitter RMS (1 σ)1.0 ps
tr, tfOutput Rise/Fall Time 150 800 ps 20% to 80%
tPDL(8)
8. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
Output Disable Time 2.5·T + tPD 3.5·T + tPD ns T=CLKn period
tPLE(9)
9. Propagation delay OE assertion to output enabled (active).
Output Enable Time 3.0·T + tPD 4.0·T + tPD ns T=CLKn period
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APPLICATIONS INFORMATION
Test Referenc e an d Output Termination
The MC100ES8111 is designed for high-frequency and
low-skew clock distribution. The high -speed differential
outputs are capable of driving 50 Ω transmission lines and
always require a DC termination to VTT (GND). In order to
maintain the tight skew and timing specifications, it is
recommend to terminate the differential outputs by 50 Ω to
GND, with the termination resistor located as close as
possible to the end of the clock transmission line. All DC and
AC specifications apply to this termination method (see the
reference circuit shown in Figure 3 “MC100ES8111 AC Test
Reference”). The MC100ES81 11 does not support an output
termination to VTT = VX = 0.75 V (center voltage termination).
Figure 3. MC100ES8111 AC Test Referen ce
Power Consumption and the Junction Temperature
The power consumption PTOT of the MC100ES8111
depends on the supply voltages and th e DC output
termination. The clock freq uency has a negligible effect on
PTOT. If all outputs are terminated by 50 Ω to GND, the device
power consumption is calculated by:
PTOT = VCC · ICC + ICCO · (VCCO - VX)
For instance, at a supply voltage of VCC = 3.3 V and a
termination of 50 Ω to GND, the typical device power
consumption is 579 mW at VCCO = 1.8 V and 474 mW at
VCCO = 1.5 V.
To make the optimum use of high clock frequency and low
skew capabilities of the MC100ES8111, the device is
specified, characterized and tested for the junction
temperature range of TJ = 0°C to +1 10°C. Because the exact
thermal performance depends on the PCB type, design,
thermal management and natural or fo rced air convection,
the junction temperature provides an exact way to correlate
the application specific conditions to the published
performance data of this datasheet. The correlation of the
junction temperature range to the application ambient
temperature range and vice versa can be done by
calculation: TJ = TA + Rthja · Ptot
Assuming a thermal resistance (junction to ambient) of
54.4°C/W (2s2p board, 100 ft/min airflow , see Table 8) and a
typical power consumption of 575 mW (all outputs terminated
50 ohms to GND, VCCO = 1.8 V), the junction temperature of
the MC100ES8111 is app roximately TA+ 31° C, and the
minimum ambient temperature in this example case
calculates to -31°C (the maximum ambient temperature
is 79°C. See Table 8). Exceeding the minimum junction
temperature specification of the MC100ES8111 does not
have a significant impact on the device functionality.
However, the continuous use the MC100ES8111 at high
ambient temperatures requires thermal management to not
exceed the specified maximum junction te mperature.
Maintaining Lowest Device Skew
The MC100ES81 1 1 guarantees low output-to-output skew
of max. 80 ps and a part-to-part skew of max. 630 ps
(VCCO = 1.8 V). To ensure low skew clock signals in the
application, both outputs of any differential output pair need
to be terminated identically, even if only one output is used.
When fewer than all ten output pairs are used, identical
termination of all output pairs within the output bank (same
package side) is recommended. If an entire output bank is not
used, it is recommended to leave all of these outputs open
and unterminated. This will reduce the device power
consumption while maintaining minimum output skew.
Z = 50 Ω
RT = 50 Ω
DUT
MC100ES8111
Differential Pulse
Generator
Z = 50 Ω
RT = 50 Ω
VTT = GND VTT = GND
VCC = 3.3 V ± 5%
VCCO = 1.8 V ± 0.1 V or 1.5 V ± 0. 1 V
Z = 50 ΩOscilloscope
or Tester
Table 7. Power Consumption
MC100ES8111 PTOT, TYP(1)
1. Typical case: VCC, VCCO at nominal values and using typical
ICC, ICCO data.
PTOT, MAX(2)
2. Worst case: VCC, VCC at max. values and using max. ICC, ICCO
limits.
VCCO = 1.5 V 470 mW 647 mW
VCCO = 1.8 V 575 mW 769 mW
Table 8. Ambient Temperature Ranges (Ptot = 575 mW)
Rthja (2s2p bo ard) TA, min(1)
1. The MC100ES8111 device function is guaranteed from
TA = -40°C to TJ = 110°C.
TA, max
Natural convection 59.0°C/W -34°C 76°C
100 ft/min 54.4°C/W -31°C 79°C
200 ft/min 52.5°C/W -30°C 80°C
400 ft/min 50.4°C/W -29°C 81°C
800 ft/min 47.8°C/W -27.5°C 82.5°C
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Power Supply Bypassing
The MC100ES81 11 is a mixed analog/digital product. The
differential architecture of the MC100ES8111 supports low
noise signal operation at high frequencies. In order to
maintain its superior signal quality, all VCC pins should be
bypassed by high-frequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally
generated switching noise on the supply pins cross the series
resonant point of an individual bypass capacitor, its overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the noise band width.
Figure 4. VCC, VCCO Power Supply Bypass
Output Enable/Disable Control
The MC100ES8111 enables and disables outputs
synchronously to the input clock signal. The user may enable
and disable the outputs by using the OE control regardless of
any hold and setup time constraints. Output runt pulses are
prevented in any case. Outputs are disabled in logic low state
(Qn=Low, Qn=High) without a change of the output
impedance.
Figure 5. MC100ES8111 Output Disable/Enable Timing
VCC
0.1 nF
33...100 nF MC100ES8111
0.1 nF
33...100 nF
4
3.3 V ± 5%
1.8 V ± 0.1 V or VCCO
1.5 V ± 0. 1V
CLKn
CLKn
OE
Qn
Qn
tPDL (OE to Qn)
50%
tPLE (OE to Qn)
Outputs Disabled
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AC MEASUREMENT REFERENCES
Figure 6. MC100ES8111 AC Reference
Measurement Waveform (HSTL Input)
Figure 7. MC100ES8111 AC Reference
Measurement Wavefo rm (PECL Input)
Figure 8. Output-to-Output Skew
The output-to-output skew is defined as the worst case
difference in propagation delay between any two similar
delay paths within a single device.
Figure 9. HSTL Ou tput Rise/Fall Time
CLK0
CLK0
Qn
Qn
REF_SEL = 0
tPD (CLK0 to Qn)
VX,IN = 0.75 V
V
DIF
= 1.0 V
VO(P-P)
VOL
VOH
VX;OUT
CLK1
CLK1
Qn
Qn
REF_SEL = 1 tPD (CLK1 to Qn)
VCMR = VCC-1.3 V
VPP = 0.8 V
VOL
VOH
VO(P-P) VX;OUT
tSK(O)
Q0
Q0
QN
QN
tR
80%
20%
tF
VO(PP)
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PACKAGE DIMENSIONS
CASE 873A-03
ISSUE B
12 REF
DIM MIN MAX
MILLIMETERS
A
A1
7.00 BSC
A2
0.80 BSC
b
9.00 BSC
b1 0.30 0.40
c0.09 0.20
c1 0.09 0.16
D
D1
e
E
E1
L
L1 1.00 REF
R1 0.08 0.20
R2
S
1
1.40 1.60
0.05 0.15
1.35 1.45
0.30 0.45
0.08 ---
0˚ 7˚
9.00 BSC
7.00 BSC
0.50 0.70
q
q
0.20 REF
D1
D/2
EE1
1
8
9
17
25
32
D1/2
E1/2
E/2
4X
D
7
A
D
B
A-B0.20 H D
4X
A-B0.20 C D
6
64
4
DETAIL G
PIN 1 INDEX
DETAIL AD
R R2
θ˚
(S) L
(L1)
0.25
GAUGE PLANE
A2
A
A1
(θ1˚)
8X
R R1
e
SEATING
PLANE
DETAIL AD
0.1 C
C
32X
28X
H
DETAIL G
F
F
e/2 A, B, D
3
SECTION F-F
BASE
c1c
b
b1
METAL
A-B
M
0.20 DC
5 8
PLATING
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
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NOTES
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NOTES
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© Freescale Semiconductor, Inc. 2004. All rights reserved.
MC100ES8111
Rev. 2
09/2004
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