ICS83905AKT - Integrated Device Technology

LOW SKEW, 1:6 CRYSTAL-TO-

LVCMOS/LVTTL FANOUT BUFFER

ICS83905

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 1 ICS83905AM REV. B JANUARY 24, 2008

GENERAL DESCRIPTION

The ICS83905 is a low skew, 1-to-6 LVCMOS / LVTTL

Fanout Buffer and a member of the HiPerClockS™

family of High Performance Clock Solutions from IDT.

The low impedance LVCMOS/LVTTL outputs are de-

signed to drive 50Ω series or parallel terminated

transmission lines. The effective fanout can be increased from 6

to 12 by utilizing the ability of the outputs to drive two series

terminated lines.

The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V,

mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating

supply mode. Guaranteed output and part-to-part skew char-

acteristics along with the 1.8V output capabilities makes the

ICS83905 ideal for high performance, single ended applica-

tions that also require a limited output voltage.

FEATURES

•Six LVCMOS / LVTTL outputs

•Outputs able to drive 12 series terminated lines

•Crystal oscillator interface

•Crystal input frequency range: 10MHz to 40MHz

•Output skew: 80ps (maximum)

•RMS phase jitter @ 25MHz, (100Hz - 1MHz):

0.26ps (typical) (VDD = VDDO = 2.5V)

Phase noise:

Offset Noise Power

100Hz ............. -129.7 dBc/Hz

1kHz ............. -144.4 dBc/Hz

10kHz ............. -147.3 dBc/Hz

100kHz ............. -157.3 dBc/Hz

•5V tolerant enable inputs

•Synchronous output enables

•Operating power supply modes:

Full 3.3V, 2.5V and 1.8V,

mixed 3.3V core/2.5V output operating supply,

mixed 3.3V core/1.8V output operating supply,

mixed 2.5V core/1.8V output operating supply

•0°C to 70°C ambient operating temperature

•Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

HiPerClockS™

ICS

XTAL_OUT

ENABLE 2

GND

BCLK0

VDDo

BCLK1

GND

BCLK2

XTAL_IN

ENABLE 1

BCLK5

VDDO

BCLK4

GND

BCLK3

VDD

ICS83905

16-Lead SOIC

3.9mm x 9.9mm x 1.38mm

body package

M Pacakge

Top View

16-Lead TSSOP

4.4mm x 5.0mm x 0.925mm

body package

G Pacakge

Top View

20 19 18 17 16

6 7 8 9 10

ENABLE 2

XTAL_OUT

XTAL_IN

ENABLE 1

BCLK5

VDDO

BCLK4

GND

BCLK0

VDDO

BCLK1

GND

BCLK2

VDD

BCLK3

ICS83905

20-Lead VFQFN

4mm x 4mm x 0.925mm

body package

K Package

Top View

PIN ASSIGNMENTS

BLOCK DIAGRAM

SYNCHRONIZE

BCLK0

BCLK1

BCLK2

BCLK3

BCLK4

BCLK5

ENABLE 1

ENABLE 2

XTAL_IN

XTAL_OUT

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 2 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

TABLE 3. CLOCK ENABLE FUNCTION TABLE

emaNepyTnoitpircseD

TUO_LATXtuptuO.tuptuoehtsiTUO_LATX.ecafretnirotallicsolatsyrC

NI_LATXtupnI.tupniehtsiNI_L

ATX.ecafretnirotallicsolatsyrC

2ELBANE,1ELBANEtupnI .3elbaTeeS.slevelecafretniLTTVL/SOMCVL.elbanekcolC

KLCB,1KLCB,0KLCB

5KLCB,4KLCB,3KLCB tuptuO.slevelecafretniLTTVL/SOMCVL.stuptuokcolC

DNGrewoP.dnuorgylppusrew

rewoP.nipylppuseroC

ODD

rewoP.nipylppustuptuO

c/ndesunU.tcennocoN

stupnIlortnoCstuptuO

1ELBANE2ELBANE4KLCB:0KLCB5KLCB

00 WOLWOL

01 WOLgnilggoT

10 gnilggoTWOL

11 gnilggoTgnilggoT

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

ecnaticapaCnoitapissiDrewoP

)tuptuorep(

ODD

V564.3=91Fp

ODD

V526.2=81Fp

ODD

V2=61Fp

TUO

ecnadepmItuptuO

ODD

%5±V3.3=7

ODD

%5±V5.2=7

ODD

V2.0±V8.1=01Ω

BCLK5

BCLK0:4

ENABLE2

ENABLE1

FIGURE 1. ENABLE TIMING DIAGRAM

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 3 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ODD

egatloVylppuStuptuO 531.33.3564.3V

tnerruCylppuSrewoP00=2:1ELBANE01Am

ODD

tnerruCylppuStuptuO00=2:1ELBANE5Am

TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 573.25.2526.2V

ODD

egatloVylppuStuptuO 573.25.2526.2V

tnerruCylppuSrewoP00=2:1ELBANE8Am

ODD

tnerruCylppuStuptuO00=2:1ELBANE4Am

TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 6.18.10.2V

ODD

egatloVylppuStuptuO 6.18.10.2V

tnerruCylppuSrewoP00=2:1ELBANE5Am

ODD

tnerruCylppuStuptuO00=2:1ELBANE3Am

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5 V

Outputs, V

O-0.5V to VDDO + 0.5V

Package Thermal Impedance, θ

16 Lead SOIC package 78.8°C/W (0 mps)

16 Lead TSSOP package 100.3°C/W (0 mps)

20 Lead VFQFN package 57.5°C/W (0 mps)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional op-

eration of product at these conditions or any conditions beyond

those listed in the

DC Characteristics

AC Characteristics

is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ODD

egatloVylppuStuptuO 573.25.2526.2V

tnerruCylppuSrewoP00=2:1ELBANE01Am

ODD

tnerruCylppuStuptuO00=2:1ELBANE4Am

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 4 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 4G. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI ,1ELBANE

2ELBANE

%5±V3.3=2V

3.0+V

%5±V5.2=7.1V

3.0+V

V2.0±V8.1=V*56.0

3.0+V

egatloVwoLtupnI ,1ELBANE

2ELBANE

%5±V3.3=3.0-8.0V

%5±V5.2=3.0-7.0V

V2.0±V8.1=3.0-V*53.0

hgiHtuptuOegatloV

ODD

1ETON;%5±V3.3=6.2V

ODD

I;%5±V5.2=

Am1-=2 V

ODD

1ETON;%5±V5.2=8.1V

ODD

1ETON;V2.0±V8.1=V

ODD

3.0-V

egatloVwoLtuptuO

ODD

1ETON;%5±V3.3=5.0V

ODD

I;%5±V5.2=

Am1=4.0V

ODD

1ETON;%5±V5.2=54.0V

ODD

1ETON;V2.0±V8.1=53.0V

05htiwdetanimretstuptuO:1ETON ΩVot

ODD

.smargaid"tiucriCtseTdaoL",noitcestnemerusaeMretemaraPeeS.2/

TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ODD

egatloVylppuStuptuO 6.18.10.2V

tnerruCylppuSrewoP00=2:1ELBANE01Am

ODD

tnerruCylppuStuptuO00=2:1ELBANE3Am

TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 573.25.2526.2V

ODD

egatloVylppuStuptuO 6.18.10.2V

tnerruCylppuSrewoP00=2:1ELBANE8Am

ODD

tnerruCylppuStuptuO00=2:1ELBANE3Am

TABLE 5. CRYSTAL CHARACTERISTICS

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuF

ycneuqerF 0104zHM

)RSE(ecnatsiseR

seireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

leveLevirD 1Wm

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 5 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C

TABLE 6B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO

latsyrClanretxEgnisU0104zHM

kcolClanretxEgnisU

;ecruoS1ETON CD001zHM

cdoelcyCytuDtuptuO 8425%

)o(ks4,2ETON;wekStuptuO 08sp

)Ø(tij)modnaR(rettiJesahPSMR noitargetnI(@zHM52

)zHM1-zH001:egnaR 31.0sp

emiTllaF/esiRtuptuO%08ot%02002008sp

;emiTelbanEtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

SID

;emiTelbasiDtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

ƒtaderusaemsretemarapllA ≤f

XAM

.esiwrehtodetonsselnutupnilatsyrcagnisu

05tadetanimreT ΩVot

ODD

.2/

.edivorpdluowlatsyrcalangisaotevitalernevirdrevoebnacNI_LATX:1ETON

VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

ODD

.2/

.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:3ETON

.56dradnatSCEDEJhtiwecn

adroccanidenifedsiretemarapsihT:4ETON

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO

latsyrClanretxEgnisU0104zHM

kcolClanretxEgnisU

;ecruoS1ETON CD001zHM

cdoelcyCytuDtuptuO 7435%

)o(ks5,2ETON;wekStuptuO 08sp

)Ø(tij3ETON;)modnaR(rettiJesahPSMR noitargetnI(@zHM52

)zHM1-zH001:egnaR 62.0sp

emiTllaF/esiRtuptuO%08ot%02002008sp

;emiTelbanEtuptuO

4ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

SID

;emiTelbasiDtuptuO

4ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

ƒtaderusaemsretemarapllA ≤f

XAM

.esiwrehtodetonsselnutupnilatsyrcagnisu

05tadetanimreT ΩVot

ODD

.2/

.edivorpdluowlatsyrcalangisaotevitalernevirdrevoebnacNI_LATX:1ETON

VtaderusaeM.snoitidnocdaollauqeh

tiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

ODD

.2/

.tolpesionesahpotreferesaelP:3ETON

.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarap

esehT:4ETON

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:5ETON

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 6 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 6D. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C

TABLE 6C. AC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO

latsyrClanretxEgnisU0104zHM

kcolClanretxEgnisU

;ecruoS1ETON CD001zHM

cdoelcyCytuDtuptuO 7435%

)o(ks4,2ETON;wekStuptuO 08sp

)Ø(tij)modnaR(rettiJesahPSMR noitargetnI(@zHM52

)zHM1-zH001:egnaR 72.0sp

emiTllaF/esiRtuptuO%08ot%02002009sp

;emiTelbanEtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

SID

;emiTelbasiDtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

ƒtaderusaemsretemarapllA ≤f

XAM

.esiwrehtodetonsselnutupnilatsyrcagnisu

05tadetanimreT ΩVot

ODD

.2/

.edivorpdluowlatsyrcalangisaotevitalernevirdrevoebnacNI_LATX:1ETON

VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

ODD

.2/

.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:3ETON

.56dradnatSCEDEJhtiwecn

adroccanidenifedsiretemarapsihT:4ETON

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO

latsyrClanretxEgnisU0104zHM

kcolClanretxEgnisU

;ecruoS1ETON CD001zHM

cdoelcyCytuDtuptuO 8425%

)o(ks4,2ETON;wekStuptuO 08sp

)Ø(tij)modnaR(rettiJesahPSMR noitargetnI(@zHM52

)zHM1-zH001:egnaR 41.0sp

emiTllaF/esiRtuptuO%08ot%02002008sp

;emiTelbanEtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

SID

;emiTelbasiDtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

ƒtaderusaemsretemarapllA ≤f

XAM

.esiwrehtodetonsselnutupnilatsyrcagnisu

05tadetanimreT ΩVot

ODD

.2/

.edivorpdluowlatsyrcalangisaotevitalernevirdrevoebnacNI_LATX:1ETON

VtaderusaeM.snoitidnocdaollauqeh

tiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

ODD

.2/

.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:3ETON

.56dradnatSCEDEJhtiwecn

adroccanidenifedsiretemarapsihT:4ETON

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 7 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 6E. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C

TABLE 6F. AC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO

latsyrClanretxEgnisU0104zHM

kcolClanretxEgnisU

;ecruoS1ETON CD001zHM

cdoelcyCytuDtuptuO 8425%

)o(ks4,2ETON;wekStuptuO 08sp

)Ø(tij)modnaR(rettiJesahPSMR noitargetnI(@zHM52

)zHM1-zH001:egnaR 81.0sp

emiTllaF/esiRtuptuO%08ot%02002009sp

;emiTelbanEtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

SID

;emiTelbasiDtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

ƒtaderusaemsretemarapllA ≤f

XAM

.esiwrehtodetonsselnutupnilatsyrcagnisu

05tadetanimreT ΩVot

ODD

.2/

.edivorpdluowlatsyrcalangisaotevitalernevirdrevoebnacNI_LATX:1ETON

VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

ODD

.2/

.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:3ETON

.56dradnatSCEDEJhtiwecn

adroccanidenifedsiretemarapsihT:4ETON

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO

latsyrClanretxEgnisU0104zHM

kcolClanretxEgnisU

;ecruoS1ETON CD001zHM

cdoelcyCytuDtuptuO 7435%

)o(ks4,2ETON;wekStuptuO 08sp

)Ø(tij)modnaR(rettiJesahPSMR noitargetnI(@zHM52

)zHM1-zH001:egnaR 91.0sp

emiTllaF/esiRtuptuO%08ot%02002009sp

;emiTelbanEtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

SID

;emiTelbasiDtuptuO

3ETON

1ELBANE 4selcyc

2ELBANE 4selcyc

ƒtaderusaemsretemarapllA ≤f

XAM

.esiwrehtodetonsselnutupnilatsyrcagnisu

05tadetanimreT ΩVot

ODD

.2/

.edivorpdluowlatsyrcalangisaotevitalernevirdrevoebnacNI_LATX:1ETON

VtaderusaeM.snoitidnocdaollauqeh

tiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

ODD

.2/

.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:3ETON

.56dradnatSCEDEJhtiwecn

adroccanidenifedsiretemarapsihT:4ETON

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 8 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TYPICAL PHASE NOISE AT 25MHZ (2.5V CORE/ 2.5V OUTPUT)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

10 100 1k 10k 100k 1M

25MHz

RMS Phase Jitter (Random)

100Hz to 1MHz = 0.26ps (typical)

OFFSET FREQUENCY (HZ)

NOISE POWER dBc

Raw Phase Noise Data

➤

TYPICAL PHASE NOISE AT 25MHZ (3.3V CORE/ 3.3V OUTPUT)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

10 100 1k 10k 100k 1M

25MHz

RMS Phase Jitter (Random)

100Hz to 1MHz = 0.13ps (typical)

OFFSET FREQUENCY (HZ)

NOISE POWER dBc

Raw Phase Noise Data

➤

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 9 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

PARAMETER MEASUREMENT INFORMATION

SCOPE

LVCMOS

GND

1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT

2.4±0.9V

VDDO

-0.9V±0.1V

VDD

0.9V±0.1V

SCOPE

LVCMOS

GND

2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

2.05V±5%

VDDO

-1.25V±5%

VDD

1.25V±5%

3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

LVCMOS

GND

1.65V±5%

-1.65V±5%

3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

LVCMOS

GND

1.25V±5%

-1.25V±5%

SCOPE

LVCMOS

GND

0.9V±0.1V

-0.9V ± 0.1V

SCOPE

LVCMOS

GND

1.6V±0.025%

VDDO

-0.9V±0.1V

VDD

0.9V±0.1V

VDD,

VDDO

VDD,

VDDO

VDD,

VDDO

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 10 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

Clock

Outputs

20%

80% 80%

20%

tPERIOD

tPW

tPERIOD

odc =

x 100%

tPW

BCLKx

OUTPUT RISE/FALL TIME

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIODOUTPUT SKEW

sk(o)

DDO

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 11 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

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APPLICATION INFORMATION

CRYSTAL INPUT INTERFACE

Figure 2

shows an example of ICS83905 crystal interface with a

parallel resonant crystal. The frequency accuracy can be fine

tuned by adjusting the C1 and C2 values. For a parallel crystal

with loading capacitance CL = 18pF, we suggest C1 = 15pF and

C2 = 15pF to start with. These values may be slightly fine tuned

further to optimize the frequency accuracy for different board

layouts. Slightly increasing the C1 and C2 values will slightly reduce

the frequency. Slightly decreasing the C1 and C2 values will slightly

increase the frequency. For the oscillator circuit below, R1 can be

used, but is not required. For new designs, it is recommended

that R1 not be used.

FIGURE 2. CRYSTAL OSCILLATOR INTERFACE

15p

R1 (optional)

18pF Parallel Cry stal

15p

XTAL_IN

XTAL_OUT

LVCMOS TO XTAL INTERFACE

The XTAL_IN input can accept a single-ended LVCMOS

signal through an AC couple capacitor. A general interface

diagram is shown in

Figure 3.

The XTAL_OUT pin can be left

floating. The input edge rate can be as slow as 10ns. For

LVCMOS inputs, it is recommended that the amplitude be

reduced from full swing to half swing in order to prevent signal

interference with the power rail and to reduce noise. This

configuration requires that the output impedance of the driver

(Ro) plus the series resistance (Rs) equals the transmission

line impedance. In addition, matched termination at the crystal

input will attenuate the signal in half. This can be done in one

of two ways. First, R1 and R2 in parallel should equal the

transmission line impedance. For most 50Ω applications, R1

and R2 can be 100Ω. This can also be accomplished by

removing R1 and making R2 50Ω.

FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

XTA L _ I N

XTA L _ O U T

VCC

Zo = 50

VCC

.1uf

VDD VDD

Zo = Ro + Rs

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 12 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

INPUTS:

LVCMOS CONTROL PINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVCMOS OUTPUTS

All unused LVCMOS output can be left floating. There should be

no trace attached.

FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)

VFQFN EPAD THERMAL RELEASE PATH

In order to maximize both the removal of heat from the package

and the electrical performance, a land pattern must be

incorporated on the Printed Circuit Board (PCB) within the footprint

of the package corresponding to the exposed metal pad or

exposed heat slug on the package, as shown in

Figure 4.

The

solderable area on the PCB, as defined by the solder mask, should

be at least the same size/shape as the exposed pad/slug area on

the package to maximize the thermal/electrical performance.

Sufficient clearance should be designed on the PCB between the

outer edges of the land pattern and the inner edges of pad pattern

for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat

transfer and electrical grounding from the package to the board

through a solder joint, thermal vias are necessary to effectively

conduct from the surface of the PCB to the ground plane(s). The

land pattern must be connected to ground through these vias.

The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)

are application specific and dependent upon the package power

dissipation as well as electrical conductivity requirements. Thus,

thermal and electrical analysis and/or testing are recommended

to determine the minimum number needed. Maximum thermal

and electrical performance is achieved when an array of vias is

incorporated in the land pattern. It is recommended to use as

many vias connected to ground as possible. It is also

recommended that the via diameter should be 12 to 13mils (0.30

to 0.33mm) with 1oz copper via barrel plating. This is desirable to

avoid any solder wicking inside the via during the soldering process

which may result in voids in solder between the exposed pad/

slug and the thermal land. Precautions should be taken to

eliminate any solder voids between the exposed heat slug and

the land pattern. Note: These recommendations are to be used

as a guideline only. For further information, refer to the Application

Note on the

Surface Mount Assembly

of Amkor’s Thermally/

Electrically Enhance Leadfame Base Package, Amkor Technology.

THERMAL VIA

LAND PATTERN

SOLDER PIN

SOLDER

PIN PADPIN PAD

GROUND PLANE

EXPOSED HEAT SLUG

(GROUND PAD)

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 13 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

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LAYOUT GUIDELINE

Figure 5 shows an example of ICS83905 application schematic.

In this example, the device is operated at VDD = 3.3V and VDDO =

3.3V. The decoupling capacitors should be located as close as

possible to the power pins. The input is driven by an 18pF load

resonant quartz crystal. The tuning capacitors (C1, C2) are fairly

VDD

.1uF

VDDO

ENABLE 2

100

Zo = 50 OhmVDD = 3.3V

15pf

VDD

15pF

LVCMOS

ENABLE 1

CL = 18 pf

Optional Termination

100

.1uF

LVCMOS

Zo = 50 Ohm

VDDO

ICS83905

8 9

XTA L _ O U T

ENABLE 2

GND

BCLK0

VDDO

BCLK1

GND

BCLK2 VDD

BCLK3

GND

BCLK4

VDDO

BCLK5

ENABLE 1

XTA L _ I N

10uF

VDDO = 3.3V

Unused outputs can be left floating. There should be

no trace attached to unused outputs. Device

characterized and specification limits set with all

outputs terminated.

.1uF

accurate, but minor adjustments might be required. For the

LVCMOS output drivers, two termination examples are shown in

the schematic. For additional termination, examples are shown

in the LVCMOS Termination Application Note.

FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 14 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS83905 is: 339

Pin compatible to MPC905

TABLE 7B. θ

JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 100.3°C/W 96.0°C/W 93.9°C/W

TABLE 7A. θ

JAVS. AIR FLOW TABLE FOR 16 LEAD SOIC

θθ

θJA by Velocity (Meters per Second)

012

Multi-Layer PCB, JEDEC Standard Test Boards 78.8°C/W 71.1°C/W 66.2°C/W

TABLE 7C. θ

JAVS. AIR FLOW TABLE FOR 20 LEAD VFQFN

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 57.5°C/W 50.3°C/W 45.1°C/W

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 15 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP

LOBMYS sretemilliM

muminiMmumixaM

N61

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D09.401.5

ECISAB04.6

1E03.405.4

eCISAB56.0

4.057.0

α°0°8

aaa--01.0

PACKAGE OUTLINE - M SUFFIX FOR 16 LEAD SOIC

TABLE 8A. PACKAGE DIMENSIONS FOR 16 LEAD SOIC

Reference Document: JEDEC Publication 95, MS-012

LOBMYS sretemilliM

MUMINIMMUMIXAM

N61

A53.157.1

1A01.052.0

B33.015.0

C91.052.0

D08.900.01

E08.300.4

eCISAB72.1

H08.502.6

h52.005.0

L04

.072.1

α°0°8

TABLE 8B. PACKAGE DIMENSIONS FOR 16 LEAD TSSOP

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 16 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 8C. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN

PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN

NOITAIRAVCEDEJ

SRETEMILLIMNISNOISNEMIDLLA

LOBMYSMUMINIMMUMIXAM

N02

A08.00.1

1A 050.0

3A ecnerefeR52.0

b81.003.0

eCIS

AB05.0

D0.4

2D 57.008.2

E0.4

2E 57.008.2

L53.057.0

Reference Document: JEDEC Publication 95, MO-220

NOTE: The following package mechanical drawing is a generic

drawing that applies to any pin count VFQFN package. This draw-

ing is not intended to convey the actual pin count or pin layout of

this device. The pin count and pinout are shown on the front page.

The package dimensions are in Table 8 below.

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 17 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial

applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves

the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

TABLE 9. ORDERING INFORMATION

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

MA50938SCIMA50938CIOSdaeL61ebutC°07otC°0

TMA50938SCIMA50938CIOSdaeL61leer&epat0052C°07otC°0

FLMA50938SCILMA50938CIOS"eerF-daeL"daeL61ebutC°07otC°0

TFLMA50938SCILMA5

0938CIOS"eerF-daeL"daeL61leer&epat0052C°07otC°0

GA50938SCIGA50938POSSTdaeL61ebutC°07otC°0

TGA50938SCIGA50938POSSTdaeL61leer&epat0052C°07otC°0

FLGA50938SCILGA50938POSST"eerF-daeL"daeL61ebutC°07otC°0

TFLGA50938SCILGA50938POSS

T"eerF-daeL"daeL61leer&epat0052C°07otC°0

KA50938SCIA50938NFQFVdaeL02ebutC°07otC°0

TKA50938SCIA50938NFQFVdaeL02leer&epat0052C°07otC°0

FLKA50938SCILA5093NFQFV"eerF-daeL"daeL02ebutC°07otC°0

TFLKA50938SCILA5093NFQFV"eerF-daeL"daeL02leer&epat0052C°07otC°0

NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 18 ICS83905AM REV. B JANUARY 24, 2008

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TEEHSYROTSIHNOISIVER

veRelbaTegaPegnahCfonoitpircseDetaD

A2 .margaiDgnimiTelbanEdeddA 50/82/3

BF6-A6

7-5

.tellubr

ettiJesahPSMRdedda-noitceSserutaeF

.cepsrettiJesahPSMRdedda-selbaTscitsiretcarahCCA

.tolPesioNesahPdedd

50/8/4

B9T41.rebmuntrapFL-non,POSSTdda-elbaTnoitamrofnIgniredrO 50/52/4

B11

.noitceSnoitacilppAniecafret

nItupnIlatsyrCdeddA

.tuoyalcitamehcsdeddA 50/61/5

C7T

lamrehTegakcaPNFQFVdael02tcerroc-sgnitaRmumix

aMetulosbA

.ecnadepmI

deddA

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.NFQFVdael02rofelbaTwolFriAAJatehTdetcerroC

60/2/01

deddA

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deddA

noitceshtaPesaeleRlamrehT

.egakcapNFQFV02rofgnikrameerf-daeldedda-elbaTscitsiretcarahCCA

70/9/7

BC7T-B7T

.ecnadepmIlamrehT

NFQFVdnaPOSSTdetadpU

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.ecnadepmIlamrehTNFQFVdnaPOSSTdetadpU

.eniltuOegakcaPNFQFVotetondeddA

80/42/1

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trademarks or registered trademarks used to identify products or services of their respective owners.

Printed in USA

ICS83905

LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER