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FEATURES APPLICATIONS
DESCRIPTION
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
14-BIT, 190 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
•Wireless Communications Infrastructure•Maximum Sample Rate: 190 MSPS
•Software Defined Radio•14-Bit Resolution
•Power Amplifier Linearization•No Missing Codes
•802.16d/e•Total Power Dissipation 1.1 W
•Test and Measurement Instrumentation•Internal Sample and Hold
•High Definition Video•73.2-dBFS SNR at 70-MHz IF
•Medical Imaging•87-dBc SFDR at 70-MHz IF, 0 dB gain
•Radar Systems•Double Data Rate (DDR) LVDS and ParallelCMOS Output Options•Programmable Gain up to 6 dB for SNR/SFDR
ADS5546 is a high performance 14-bit, 190-MSPSTrade-Off at High IF
A/D converter. It offers state-of-the art functionality•Reduced Power Modes at Lower Sample
and performance using advanced techniques toRates
minimize board space. Using an internal sample andhold and low jitter clock buffer, the ADC supports•Supports input clock amplitude down to
both high SNR and high SFDR at high input400 mV
PP
frequencies. It features programmable gain options•Clock Duty Cycle Stabilizer
that can be used to improve SFDR performance at•No External Reference Decoupling Required
lower full-scale analog input ranges.•Internal and External Reference Support
In a compact 48-pin QFN, the device offers fully•Programmable Output Clock position to ease
differential LVDS DDR (Double Data Rate) interfacewhile parallel CMOS outputs can also be selected.data capture
Flexible output clock position programmability is•3.3-V Analog and Digital Supply
available to ease capture and trade-off setup for hold•48-QFN Package (7 mm ×7 mm)
times. At lower sampling rates, the ADC can beoperated at scaled down power with no loss inperformance. ADS5546 includes an internalreference, while eliminating the traditional referencepins and associated external decoupling. The devicealso supports an external reference mode.
The device is specified over the industrialtemperature range (-40 °C to 85 °C).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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B0095-01
SHA 14-Bit
ADC
CLOCKGEN
Reference
Digital
Encoder
and
Serializer
Control
Interface
INP
INM
CLKP
CLKM
VCM
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D4_D5_P
D6_D7_P
D8_D9_P
D10_D11_P
D12_D13_P
D2_D3_M
D4_D5_M
D6_D7_M
D8_D9_M
D10_D11_M
D12_D13_M
OVR
ADS5546
IREF
SCLK
SEN
SDATA
RESET
OE
DFS
MODE
LVDSMODE
AVDD
AGND
DRVDD
DRGND
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
PACKAGE/ORDERING INFORMATION
(1)
SPECIFIED TRANSPORTPACKAGE- PACKAGE PACKAGE ORDERINGPRODUCT TEMPERATURE MEDIA,LEAD DESIGNATOR MARKING NUMBERRANGE QUANTITY
ADS5546IRGZT Tape and Reel,
250ADS5546 QFN-48
(2)
RGZ –40 °C to 85 °C AZ5546
ADS5546IRGZR Tape and Reel,2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θ
JA
= 25.41 °C/W (0 LFM air flow),θ
JC
= 16.5 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in (7.62 cm x 7.62cm) PCB.
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
Supply voltage range, AVDD –0.3 V to 3.9 VSupply voltage range, DRVDD –0.3 V to 3.9 VVoltage between AGND and DRGND -0.3 to 0.3 VVoltage between AVDD to DRVDD -0.3 to 3.3 VVoltage applied to VCM pin (in external reference mode) -0.3 to 1.8 VVoltage applied to analog input pins, INP and INM –0.3 V to minimum (3.6, AVDD + 0.3 V) VVoltage applied to input clock pins, CLKP and CLKM -0.3 V to AVDD + 0.3 V VT
A
Operating free-air temperature range –40 to 85 °CT
J
Operating junction temperature range 125 °CT
stg
Storage temperature range –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
SUPPLIES
Analog supply voltage, AVDD 3 3.3 3.6 VDigital supply voltage, DRVDD 3 3.3 3.6 V
ANALOG INPUTS
Differential input voltage range 2 V
PP
Input common-mode voltage 1.5 ±0.1 VVoltage applied on VCM in external reference mode 1.45 1.5 1.55 V
CLOCK INPUT
Input clock sample rate
DEFAULT SPEED mode 50 190 MSPSLOW SPEED mode 1 60Input clock amplitude differential (V
(CLKP)
- V
(CLKM)
)Sine wave, ac-coupled 0.4 1.5 V
PP
LVPECL, ac-coupled 1.6 V
PP
LVDS, ac-coupled 0.7 V
PP
LVCMOS, single-ended, ac-coupled 3.3 VInput clock duty cycle (See Figure 33 ) 35% 50% 65%
DIGITAL OUTPUTS
Maximum external load capacitance from each output pin to DRGND (LVDS andC
L
5 pFCMOS modes)R
L
Differential load resistance between the LVDS output pairs (LVDS mode) 100 ΩOperating free-air temperature –40 85 °C
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ELECTRICAL CHARACTERISTICS
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Typical values are at 25 °C, min and max values are across the full temperature range T
MIN
= –40 °C to T
MAX
= 85 °C,AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 V
PP
differential clock amplitude, 50% clockduty cycle, –1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION 14 bits
ANALOG INPUT
Differential input voltage range 2 V
PP
Differential input capacitance 7 pFAnalog input bandwidth –3 dB, source impedance 50 Ω500 MHzAnalog input common mode current
310 µA(per input pin)
REFERENCE VOLTAGES
V
(REFB)
Internal reference bottom voltage Internal reference mode 0.5 VV
(REFT)
Internal reference top voltage Internal reference mode 2.5 V∆V
(REF)
Internal reference error, V
(REFT)
- V
(REFB)
-60 ±25 60 mVV
CM
Common mode output voltage Internal reference mode 1.5 VVCM output current capability Internal reference mode ±4 mA
DC ACCURACY
No Missing Codes SpecifiedDNL Differential non-linearity –0.9 0.5 2.5 LSBINL Integral non-linearity –5 ±3 5 LSBOffset error -10 5 10 mVOffset error temperature coefficient 0.002 ppm/ °CGain error due to internal reference error alone ( ∆V
(REF)
/ 2.0V) % -3 ±1 3 %FSGain error excluding internal reference error
(1)
-2 ±1 2 %FSGain error temperature coefficient 0.01 ∆%/ °CPSRR DC Power supply rejection ratio 0.6 mV/V
POWER SUPPLY
I
(AVDD)
Analog supply current 291 mALVDS mode, I
O
= 3.5 mA,
51 mAR
L
= 100 Ω, C
L
= 5 pFI
(DRVDD)
Digital supply current
CMOS mode, F
IN
= 2.5 MHz,
43 mAC
L
= 5 pFI
CC
Total supply current LVDS mode 342 mATotal power dissipation LVDS mode 1.13 1.29 WIn STANDBY mode with clockStandby power 100 150 mWrunningClock stop power With input clock stopped 100 150 mW
(1) Gain error is specified from design and characterization; it is not tested in production.
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ELECTRICAL CHARACTERISTICS
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Typical values are at 25 °C, min and max values are across the full temperature range T
MIN
= –40 °C to T
MAX
= 85 °C,AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 V
PP
differential clock amplitude, 50% clockduty cycle, –1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC CHARACTERISTICS
F
IN
= 10 MHz 73.8F
IN
= 40 MHz 73.6F
IN
= 70 MHz 71.5 73.5F
IN
= 100 MHz 73SNR Signal to noise ratio F
IN
= 150 MHz 72.2 dBFS0 dB gain, 2 V
PP
FS
(1)
71F
IN
= 225 MHz
3 dB gain, 1.4 V
PP
FS 69.80 dB gain, 2 V
PP
FS 70F
IN
= 300 MHz
3 dB gain, 1.4 V
PP
FS 69RMS output noise Inputs tied to common-mode 1.1 LSBF
IN
= 10 MHz 90F
IN
= 40 MHz 89F
IN
= 70 MHz 77 87F
IN
= 100 MHz 84SFDR Spurious free dynamic range F
IN
= 150 MHz 84 dBc0 dB gain, 2 V
PP
FS 75F
IN
= 225 MHz
3 dB gain, 1.4 V
PP
FS 780 dB gain, 2 V
PP
FS 72F
IN
= 300 MHz
3 dB gain, 1.4 V
PP
FS 75F
IN
= 10 MHz 73.5F
IN
= 40 MHz 73.1F
IN
= 70 MHz 71 72.8F
IN
= 100 MHz 72.1SINAD Signal to noise and distortion ratio F
IN
= 150 MHz 71.8 dBFS0 dB gain, 2 V
PP
FS 69F
IN
= 225 MHz
3 dB gain, 1.4 V
PP
FS 68.50 dB gain, 2 V
PP
FS 67.8F
IN
= 300 MHz
3 dB gain, 1.4 V
PP
FS 67.5F
IN
= 10 MHz 92F
IN
= 40 MHz 91F
IN
= 70 MHz 77 90F
IN
= 100 MHz 89HD2 Second harmonic F
IN
= 150 MHz 87 dBc0 dB gain, 2 V
PP
FS 76F
IN
= 225 MHz
3 dB gain, 1.4 V
PP
FS 790 dB gain, 2 V
PP
FS 73F
IN
= 300 MHz
3 dB gain, 1.4 V
PP
FS 75
(1) FS = Full scale range
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ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
ELECTRICAL CHARACTERISTICS (continued)Typical values are at 25 °C, min and max values are across the full temperature range T
MIN
= –40 °C to T
MAX
= 85 °C,AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 V
PP
differential clock amplitude, 50% clockduty cycle, –1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
F
IN
= 10 MHz 90F
IN
= 40 MHz 89F
IN
= 70 MHz 77 87F
IN
= 100 MHz 84HD3 Third harmonic F
IN
= 150 MHz 84 dBc0 dB gain, 2 V
PP
FS 75F
IN
= 225 MHz
3 dB gain, 1.4 V
PP
FS 780 dB gain, 2 V
PP
FS 72F
IN
= 300 MHz
3 dB gain, 1.4 V
PP
FS 74F
IN
= 10 MHz 93F
IN
= 40 MHz 92F
IN
= 70 MHz 91Worst harmonic (other than HD2, HD3) F
IN
= 100 MHz 90 dBcF
IN
= 150 MHz 89F
IN
= 225 MHz 87F
IN
= 300 MHz 87F
IN
= 10 MHz 85F
IN
= 40 MHz 85F
IN
= 70 MHz 75 83THD Total harmonic distortion F
IN
= 100 MHz 81 dBcF
IN
= 150 MHz 80F
IN
= 225 MHz 72F
IN
= 300 MHz 68ENOB Effective number of bits F
IN
= 10 MHz 11.8 bitsF
IN1
= 50.09 MHz, F
IN2
= 46.09 MHz, -7 dBFS 95each toneIMD Two-tone intermodulation distortion dBFSF
IN1
= 135.08 MHz, F
IN2
= 130.08 MHz, -7 dBFS
89each tonePSRR AC power supply rejection ratio 30 MHz, 200 mV
PP
signal on 3.3-V supply 35 dBcRecovery to 1% (of final value) for 6-dB overload ClockVoltage overload recovery time 1with sine-wave input at Nyquist frequency cycles
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DIGITAL CHARACTERISTICS
(1)
TIMING CHARACTERISTICS – LVDS AND CMOS MODES
(1)
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logiclevel 0 or 1 AVDD = DRVDD = 3.3 V, I
O
= 3.5 mA, R
L
= 100 Ω
(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS
High-level input voltage 2.4 VLow-level input voltage 0.8 VHigh-level input current 33 µALow-level input current –33 µAInput capacitance 4 pF
DIGITAL OUTPUTS – CMOS MODE
High-level output voltage 3.3 VLow-level output voltage 0 VOutput capacitance inside the device, from each output toOutput capacitance 2 pFground
DIGITAL OUTPUTS – LVDS MODE
High-level output voltage 1375 mVLow-level output voltage 1025 mVOutput differential voltage, |V
OD
| 225 350 mVV
OS
Output offset voltage, single-ended Common-mode voltage of OUTP and OUTM 1200 mVOutput capacitance inside the device, from either output toOutput capacitance 2 pFground
(1) All LVDS and CMOS specifications are characterized, but not tested at production.(2) I
O
refers to the LVDS buffer current setting, R
L
is the differential load resistance between the LVDS output pair.
Typical values are at 25 °C, min and max values are across the full temperature range T
MIN
= –40 °C to T
MAX
= 85 °C, AVDD =DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 V
PP
clock amplitude, C
L
= 5 pF
(2)
, I
O
= 3.5 mA,R
L
= 100 Ω
(3)
, no internal termination, unless otherwise noted.For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this datasheet.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
a
Aperture delay 1.2 nst
j
Aperture jitter 150 fs rmsTime to valid data after coming out of
100STANDBY modeWake-up time µsTime to valid data after stopping and restarting
100the input clock
clockLatency 14
cycles
DDR LVDS MODE
(4)
t
su
Data setup time
(5)
Data valid
(6)
to zero-cross of CLKOUTP 1.2 1.7 nsZero-cross of CLKOUTP to data becomingt
h
Data hold time
(5)
0.4 0.9 nsinvalid
(6)
Input clock rising edge zero-cross to outputt
PDI
Clock propagation delay 4 4.7 5.4 nsclock rising edge zero-cross
(1) Timing parameters are specified by design and characterization and not tested in production.(2) C
L
is the effective external single-ended load capacitance between each output pin and ground.(3) I
O
refers to the LVDS buffer current setting; R
L
is the differential load resistance between the LVDS output pair.(4) Measurements are done with a transmission line of 100 Ωcharacteristic impedance between the device and the load.(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assumethat the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appearas reduced timing margin.(6) Data valid refers to logic high of +50 mV and logic low of –50 mV.
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ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this datasheet.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Duty cycle of differential clock,LVDS bit clock duty cycle (CLKOUTP-CLKOUTM) 45% 50% 55%80 ≤Fs ≤190 MSPSRise time measured from –50 mV to 50 mVt
r
, Data rise time,
Fall time measured from 50 mV to –50 mV 50 100 200 pst
f
Data fall time
1≤Fs ≤190 MSPSRise time measured from –50 mV to 50 mVt
CLKRISE
, Output clock rise time,
Fall time measured from 50 mV to –50 mV 50 100 200 pst
CLKFALL
Output clock fall time
1≤Fs ≤190 MSPSOutput enable (OE) to valid datat
OE
Time to valid data after OE becomes active 1 µsdelay
PARALLEL CMOS MODE
t
su
Data setup time
(5)
Data valid
(7)
to 50% of CLKOUT rising edge 2.2 3 ns50% of CLKOUT rising edge to data becomingt
h
Data hold time
(5)
0.5 0.9 nsinvalid
(7)
Input clock rising edge zero-cross to 50% oft
PDI
Clock propagation delay 2.4 3.2 4 nsCLKOUT rising edgeDuty cycle of output clock (CLKOUT)Output clock duty cycle 45%80 ≤Fs ≤190 MSPSRise time measured from 20% to 80% ofDRVDDt
r
, Data rise time,
Fall time measured from 80% to 20% of 0.8 1.5 2 nst
f
Data fall time
DRVDD
1≤Fs ≤190 MSPSRise time measured from 20% to 80% ofDRVDDt
CLKRISE
, Output clock rise time,
Fall time measured from 80% to 20% of 0.4 0.8 1.2 nst
CLKFALL
Output clock fall time
DRVDD
1≤Fs ≤190 MSPSOutput enable (OE) to valid datat
OE
Time to valid data after OE becomes active 50 nsdelay
(7) Data valid refers to logic high of 2 V and logic low of 0.8 V
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E E E E E E E EE E
O O O O O O O OO O
Input
Clock
CLKOUTM
CLKOUTP
OutputData
DXP,DXM
DDR
LVDS
N–14 N–13 N–12 N–11 N–10 N–1 NN+1 N+2
N–14 N–13 N–12 N–11 N–10 N N+2
14ClockCycles
14ClockCycles
CLKOUT
OutputData
D0–D13
Parallel
CMOS
Input
Signal
Sample
N
N+1
N+2 N+3 N+4
th
tPDI
ta
tsu
th
tPDI
CLKP
CLKM
N+14
N+15 N+16 N+17
tsu
E – EvenBitsD0,D2,D4,D6,D8,D10,D12
O – OddBitsD1,D3,D5,D7,D9,D11,D13 N+1N–1
T0106-01
Input
Clock
Output
Clock
Output
DataPair
CLKM
CLKOUTP
Dn_Dn+1_P,
Dn_Dn+1_M
CLKP
tPDI
tsu th
thtsu
CLKOUTM
(1)Dn – BitsD0,D2,D4,D6,D8,D10,D12
(2)Dn+1 – BitsD1,D3,D5,D7,D9,D11,D13
Dn(1) Dn+1(2)
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Figure 1. Latency
Figure 2. LVDS Mode Timing
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T0107-01
Input
Clock
Output
Clock
Output
Data
CLKM
Dn
CLKP
tPDI
tsu
th
CLKOUT
(1)Dn – BitsD0–D13
Dn(1)
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Figure 3. CMOS Mode Timing
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DEVICE PROGRAMMING MODES
USING PARALLEL INTERFACE CONTROL ONLY
USING SERIAL INTERFACE PROGRAMMING ONLY
USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
ADS5546 offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either a parallel interface control or a serial interfaceprogramming.
In addition, the device supports a third mode, where both the parallel interface and the serial control registersare used. In this mode, the priority between the parallel and serial interfaces is determined by a priority table(Table 2 ). If this additional level of flexibility is not required, the user can select either the serial interfaceprogramming or the parallel interface control.
To control the device using the parallel interface, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN,SCLK, and SDATA are used to directly control certain modes of the ADC. The device is configured byconnecting the parallel pins to the correct voltage levels (as described in Table 4 to Table 7 ). There is no needto apply reset.
In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions arecontrolled in this mode—standby, selection between LVDS/CMOS output format, internal/external reference,two's complement/straight binary output format, and position of the output clock edge.
Table 1 has a description of the modes controlled by the four parallel pins.
Table 1. Parallel Pin Definition
PIN CONTROL MODES
DFS DATA FORMAT and the LVDS/CMOS output interfaceMODE Internal or external referenceSEN CLKOUT edge programmabilitySCLK LOW SPEED mode control for low sampling frequencies (< 50 MSPS)SDATA STANDBY mode – Global (ADC, internal references and output buffers are powered down)
To program using the serial interface, the internal registers must first be reset to their default values, and theRESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and areused to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESETpin, or by a high setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes theregister programming and register reset in more detail.
Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground.
For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) canalso be used to configure the device.
The serial registers must first be reset to their default values, and the RESET pin must be kept low. In this modeSEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.The registers are reset either by applying a pulse on RESET pin or by a high setting on the <RST> bit (D1 inregister 0x6C). The serial interface section describes the register programming and register reset in more detail.
The parallel interface control pins DFS and MODE are used, and their function is determined by the appropriatevoltage levels as described in Table 6 and Table 7 . The voltage levels are derived by using a resistor string asillustrated in Figure 4 . Since some functions are controlled using both the parallel pins and serial registers, thepriority between the two is determined by a priority table (Table 2 ).
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(1/3) AVDD
(1/3) AVDD
ToParallelPin
R
AVDD
AVDDGND
R
R
(2/3) AVDD
(2/3) AVDD
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Table 2. Priority Between Parallel Pins and Serial Registers
PIN FUNCTIONS SUPPORTED PRIORITY
When using the serial interface, bit <REF> (register 0x6D, bit D4) controls this mode, ONLYMODE Internal/External reference
if the MODE pin is tied low.When using the serial interface, bit <DF> (register 0x63, bit D3) controls this mode, ONLY ifDATA FORMAT
the DFS pin is tied low.DFS
When using the serial interface, bit <ODI> (register 0x6C, bits D3-D4) controls LVDS/CMOSLVDS/CMOS
selection independent of the state of DFS pin
Figure 4. Simple Scheme to Configure Parallel Pins
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DESCRIPTION OF PARALLEL PINS
SERIAL INTERFACE
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Table 3. SCLK Control Pin
SCLK (Pin 29) DESCRIPTION
0 DEFAULT SPEED - Must be used for sampling frequency > 50 MSPSDRVDD LOW SPEED - Must be used for sampling frequency <= 50 MSPS
Table 4. SDATA Control Pin
SDATA (Pin 28) DESCRIPTION
0 Normal operation (Default)DRVDD STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.
Table 5. SEN Control Pin
SEN (Pin 27) DESCRIPTION
0CMOS mode: CLKOUT edge later by (3/12)Ts
(1)
;LVDS mode: CLKOUT edge aligned with data transition(1/3)DRVDD CMOS mode: CLKOUT edge later by (2/12)Ts
(1)
;LVDS mode: CLKOUT edge aligned with data transition(2/3)DRVDD CMOS mode: CLKOUT edge later by (1/12)Ts
(1)
;LVDS mode: CLKOUT edge earlier by (1/12)Ts
(1)
DRVDD Default CLKOUT position
(1) Ts = 1/Sampling Frequency
Table 6. DFS Control Pin
DFS (Pin 6) DESCRIPTION
0 2's complement data and DDR LVDS output (Default)(1/3)DRVDD 2's complement data and parallel CMOS output(2/3)DRVDD Offset binary data and parallel CMOS outputDRVDD Offset binary data and DDR LVDS output
Table 7. MODE Control Pin
MODE (Pin 23) DESCRIPTION
0 Internal reference(1/3)AVDD External reference(2/3)AVDD External referenceAVDD Internal reference
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After devicepower-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edgeof SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edgewhen SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded inmultiples of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits form the register data. The interface can workwith SCLK frequency from 20 MHz down to very low speeds (few Hertz) and even with non-50% SCLK dutycycle.
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REGISTER INITIALIZATION
T0109-01
Register Address RegisterData
t(SCLK) t(DSU)
t(DH)
t(SLOADS)
D7A7 D3A3 D5A5 D1A1 D6A6 D2A2 D4A4 D0A0
SDATA
SCLK
SEN
RESET
t(SLOADH)
SERIAL INTERFACE TIMING CHARACTERISTICS
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
After power-up, the internal registers must be reset to their default values. This is done in one of two ways:1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns)as shown in Figure 5 .
OR2. By applying software reset. Using the serial interface, set the <RST> bit (D1 in register 0x6C) to high.This initializes the internal registers to their default values and then self-resets the <RST> bit to low. Inthis case the RESET pin is kept low.
Figure 5. Serial Interface Timing Diagram
Typical values at 25 °C, min and max values across the full temperature range T
MIN
= –40 °C to T
MAX
= 85 °C,AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN TYP MAX UNIT
f
SCLK
SCLK frequency > DC 20 MHzt
SLOADS
SEN to SCLK setup time 25 nst
SLOADH
SCLK to SEN hold time 25 nst
DSU
SDATA setup time 25 nst
DH
SDATA hold time 25 ns
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RESET TIMING
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Typical values at 25 °C, min and max values across the full temperature range T
MIN
= –40 °C to T
MAX
= 85 °C,AVDD = DRVDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active 5 mst
2
Reset pulse width Pulse width of active RESET signal 10 nst
3
Register write delay Delay from RESET disable to SEN active 25 nst
PO
Power-up time Delay from power-up of AVDD and DRVDD to output stable 6.5 ms
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
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SERIAL REGISTER MAP
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Table 8 gives a summary of all the modes that can be programmed through the serial interface.
Table 8. Summary of Functions Supported by Serial Interface
(1) (2)
REGISTER
ADDRESS REGISTER FUNCTIONSIN HEX
A7 - A0 D7 D6 D5 D4 D3 D2 D1 D0
<DATA POSN>OUTPUT DATA <CLKOUT POSN>62
POSITION OUTPUT CLOCK POSITION PROGRAMMABILITYPROGRAMMABILITY
<LOW SPEED> <DF><STBY>
ENABLE LOW DATA FORMAT -GLOBAL63 SAMPLING 2's COMP orPOWER
FREQUENCY STRAIGHTDOWN
OPERATION BINARY
<TEST PATTERN> – ALL 0S, ALL 1s,65
TOGGLE, RAMP, CUSTOM PATTERN68 <GAIN> GAIN PROGRAMMING <GAIN> - 1 dB to 6 dB69 <CUSTOM A> CUSTOM PATTERN (D7 TO D0)6A <CUSTOM B> CUSTOM PATTERN (D13 TO D8)6B <CLKIN GAIN> INPUT CLOCK BUFFER GAIN PROGRAMMABILITY
<RST><ODI> OUTPUT DATA INTERFACE6C SOFTWARE- DDR LVDS or PARALLEL CMOS
RESET
<REF>
INTERNAL or6D <SCALING> POWER SCALING
EXTERNAL
REFERENCE
<DATA TERM> <LVDS CURR><CLKOUT TERM>7E INTERNAL TERMINATION – DATA LVDS CURRENTINTERNAL TERMINATION – OUTPUT CLOCKOUTPUTS PROGRAMMABILITY
<CURR DOUBLE>7F LVDS CURRENT
DOUBLE
(1) The unused bits in each register (shown by blank cells in above table) must be programmed as ‘0’.(2) Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Each register function is explained in detail below.
Table 9. Serial Register A
A7 - A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0
<DATA POSN>OUTPUT DATA <CLKOUT POSN>62
POSITION OUTPUT CLOCK POSITION PROGRAMMABILITYPROGRAMMABILITY
D4 - D0 <CLKOUT POSN> Output Clock Position Programmability00001 Default CLKOUT position after reset. Setup/hold timings with this clockposition are specified in the timing characteristics table.XX011 CMOS – Rising edge later by (1/12) TsLVDS – Rising edge earlier by (1/12) TsXX101 CMOS – Rising edge later by (3/12) TsLVDS – Rising edge aligned with data transitionXX111 CMOS – Rising edge later by (2/12) TsLVDS – Rising edge aligned with data transition01XX1 CMOS – Rising edge later by (1/12) TsLVDS – Rising edge earlier by (1/12) Ts10XX1 CMOS – Rising edge later by (3/12) TsLVDS – Rising edge aligned with data transition11XX1 CMOS – Rising edge later by (2/12) TsLVDS – Rising edge aligned with data transition
D6 – D5 <DATA POSN> Output Data Position Programmability (Only inCMOS mode)00 Data Position 1 - Default output data position after reset. Setup/holdtimings with this data position are specified in the timingcharacteristics table.01 Data Position 2 - Setup time increases by (2/36) Ts10 Data Position 3 - Setup time increases by (5/36) Ts11 Data Position 4 - Setup time decreases by (6/36) Ts
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ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Table 10. Serial Register B
A7 - A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0
<DF><LOW SPEED><STBY> DATAENABLE LOWGLOBAL FORMAT63 SAMPLINGPOWER 2's COMP orFREQUENCYDOWN STRAIGHTOPERATION
BINARY
D3 <DF> Output Data Format0 2's complement1 Straight binary
D4 <LOW SPEED> Low Sampling Frequency Operation0 Default SPEED mode for 50 < Fs ≤190 MSPS1 Low SPEED mode 1 ≤Fs ≤50 MSPS
D7 <STBY> Global power down0 Normal operation1 Global power down (includes ADC, internal references and output buffers)
Table 11. Serial Register C
A7 - A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0
<TEST PATTERNS>— ALL 0S, ALL 1s,65
TOGGLE, RAMP, CUSTOM PATTERN
D7 - D5 <TEST PATTERN> Outputs selected test pattern on data lines000 Normal operation001 All 0s010 All 1s011 Toggle pattern – alternate 1s and 0s on each data output and acrossdata outputs100 Ramp pattern – Output data ramps from 0x0000 to 0x3FFF by onecode every clock cycle101 Custom pattern – Outputs the custom pattern in CUSTOM PATTERNregisters A and B111 Unused
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ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Table 12. Serial Register D
A7 - A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0
68 <GAIN> GAIN PROGRAMMING <GAIN> - 1 dB to 6 dB
D3 - D0 <GAIN> Gain programmability1000 0 dB gain, default after reset1001 1 dB1010 2 dB1011 3 dB1100 4 dB1101 5 dB1110 6 dB
Table 13. Serial Register E
A7 - A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0
69 <CUSTOM A> CUSTOM PATTERN (D7 TO D0)6A <CUSTOM B> CUSTOM PATTERN (D13 TO D8)
Reg 69 D7 – D0 Program bits D7 to D0 of custom patternReg 6A D5 – D0 Program bits D13 to D8 of custom pattern
Table 14. Serial Register F
A7 - A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0
6B <CLKIN GAIN> INPUT CLOCK BUFFER GAIN PROGRAMMABILITY
D5 - D0 <CLKIN GAIN> Clock Buffer Gain110010 Gain 4, maximum gain101010 Gain 3100110 Gain 2100000 Gain1, default after reset100011 Gain 0 minimum gain
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ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Table 15. Serial Register G
A7 - A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0
<ODI> OUTPUT DATA <RST>6C INTERFACE - DDR LVDS OR SOFTWAREPARALLEL CMOS RESET
D1 <RST> Software resets the ADC1 Resets all registers to default values
D4 - D3 <ODI> Output Interface00 DDR LVDS outputs, default after reset01 DDR LVDS outputs11 Parallel CMOS outputs
Table 16. Serial Register H
A7 - A0 D7 D6 D5 D4 D3 D2 D1 D0
<REF> INTERNAL or6D <SCALING> POWER SCALING
EXTERNAL REFERENCE
D4 <REF> Reference0 Internal reference1 External reference mode, force voltage on Vcm to set reference.
D7 - D5 <SCALING> Power Scaling Modes001 Use for Fs > 150 MSPS, default after reset011 Power Mode 1, use for 105 < Fs ≤150 MSPS101 Power Mode 2, use for 50 < Fs ≤105111 Power Mode 3, use for Fs ≤50 MSPS
Table 17. Serial Register I
A7 - A0 D7 D6 D5 D4 D3 D2 D1 D0
<LVDS CURR> LVDS<DATA TERM> INTERNAL TERMINATION – <CLKOUT TERM> INTERNAL7E CURRENTDATA OUTPUTS TERMINATION – OUTPUT CLOCK
PROGRAMMABILITY
D1 - D0 <LVDS CURR> LVDS Buffer Current Programmability00 3.5 mA, default01 2.5 mA10 4.5 mA11 1.75 mA
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ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
D4 - D2 <CLKOUT TERM> LVDS Internal Termination for OutputClock Pin (CLKOUT)000 No internal termination001 325010 200011 125100 170101 120110 100111 75
D7 - D5 <DATA TERM> LVDS Internal Termination for OutputData Pins000 No internal termination001 325010 200011 125100 170101 120110 100111 75
Table 18. Serial Register J
A7 - A0 D7 D6 D5 D4 D3 D2 D1 D0
<CURR DOUBLE> LVDS7F
CURRENT DOUBLE
D7 - D6 <CURR DOUBLE> LVDS Buffer Current Double00 Value specified by <LVDS CURR>01 2x data, 2x clockout currents10 1x data, 2x clockout currents11 2x data, 4x clockout currents
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PIN CONFIGURATION (LVDS MODE)
DRGND
VCM
DRVDD
AGND
OVR
INP
CLKOUTM
INM
CLKOUTP
AGND
DFS
AVDD
OE
AGND
AVDD
AVDD
AGND
IREF
CLKP
AVDD
CLKM
MODE
AGND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DRGND
D12_D13_P
DRVDD
D12_D13_M
D0_D1_P
D10_D11_P
D0_D1_M
D10_D11_M
NC
D8_D9_P
NC
D8_D9_M
RESET
D6_D7_P
SCLK
D6_D7_M
SDATA
D4_D5_P
SEN
D4_D5_M
AVDD
D2_D3_P
AGND
D2_D3_M
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
ThermalPad
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
RGZ PACKAGE
(TOP VIEW)
Figure 7. LVDS Mode Pinout
PIN ASSIGNMENTS – LVDS Mode
PIN PIN NUMBERPIN NAME DESCRIPTION
TYPE NUMBER OF PINS
8, 18, 20,AVDD Analog power supply I 622, 24, 269, 12, 14,AGND Analog ground I 617, 19, 25CLKP, CLKM Differential clock input I 10, 11 2INP, INM Differential analog input I 15, 16 2Internal reference mode – Common-mode voltage output.VCM External reference mode – Reference input. The voltage forced on this pin sets I/O 13 1the internal references.IREF Current-set resistor, 56.2-k Ωresistor to ground. I 21 1Serial interface RESET input.When using the serial interface mode, the user MUST initialize internal registersthrough hardware RESET by applying a high-going pulse on this pin, or by usingRESET the software reset option. See the SERIAL INTERFACE section. I 30 1In parallel interface mode, the user has to tie the RESET pin permanently HIGH.(SDATA and SEN are used as parallel pin controls in this mode)The pin has an internal 100-k Ωpull-down resistor.
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ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
PIN CONFIGURATION (LVDS MODE) (continued)PIN ASSIGNMENTS – LVDS Mode (continued)
PIN PIN NUMBERPIN NAME DESCRIPTION
TYPE NUMBER OF PINS
This pin functions as serial interface clock input when RESET is low.It functions as LOW SPEED mode control pin when RESET is tied high. Tie SCLKSCLK I 29 1to LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤50 MSPS. See Table 3 .The pin has an internal 100-k Ωpull-down resistor.This pin functions as serial interface data input when RESET is low. It functionsas STANDBY control pin when RESET is tied high.SDATA I 28 1See Table 4 for detailed information.The pin has an internal 100 k Ωpull-down resistor.This pin functions as serial interface enable input when RESET is low. It functionsas CLKOUT edge programmability when RESET is tied high. See Table 5 forSEN I 27 1detailed information.
The pin has an internal 100-k Ωpull-up resistor to DRVDD.Output buffer enable input, active high. The pin has an internal 100-k Ωpull-upOE I 7 1resistor to DRVDD.Data Format Select input. This pin sets the DATA FORMAT (Twos complement orDFS Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed I 6 1information.
Mode select input. This pin selects the Internal or External reference mode. SeeMODE I 23 1Table 7 for detailed information.CLKOUTP Differential output clock, true O 5 1CLKOUTM Differential output clock, complement O 4 1D0_D1_P Differential output data D0 and D1 multiplexed, true O 34 1D0_D1_M Differential output data D0 and D1 multiplexed, complement. O 33 1D2_D3_P Differential output data D2 and D3 multiplexed, true O 38 1D2_D3_M Differential output data D2 and D3 multiplexed, complement O 37 1D4_D5_P Differential output data D4 and D5 multiplexed, true O 40 1D4_D5_M Differential output data D4 and D5 multiplexed, complement O 39 1D6_D7_P Differential output data D6 and D7 multiplexed, true O 42 1D6_D7_M Differential output data D6 and D7 multiplexed, complement O 41 1D8_D9_P Differential output data D8 and D9 multiplexed, true O 44 1D8_D9_M Differential output data D8 and D9 multiplexed, complement O 43 1D10_D11_P Differential output data D10 and D11 multiplexed, true O 46 1D10_D11_M Differential output data D10 and D11 multiplexed, complement O 45 1D12_D13_P Differential output data D12 and D13 multiplexed, true O 48 1D12_D13_M Differential output data D12 and D13 multiplexed, complement O 47 1OVR Out-of-range indicator, CMOS level signal O 3 1DRVDD Digital and output buffer supply I 2, 35 2DRGND Digital and output buffer ground I 1, 36 2NC Do not connect 31, 32 2PAD Connect the pad to ground plane. See Board Design Considerations in application 0 1information section.
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PIN CONFIGURATION (CMOS MODE)
DRGND
VCM
DRVDD
AGND
OVR
INP
UNUSED
INM
CLKOUT
AGND
DFS
AVDD
OE
AGND
AVDD
AVDD
AGND
IREF
CLKP
AVDD
CLKM
MODE
AGND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DRGND
D13
DRVDD
D12
D1
D11
D0
D10
NC
D9
NC
D8
RESET
D7
SCLK
D6
SDATA
D5
SEN
D4
AVDD
D3
AGND
D2
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
ThermalPad
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
RGZ PACKAGE
(TOP VIEW)
Figure 8. CMOS Mode Pinout
PIN ASSIGNMENTS – CMOS Mode
PIN PIN NUMBERPIN NAME DESCRIPTION
TYPE NUMBER OF PINS
8, 18, 20,AVDD Analog power supply I 622, 24, 269, 12, 14, 17,AGND Analog ground I 619, 25CLKP, CLKM Differential clock input I 10, 11 2INP, INM Differential analog input I 15, 16 2Internal reference mode – Common-mode voltage output.VCM External reference mode – Reference input. The voltage forced on this pin sets I/O 13 1the internal references.IREF Current-set resistor, 56.2-k Ωresistor to ground. I 21 1Serial interface RESET input.When using the serial interface mode, the user MUST initialize internal registersthrough hardware RESET by applying a high-going pulse on this pin, or by usingthe software reset option. See the SERIAL INTERFACE section.RESET I 30 1In parallel interface mode, the user has to tie RESET pin permanently HIGH.(SDATA and SEN are used as parallel pin controls in this mode).The pin has an internal 100-k Ωpull-down resistor.This pin functions as serial interface clock input when RESET is low.It functions as LOW SPEED mode control pin when RESET is tied high. Tie SCLKSCLK I 29 1to LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤50 MSPS. See Table 3 .The pin has an internal 100-k Ωpull-down resistor.
24
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ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
PIN CONFIGURATION (CMOS MODE) (continued)PIN ASSIGNMENTS – CMOS Mode (continued)
PIN PIN NUMBERPIN NAME DESCRIPTION
TYPE NUMBER OF PINS
This pin functions as serial interface data input when RESET is low. It functions asSTANDBY control pin when RESET is tied high.SDATA I 28 1See Table 4 for detailed information.The pin has an internal 100 k Ωpull-down resistor.This pin functions as serial interface enable input when RESET is low. It functionsas CLKOUT edge programmability when RESET is tied high. See Table 5 forSEN I 27 1detailed information.
The pin has an internal 100-k Ωpull-up resistor to DRVDD.Output buffer enable input, active high. The pin has an internal 100-k Ωpull-upOE I 7 1resistor to DRVDD.Data Format Select input. This pin sets the DATA FORMAT (Twos complement orDFS Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed I 6 1information.
Mode select input. This pin selects the internal or external reference mode. SeeMODE I 23 1Table 7 for detailed information.CLKOUT CMOS output clock O 5 1D0 CMOS output data D0 O 33 1D0 CMOS output data D1 O 34 1D2 CMOS output data D2 O 37 1D2 CMOS output data D3 O 38 1D4 CMOS output data D4 O 39 1D4 CMOS output data D5 O 40 1D6 CMOS output data D6 O 41 1D7 CMOS output data D7 O 42 1D8 CMOS output data D8 O 43 1D9 CMOS output data D9 O 44 1D10 CMOS output data D10 O 45 1D11 CMOS output data D11 O 46 1D12 CMOS output data D12 O 47 1D13 CMOS output data D13 O 48 1OVR Out-of-range indicator, CMOS level signal O 3 1DRVDD Digital and output buffer supply I 2, 35 2DRGND Digital and output buffer ground I 1, 36 2UNUSED Unused pin in CMOS mode 4 1NC Do not connect 31, 32 2PAD Connect the pad to ground plane. See Board Design Considerations in application 0 1information section.
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TYPICAL CHARACTERISTICS
-140
0
f Frequency MHz- -
Amplitude dB
-
-20
-40
-60
-80
-100
-120
SFDR=91.4dBc,
SNR=74.2dBFS,
SINAD=74dBFS
90
080
5010 403020 7060
-140
0
f Frequency MHz- -
Amplitude dB-
-20
-40
-60
-80
-100
-120
SFDR=89.2dBc,
SNR=74dBFS,
SINAD=73.7dBFS
90
080
5010 403020 7060
-140
0
f Frequency MHz- -
Amplitude dB-
-20
-40
-60
-80
-100
-120
90
080
5010 403020 7060
SFDR=87.8dBc,
SNR=73.7dBFS,
SINAD=73.3dBFS
-140
0
Amplitude dB-
-20
-40
-60
-80
-100
-120
SFDR=86.9dBc,
SNR=73.2dBFS,
SINAD=72.8dBFS
09080
5010 403020 7060
f Frequency MHz- -
-140
0
f Frequency MHz- -
Amplitude dB-
-20
-40
-60
-80
-100
-120
90
080
5010 403020 7060
SFDR=86.5dBc,
SNR=72.8dBFS,
SINAD=72.3dBFS
-140
0
f Frequency MHz- -
Amplitude dB-
-20
-40
-60
-80
-100
-120
90
080
5010 403020 7060
SFDR=85.2dBc,
SNR=72.4dBFS,
SINAD=71.9dBFS
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 V
PP
differentialclock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDSdata output (unless otherwise noted)
FFT for 10 MHz INPUT SIGNAL FFT for 40 MHz INPUT SIGNAL
Figure 9. Figure 10.
FFT for 70 MHz INPUT SIGNAL FFT for 100 MHz INPUT SIGNAL
Figure 11. Figure 12.
FFT for 130 MHz INPUT SIGNAL FFT for 150 MHz INPUT SIGNAL
Figure 13. Figure 14.
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-140
0
Amplitude dB-
-20
-40
-60
-80
-100
-120
SFDR=74dBc,
SNR=71dBFS,
SINAD=69.9dBFS
90
080
5010 403020 7060
f Frequency MHz- -
-140
0
Amplitude dB-
-20
-40
-60
-80
-100
-120
90
080
5010 403020 7060
SFDR=77.2dBc,
SNR=71.7dBFS,
SINAD=69.4dBFS
f Frequency MHz- -
-140
0
f Frequency MHz- -
Amplitude dB
-
-20
-40
-60
-80
-100
-120
90
080
5010 403020 7060
SFDR=65.6dBc,
SNR=68.7dBFS,
SINAD=62.3dBFS
-140
0
f Frequency MHz- -
Amplitude dB
-
-20
-40
-60
-80
-100
-120
90
080
5010 403020 7060
SFDR=72.1dBc,
SNR=70.1dBFS,
SINAD=66.3dBFS
-140
0
f Frequency MHz- -
Amplitude dB
-
-20
-40
-60
-80
-100
-120
90
080
5010 403020 7060
SFDR=59dBc,
SNR=66dBFS,
SINAD=56.3dBFS
-140
0
f Frequency MHz- -
Amplitude dB
-
-20
-40
-60
-80
-100
-120
90
080
5010 403020 7060
F =50.09MHz,-7dBFS,
2-ToneIMD,95dBFS
IN1
F =46.09MHz,-7dBFS,
IN2
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 V
PP
differentialclock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDSdata output (unless otherwise noted)
FFT for 200 MHz INPUT SIGNAL FFT for 225 MHz INPUT SIGNAL
Figure 15. Figure 16.
FFT for 300 MHz INPUT SIGNAL FFT for 375 MHz INPUT SIGNAL
Figure 17. Figure 18.
FFT for 500 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY
Figure 19. Figure 20.
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-140
0
Amplitude dB
-
-20
-40
-60
-80
-100
-120
90
080
5010 403020 7060
F =135.08MHz,-7dBFS,
2-ToneIMD,89dBFS
IN1
F =130.08MHz,-7dBFS,
IN2
f Frequency MHz- -
62
58
90
f InputFrequency MHz
IN - -
SFDR dBc-
500
86
82
78
74
70
66
0 40025050 200150100 350300 450
94
66
65
75
f InputFrequency MHz
IN - -
SNR dBFS-
500
74
73
72
71
70
67
0 40025050 200150100 350300 450
69
68
LVDSMode
f − InputFrequency − MHz
IN
63
64
65
66
67
68
69
70
71
72
73
74
75
10 20 30 40 50 70 100 130 230 300
SNR − dBFS
DDRLVDS
170
CMOSData
Position1
CMOSData
Position2
CMOSData
Position3
CMOSData
Position4
f − InputFrequency − MHz
IN
67
68
69
70
71
72
73
74
75
10 30 50 70 90 110 130 150 170 210 230
SNR − dBFS
190
0dB
1dB
3dB
4dB
5dB
6dB
2dB
f − InputFrequency − MHz
IN
91
92
93
95
10 30 50 70 90 110 130 150 170 210 230
SFDR − dBc
190
87
88
89
90
83
84
85
86
79
80
81
82
94
3dB
0dB
Input Adjustedto-1dBFS
forEachGainSetting
2dB
1dB
5dB 6dB
4dB
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 V
PP
differentialclock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDSdata output (unless otherwise noted)
INTERMODULATION DISTORTION (IMD) vs FREQUENCY SFDR vs INPUT FREQUENCY
Figure 21. Figure 22.
SNR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY
Figure 23. Figure 24.
SFDR vs GAIN SNR vs GAIN
Figure 25. Figure 26.
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DRV − SupplyV
DD oltage − V
85
86
87
88
89
90
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SFDR −dBc
72.4
72.8
72.0
73.2
73.6
74.0
SNR − dBFS
SNR
SFDR
f =70MHz
AV
IN
DD =3.3V
AV SupplyVoltage V
DD - -
SFDR dBc
-
SNR dBFS-
88
90
89
86
73.3
3.63.33.23.13 3.53.4
85
73.2
SFDR
SNR
87
73.6
73.1
73.4
73.5
F =70MHz
DRV =3.3V
IN
DD
85
86
87
88
89
90
SFDR −dBc
73.5
74
73
74.5
75
75.5
SNR − dBFS
SNR
SFDR
T − Free-AirT
Aemperature − C
o
−40 10 35 85
f =70MHz
IN
50−15
F − SamplingFrequency − MSPS
S
66
67
68
69
70
71
72
73
74
40 60 80 100 120 140 160 180 200
SNR − dBFS
f =70MHz
IN
PowerMode3
PowerMode2
Default
PowerMode1
74
75
76
77
78
79
80
81
82
83
84
0.34 0.64 0.94 1.24 1.54 1.84 2.14 2.44 2.74
Clock Amplitude-VPP
SFDR-dBc
70
71
72
73
74
75
SNR
SNR-dBFS
f =150MHz
SineWaveInputClock
IN
SFDR
Input Amplitude − dBFS
25
35
45
55
65
75
85
95
105
−60 −50 −40 −30 −20 −10 0
f =10MHz
IN
SFDR − dBc,dBFS
73.3
73.5
73.0
73.8
74.0
75.0
SNR − dBFS
SNR
SFDR(dBc)
SFDR(dBFS)
74.3
74.5
74.8
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 V
PP
differentialclock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDSdata output (unless otherwise noted)
PERFORMANCE vs AVDD PERFORMANCE vs DRVDD
Figure 27. Figure 28.
SNR vs SAMPLING FREQUENCYPERFORMANCE vs TEMPERATURE ACROSS POWER SCALING MODES
Figure 29. Figure 30.
PERFORMANCE vsINPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE
Figure 31. Figure 32.
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InputClockDutyCycle − %
80
82
84
86
88
90
30 35 40 45 50 55 60
SFDR −dBc
73.5
74.0
73.0
74.5
75.0
75.5
SNR − dBFS
SFDR
F =10MHz
IN
SNR
65
OutputCode
0
5
10
15
20
25
30
35
Occurence −%
8193
8194
8195
8196
8197
8198
8199
8200
8192
8191
8190
VoltageForcedontheCMPin − V
80
82
84
86
88
90
1.4 1.45 1.5 1.55 1.6
SFDR − dBc
72
73
71
74
75
76
SNR − dBFS
SFDR
SNR
f-Frequencyof ACCommon-ModeVoltage-MHz
-70
-65
-60
-45
-40
-35
0 20 40 60 80 100
CMRR − dBc
-55
-50
f − Frequency − MSPS
0
10
20
30
40
50
60
70
80
100
10 30 50 70 90 110 130 150 170
DRVDDCurrent − mA
DDRLVDS
CMOS
5-pFLoadCap
CMOS
0-pFLoadCap
CMOS
10-pFLoadCap
190
90
F − SamplingFrequency − MSPS
S
0.61
0.66
0.71
0.76
0.81
0.86
0.91
0.96
1.01
1.06
1.11
1.16
1.21
0 20 40 60 80 100 120 140 160 180 200
P − PowerDissipation −W
D
PowerMode1
PowerMode2
PowerMode3
LVDSMode
Default
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 V
PP
differentialclock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDSdata output (unless otherwise noted)
OUTPUT NOISE HISTOGRAM WITHPERFORMANCE vs INPUT CLOCK DUTY CYCLE INPUTS SHORTED TO COMMON-MODE
Figure 33. Figure 34.
PERFORMANCE IN EXTERNAL REFERENCE MODE COMMON-MODE REJECTION RATIO vs FREQUENCY
Figure 35. Figure 36.
POWER DISSIPATION vs DRVDD CURRENT vsSAMPLING FREQUENCY (DDR LVDS outputs) SAMPLING FREQUENCY (Parallel CMOS outputs)
Figure 37. Figure 38.
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60
62
62
64
64
66
66
66
68
68
68
70
70
70
72
72
72
73
73
73
74
74
74
70
50 100 150 200 250 300 350 400 450 500
56 58 60 62 64 66 68 70 72 74
10
65
100
120
140
160
190
SNR-dBFS
f -SamplingFrequency-MSPS
S
f -InputFrequency-MHz
IN
180
80
50
55
55
60
60
60
65
65
65
70
70
70
70
75
75
75
75
80
80
80
85
85
85
85
85
85
85
70
70
90
90
85
90
90
90
90
10 100 150 200 250 300 350 400 450 500
65
100
120
140
160
190
45 50 55 60 65 70 75 80 85 90 95
SFDR-dBc
f -SamplingFrequency-MSPS
S
f -InputFrequency-MHz
IN
180
80
50
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 V
PP
differentialclock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDSdata output (unless otherwise noted)
Figure 39. SNR Contour in dBFS
Figure 40. SFDR Contour in dBc
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APPLICATION INFORMATION
THEORY OF OPERATION
ANALOG INPUT
Resr
200 W
Lpkg
6nH 25 W
Sampling
Capacitor
Csamp
3.2pF
INP
INM
Cbond
2pF
50 W
Cpar1
0.8pF
Ron
10 W
Cpar2
1pF
Ron
15 W
Ron
15 W
Cpar2
1pF
50 W
4pF
Lpkg
6nH
25 W
Cbond
2pF Resr
200 W
Csamp
3.2pF
Sampling
Capacitor
Sampling
Switch
Sampling
Switch
R-C-RFilter
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
ADS5546 is a low power 14-bit 190 MSPS pipeline ADC in a CMOS process. ADS5546 is based on switchedcapacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge ofthe external input clock. Once the signal is captured by the input sample and hold, the input sample issequentially converted by a series of lower resolution stages, with the outputs combined in a digital correctionlogic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14clock cycles. The output is available as 14-bit data, in DDR LVDS or CMOS and coded in either straight offsetbinary or binary 2’s complement format.
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown inFigure 41 . This differential topology results in good ac-performance even for high input frequencies at highsampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V,available on VCM pin 13. For a full-scale differential input, each input pin (INP, INM) has to swing symmetricallybetween VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-V
PP
differential input swing. The maximum swing isdetermined by the internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Figure 41. Input Stage
The input sampling circuit has a 3-dB bandwidth that extends up to 500 MHz, see Figure 42 (measured from theinput pins to the voltage across the sampling capacitors).
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-16
-10
-8
-6
-2
0
Magnitude −dB
f − Frequency − MHz
0 500 700 1000900100
2
-4
-12
-14
300200 400 600 800
0
150
250
300
400
450
Magnitude −W
f − Frequency − MHz
0 500 700 1000900100
500
350
100
50
300200 400 600 800
200
Drive Circuit Requirements
Example Drive Circuits
INP
INM
VCM
ADT1-1WT
1:1
S11,ZI
ADS5546
25 W
25 W
5W
0.1 Fm
0.1 Fm5W
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
Transfer Function - ADC Only ADC Input Impedance, Z
I
Figure 42. Analog Input Bandwidth (Data From Actual Figure 43. Impedance Looking Into INP, INM (Data FromSilicon) Simulation)
A 5- Ωresistor in series with each input pin is recommended to damp out ringing caused by the packageparasitics. It is also necessary to present a low impedance (< 50 Ω) for the common-mode switching currents.For example, this is achieved by using two resistors from each input terminated to the common-mode voltage(VCM).
In addition to the above ADC requirements, the drive circuit may have to be designed to provide a low insertionloss over the desired frequency range and matched impedance to the source. For this, the ADC inputimpedance has to be considered, see Figure 43 .
A configuration suitable for low input frequency ranges (< 100 MHz) is shown in Figure 44 . Note the 5- Ωseriesresistors and the low common-mode impedance (using 25- Ωresistors terminated to VCM). In addition, the circuithas low insertion loss, and good impedance match at low input frequencies, see Figure 45 .
Figure 44. Configuration for Low Input Frequencies
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-9
-7
-1
1
Magnitude −dB
f − Frequency − MHz
TransferFunction − SourceTo ADCOutput
(IncludingtheTransformer)
0 250
3
-5
50 100 150 200
-3
-70
-60
-20
-10
S11 − dB
f − Frequency − MHz
S11
0 250
0
-40
50 100 150 200
-30
-50
Frequency =100MHz
S(1,1)=0.11/-1.19E2
Impedance=44.07-j8.63
S(1,1)
Frequency (100kHzto500MHz)
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
Figure 45. S11, Input Impedance and Transfer Function for the Configuration in Figure 44
For high input frequencies, the previous configuration has been modified to improve the insertion loss andimpedance matching (see Figure 46 ). The S11 curve shows that the matching is good from 100 MHz to300 MHz.
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TC4-1W TC4-1W
1:2 2:1
0.1 Fm
INP
INM
VCM
ADS5546
50 W
50 W
0.1 Fm
12nH
(Note A)
5W
5W
S11,ZI
12nH
(Note A)
-10
-8
-2
0
Magnitude −dB
f − Frequency − MHz
TransferFunction − Sourceto ADCOutput
(IncludingtheTransformer)
0 500
2
-6
50 250 350 450
-4
-25
-20
-5
S11 − dB
f − Frequency − MHz
S11
0 1000
0
-15
100 500 700 900
-10
100 150 200 300 400
200 300 400 600 800
Frequency =200MHz
S(1,1)=0.09/50.92
Impedance=55.57+j8.03
S(1,1)
Frequency (100kHzto500MHz)
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
A. Includes transformer leakage inductances.
Figure 46. Configuration for Higher Input Frequencies
Figure 47. S11, Input Impedance and Transfer Function for the Configuration in Figure 46
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Using RF Transformer-Based Drive Circuits
Using Differential Amplifier Drive Circuits
RG
RF
RF
RFIL
RFIL
CFIL
CFIL
RG
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
10 Fm
10 Fm
RS
RS T
||R
RT
+VS
CM
INP
INM
ADS5546
THS4509
VCM
500 W
200 W
200 W
5W
5W
500 W
0.1 Fm
–VS
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
For optimum performance, the analog inputs must be driven differentially. This improves the common-modenoise immunity and even order harmonic rejection. Some examples of input configurations using RFtransformers suitable for low and high input frequencies are shown in Figure 46 and Figure 47 .
The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated onthe secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by thesampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by tworesistors connected in series, with the center point connected to the 1.5 V common-mode (VCM pin 13). Thevalue of the termination resistors (connected to common-mode) has to be low (< 100 Ω) to provide alow-impedance path for the ADC common-mode switching current.
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) resultsin degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helpsminimize this mismatch, and good performance is obtained for high frequency input signals. An additionaltermination resistor pair (enclosed within the shaded box in Figure 46 ) may be required between the twotransformers to improve the balance between the P and M sides. The center point of this termination must beconnected to ground. (Note that the drive circuit has to be tuned to account for this additional termination, to getthe desired S11 and impedance match).
Figure 48 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input todifferential output that can be interface to the ADC analog input pins. In addition to the single-ended todifferential conversion, the amplifier also provides gain (10 dB in Figure 48 ). R
FIL
helps to isolate the amplifieroutputs from the switching input of the ADC. Together with C
FIL
it also forms a low-pass filter that band-limits thenoise (and signal) at the ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADCinput pins is set using two 200 Ωresistors connected to VCM.
The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADCinput pins can be biased to 1.5V. In this case, use +4 V and -1 V supplies for the THS4509 so that its outputcommon-mode voltage (1.5 V) is at mid-supply.
Figure 48. Drive Circuit Using the THS4509
See the EVM User Guide (SLWU028 ) for more information.
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Input Common-Mode
190MSPS
(310 Am ) xFs
(1)
Reference
S0165-01
VCM
REFM
REFP
INTREF
INTREF
EXTREF
Internal
Reference
ADS5546
Internal Reference
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1- µF low-inductance capacitorconnected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADCsinks a common-mode current in the order of 310 µA (at 190 MSPS). Equation 1 describes the dependency ofthe common-mode current and the sampling frequency.
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
ADS5546 has built-in internal references REFP and REFM, requiring no external components. Design schemesare used to linearize the converter load seen by the references; this and the integration of the requisitereference capacitors on-chip eliminates the need for external decoupling. The full-scale input range of theconverter can be controlled in the external reference mode as explained below. The internal or externalreference modes can be selected by controlling the MODE pin 23 (see Table 7 for details) or by programmingthe serial interface register bit <REF> (Table 16 ).
Figure 49. Reference Section
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analoginput pins.
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External Reference
Full−scale differential input pp +(Voltage forced on VCM) 1.33
(2)
Low Sampling Frequency Operation
Clock Input
S0166-01
CLKP
VCM
5kW5kW
CLKM
VCM
ADS5546
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced onthe VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differentialinput voltage corresponding to full-scale is given by Equation 2 .
In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is nochange in performance compared to internal reference mode.
For best performance at high sampling frequencies, ADS5546 uses a clock generator circuit to derive internaltiming for the ADC. The clock generator operates from 190 MSPS down to 50 MSPS in the DEFAULT SPEEDmode. The ADC enters this mode after applying reset (with serial interface configuration) or by tying SCLK pin tolow (with parallel configuration).
For low sampling frequencies (below 50 MSPS), the ADC must be put in the LOW SPEED mode. This modecan be entered by:•setting the register bit <LOW SPEED> (Table 10 ) through the serial interface, OR•tying the SCLK pin to high (see Table 3 ) using the parallel configuration.
ADS5546 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), withlittle or no difference in performance between configurations. The common-mode voltage of the clock inputs isset to VCM using internal 5-k Ωresistors as shown in Figure 50 . This allows the use of transformer-coupled drivecircuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources (Figure 51 and Figure 52 )
Figure 50. Internal Clock Buffer
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CLKP
CLKM
DifferentialSine-Wave
orPECL orLVDS
ClockInput
ADS5546
0.1 Fm
0.1 Fm
CLKP
CLKM
CMOSClockInput
ADS5546
0.1 Fm
0.1 Fm
Clock Buffer Gain
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility tocommon-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with0.1- µF capacitors, as shown in Figure 51 .
Figure 51. Differential Clock Driving Circuit
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground witha 0.1- µF capacitor, as shown in Figure 52 .
Figure 52. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-modenoise. For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpassfiltering of the clock source can help reduce the effect of jitter. There is no change in performance with anon-50% duty cycle clock input. Figure 33 shows the performance variation of the ADC versus clock duty cycle
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude isincreased. Therefore, using a large amplitude clock is recommended. In addition, the clock buffer has aprogrammable gain option to amplify the input clock. The clock buffer gain can be set by programming theregister bits <CLKIN GAIN> (Table 14 ). The clock buffer gain decreases monotonically from Gain 4 to Gain 0settings.
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Programmable Gain
Power Down
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
ADS5546 has programmable gain from 0 dB to 6 dB in steps of 1 dB. The corresponding full-scale input rangevaries from 2 V
PP
down to 1 V
PP
, with 0 dB being the default gain. At high IF, this is especially useful as theSFDR improvement is significant with marginal degradation in SNR.
The gain can be programmed using the chapter bits <GAIN> (Table 12 ).
Table 19. Full-scale Range Across Gains
Gain Corresponding full-scale range, Vpp
0 dB 2.001 dB 1.782 dB 1.593 dB 1.424 dB 1.265 dB 1.126 dB 1.00
ADS5546 has three power-down modes – global STANDBY, output buffer disabled, and input clock stopped.
Global STANDBY
This mode can be initiated by controlling SDATA (pin 28) or by setting the register bit <STBY> (Table 10 )through the serial interface. In this mode, the A/D converter, reference block and the output buffers are powereddown and the total power dissipation reduces to about 100 mW. The output buffers are in high impedance state.The wake-up time from the global power down to data becoming valid normal mode is maximum 100 µs.
Output Buffer Disable
The output buffers can be disabled using OE pin 7 in both the LVDS and CMOS modes, reducing the totalpower by about 100 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up timefrom this mode to data becoming valid in normal mode is maximum 1 µs in LVDS mode and 50 ns in CMOSmode.
Input Clock Stop
The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation isabout 100 mW and the wake-up time from this mode to data becoming valid in normal mode is maximum100 µs.
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Power Scaling Modes
Power Supply Sequence
Digital Output Information
Output Interface
DDR LVDS Outputs
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
ADS5546 has a power scaling mode in which the device can be operated at reduced power levels at lowersampling frequencies with no difference in performance. (See Figure 30 )
(1)
There are four power scaling modesfor different sampling clock frequency ranges, using the serial interface register bits <SCALING> (Table 16 ).Only the AVDD power is scaled, leaving the DRVDD power unchanged.
Table 20. Power Scaling vs Sampling Speed
Sampling Frequency Analog PowerPower Scaling Mode Analog Power in Default ModeMSPS (Typical)
> 150 Default 960 mW at 190 MSPS 960 mW at 190 MSPS105 to 150 Power Mode 1 841 mW at 150 MSPS 917 mW at 150 MSPS50 to 105 Power Mode 2 670 mW at 105 MSPS 830 mW at 105 MSPS< 50 Power Mode 3 525 mW at 50 MSPS 760 mW at 50 MSPS
(1) The performance in the power scaling modes is from characterization and not tested in production.
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies areseparated inside the device. Externally, they can be driven from separate supplies or from a single supply.
ADS5546 provides 14-bit data, an output clock synchronized with the data and an out-of-range indicator thatgoes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is providedto power down the output buffers and put the outputs in high-impedance state.
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can beselected using the DFS (see Table 6 ) or the serial interface register bit <ODI>(Table 15 ).
In this mode, the 14 data bits and the output clock are available as LVDS (Low Voltage Differential Signal)levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown inFigure 53 . So, there are 7 LVDS output pairs for the 14 data bits and 1 LVDS output pair for the output clock.
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S0169-01
CLKOUTP
D0_D1_P
D2_D3_P
D4_D5_P
D6_D7_P
D8_D9_P
D10_D11_P
D12_D13_P
OVR
Pins
OutputClock
DataBitsD0.D1
DataBitsD2,D3
DataBitsD4,D5
DataBitsD6,D7
DataBitsD8,D9
DataBitsD10,D11
DataBitsD12,D13
Out-of-RangeIndicator
CLKOUTM
D0_D1_M
D2_D3_M
D4_D5_M
D6_D7_M
D8_D9_M
D10_D11_M
D12_D13_M
ADS5546
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Figure 53. DDR LVDS Outputs
Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the falling edge of CLKOUTP and the odd databits D1, D3, D5, D7, D9, D11, and D13 are output at the rising edge of CLKOUTP. Both the rising and fallingedges of CLKOUTP have to be used to capture all the 14 data bits (see Figure 54 ).
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T0110-01
CLKOUTP
D0_D1_P,
D0_D1_M
D2_D3_P,
D2_D3_M
D4_D5_P,
D4_D5_M
D6_D7_P,
D6_D7_M
D8_D9_P,
D8_D9_M
D10_D11_P,
D10_D11_M
D12_D13_P,
D12_D13_M
D0
D2
D4
D6
D8
D10
D12
SampleN+1SampleN
D0
D2
D4
D6
D8
D10
D12
D1
D3
D5
D7
D9
D11
D13
D1
D3
D5
D7
D9
D11
D13
CLKOUTM
LVDS Buffer Current Programmability
LVDS Buffer Internal Termination
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
Figure 54. DDR LVDS Interface
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mVsingle-ended voltage swing (700-mV
PP
differential swing). The LVDS buffer currents can also be programmed to2.5 mA, 4.5 mA, and 1.75 mA using the register bits <LVDS CURR> (Table 17 ). In addition, there exists acurrent double mode, where this current is doubled for the data and output clock buffers (register bits <CURRDOUBLE> (Table 18 ).
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentiallyterminated inside the device. The termination resistances available are – 325, 200, and 170 Ω(nominal with±20% variation). Any combination of these three terminations can be programmed; the effective termination isthe parallel combination of the selected resistances. This results in eight effective terminations from open (notermination) to 75 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signalintegrity. With 100- Ωinternal and 100- Ωexternal termination, the voltage swing at the receiver end is halved(compared to no internal termination). The voltage swing can be restored by using the LVDS current doublemode. The termination can be programmed using register bits <DATA TERM> and <CLKOUT TERM>(Table 17 ).
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Parallel CMOS
CMOS Mode Power Dissipation
Output Switching Noise and Data Position Programmability (in CMOS mode ONLY)
Output Clock Position Programmability
Output Data Format
Overvoltage Signal
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
In this mode, the 14 data outputs and the output clock are available as 3.3-V CMOS voltage levels. Each databit and the output clock is available on a separate pin in parallel. By default, the data outputs are valid during therising edge of the output clock. The output clock is CLKOUT (pin 5).
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on everyoutput pin (see Figure 38 ). The maximum DRVDD current occurs when each output bit toggles between 0 and 1every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would bedetermined by the average number of output bits switching, which is a function of the sampling frequency andthe nature of the analog input signal.Digital current due to CMOS output switching = C
L
x V
DRVDD
x (N x F
AVG
)
where C
L
= load capacitance, N x F
AVG
= average number of output bits switching
Figure 38 shows the current with various load capacitances across sampling frequencies at 2MHz analog inputfrequency.
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instantof sampling and degrade the SNR. To minimize this, the device includes programmable options to move theoutput data transitions with respect to the output clock. This can be used to position the data transitions at theoptimum place away from the sampling instant and improve the SNR. Figure 24 shows the variation of SNR fordifferent CMOS output data positions at 190 MSPS.
Note that the optimum output data position varies with the sampling frequency. The data position can beprogrammed using the register bits <DATA POSN> (Table 9 ).
It is recommended to put series resistors (50 to 100 Ω) on each output line placed very close to the converterpins. This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount ofswitching noise. For example, the data in Figure 24 was taken with 50 Ωseries resistors on each output line.
In both the LVDS and CMOS modes, the output clock can be moved around its default position. This can bedone using SEN pin 27 (as described in Table 5 ) or using the serial interface register bits <CLKOUT POSN>(Table 9 ). Using this allows to trade-off the setup and hold times leading to reliable data capture. There alsoexists an option to align the output clock edge with the data transition.
Note that programming the output clock position also affects the clock propagation delay times.
Two output data formats are supported – 2's complement and offset binary. They can be selected using the DFS(pin 6) or the serial interface register bit <DF> (Table 10 ). In the event of an input voltage overdrive, the digitaloutputs go to the appropriate full scale level. For a positive overdrive, the output code is 0x3FFF in offset binaryoutput format, and 0x1FFF in 2's complement output format. For a negative input overdrive, the output code is0x0000 in offset binary output format and 0x2000 in 2's complement output format.
When the input voltage exceeds the full-scale range of the ADC, OVR (pin 3) goes high and the output codegets clamped to the appropriate full-scale level for the duration of the overload. For a positive overdrive, theoutput code is 0x3FFF in offset binary output format, and 0x1FFF in 2's complement output format. For anegative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2's complementoutput format. shows the behaviour of OVR during the overload. Note that OVR and the output code react to theoverload after a latency of 14 clock cycles.
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Output Timing
SamplingFrequency − MHz
0
10
30
50
70
100
60 80 140 160 180
OutputClockDutyCycle −%
CMOS
DDRLVDS
0 20 40 100 120
20
40
60
90
80
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
For the best performance at high sampling frequencies, ADS5546 uses a clock generator circuit to deriveinternal timing for ADC. This results in optimal setup and hold times of the output data and 50% output clockduty cycle for sampling frequencies from 80 MSPS to 190 MSPS. See Table 21 for timing information above 80MSPS.
Table 21. Timing Characteristics (80 MSPS to 190 MSPS)
(1)
t
su
DATA SETUP TIME, ns t
h
DATA HOLD TIME, ns t
PDI
CLOCK PROPAGATION DELAY, nsFs, MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
DDR LVDS
190 1.3 1.8 0.5 1 3.9 4.6 5.3
150 1.6 2.1 0.6 1.1 4.3 5 5.7
130 2.0 2.5 0.8 1.3 4.5 5.2 5.9
80 3.6 4.1 1.6 2.1 4.7 5.7 6.7
PARALLEL CMOS
190 2.5 3.3 0.8 1.2 1.9 2.7 3.5
150 2.8 3.6 1.2 1.6 1.7 2.5 3.3
130 3.3 4.1 1.7 2.1 1.1 1.9 2.7
80 6 7 3.7 4.1 10.8 12 13.2
(1) Timing parameters are specified by design and characterization and not tested in production.
Below 80 MSPS, the setup and hold times do not scale with the sampling frequency. The output clock duty cyclealso progressively moves away from 50% as the sampling frequency is reduced from 80 MSPS.
See Table 22 for detailed timings at sampling frequencies below 80 MSPS. Figure 55 shows the clock duty cycleacross sampling frequencies in the DDR LVDS and CMOS modes.
Table 22. Timing Characteristics (1 MSPS to 80 MSPS)
(1)
t
su
DATA SETUP TIME, ns t
h
DATA HOLD TIME, ns t
PDI
CLOCK PROPAGATION DELAY, nsFs, MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
DDR LVDS
1 to 80 3.6 1.6 5.7
PARALLEL CMOS
1 to 80 6 3.7 12
(1) Timing parameters are specified by design and characterization and not tested in production.
Figure 55. Output Clock Duty Cycle (typical) vs Sampling Frequency
The latency of ADS5546 is 14 clock cycles from the sampling instant (input clock rising edge). In the LVDSmode, the latency remains constant across sampling frequencies. In the CMOS mode, the latency is 14 clockcycles above 80 MSPS and 13 clock cycles below 80 MSPS.
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Board Design Considerations
Grounding
Supply Decoupling
Series Resistors on Data Outputs
Exposed Thermal Pad
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections ofthe board are cleanly partitioned. Refer to the EVM User Guide (SLWU028 ) for details on layout and grounding.
As the ADS5546 already includes internal decoupling, minimal external decoupling can be used without loss inperformance. Note that decoupling capacitors can help to filter external power supply noise, so the optimumnumber of capacitors would depend on the actual application. The decoupling capacitors should be placed veryclose to the converter supply pins.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switchingnoise from sensitive analog circuitry. In case only a single 3.3V supply is available, it should be routed first toAVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, beforebeing routed to DRVDD.
It is recommended to put series resistors (50 to 100 Ω) on each output line placed very close to the converterpins. This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount ofswitching noise.
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermalperformance. For detailed information, see application notes QFN Layout Guidelines (SLOA122 ) andQFN/SON PCB Attachment (SLUA271 ).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
Aperture Delay
Aperture Uncertainty (Jitter)
Clock Pulse Width/Duty Cycle
Maximum Conversion Rate
Minimum Conversion Rate
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Gain Error
Offset Error
Temperature Drift
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the lowfrequency value.
The delay in time between the rising edge of the input sampling clock and the actual time at which the samplingoccurs.
The sample-to-sample variation in aperture delay.
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width)to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differentialsine-wave clock results in a 50% duty cycle.
The maximum sampling rate at which certified operation is given. All parametric testing is performed at thissampling rate unless otherwise noted.
The minimum sampling rate at which the ADC functions.
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is thedeviation of any single step from this ideal value, measured in units of LSBs
The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fitof that transfer function, measured in units of LSBs.
The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error isgiven as a percentage of the ideal input full-scale range.
The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channeloutput code and the ideal average idle channel output code. This quantity is often mapped into mV.
The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degreeCelsius of the parameter from T
MIN
to T
MAX
. It is calculated by dividing the maximum deviation of the parameteracross the T
MIN
to T
MAX
range by the difference T
MAX
–T
MIN
.
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Signal-to-Noise Ratio
SNR +10Log10 Ps
PN
(4)
Signal-to-Noise and Distortion (SINAD)
SINAD +10Log10 Ps
PN)PD
(5)
Effective Number of Bits (ENOB)
ENOB +SINAD *1.76
6.02
(6)
Total Harmonic Distortion (THD)
THD +10Log10 Ps
PN
(7)
Spurious-Free Dynamic Range (SFDR)
Two-Tone Intermodulation Distortion
DC Power Supply Rejection Ratio (DC PSRR)
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
DEFINITION OF SPECIFICATIONS (continued)
SNR is the ratio of the power of the fundamental (P
S
) to the noise floor power (P
N
), excluding the power at dcand the first nine harmonics.
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as thereference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’sfull-scale range.
SINAD is the ratio of the power of the fundamental (P
S
) to the power of all the other spectral componentsincluding noise (P
N
) and distortion (P
D
), but excluding dc.
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as thereference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’sfull-scale range.
The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantizationnoise.
THD is the ratio of the power of the fundamental (P
S
) to the power of the first nine harmonics (P
D
).
THD is typically given in units of dBc (dB to carrier).
The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).SFDR is typically given in units of dBc (dB to carrier).
IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectralcomponent at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when theabsolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of thefundamental is extrapolated to the converter’s full-scale range.
The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR istypically given in units of mV/V.
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AC Power Supply Rejection Ratio (AC PSRR)
(ExpressedindBc)
DVSUP
DVOUT
10
PSRR=20Log
(8)
Common Mode Rejection Ratio (CMRR)
(ExpressedindBc)
DVCM
DVOUT
10
CMRR=20Log
(9)
Voltage Overload Recovery
ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
DEFINITION OF SPECIFICATIONS (continued)
AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ∆V
SUP
is the change inthe supply voltage and ∆V
OUT
is the resultant change in the ADC output code (referred to the input), then
CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ∆Vcm is thechange in the input common-mode voltage and ∆V
OUT
is the resultant change in the ADC output code (referredto the input), then
The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A6-dBFS sine wave at Nyquist frequency is used as the test stimulus.
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ADS5546
SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007
ADS5546 Revision history
Revision Date Description
A 11/05 Added new graphs to the Typical Characteristics.B 6/06 New Timing Characteristics table.New text for the Device Mode ConfigurationParallel Pin Control section changed to Parallel Configuration Only section.Added Serial Interface Configuration Only section.Added Configuration Using Both the Serial Interface and Parallel ControlsNew text for the Serial Interface sectionAdded Register Reset sectionAdditions to Table 8 , <RST> and <GAIN>Revised Typical Characteristics graphs.Added Programmable gain section in the Application InformationAdded DEFAULT and LOW SPEED modes to the Clock Input of the Recommended OperatingC 10/06
Conditions
Changed the max Standby power specifications.Changed the max Clock stop power specifications.Changed Analog Input information and Figures.Changed Drive Circuit and Example Drive Circuit information and Figures.Added Using RF Transformer-Based Drive Circuits information.D 4/07 Thermal Pad to pinout (Figure 7 and Figure 8 )Added graph - DRVDD CURRENT (Figure 38 )Revised Serial Register and Application InformationAdded section in Application Information - Using Differential Amplifier Drive CircuitsAdded section in Application Information - CMOS Mode Power DissipationAdded min/max specs for Offset error and Gain errorAdded Board Design Considerations in application sectionAdded Using Differential Amplifier Drive Circuits information and figure.
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PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADS5546IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ5546
ADS5546IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ5546
PADS5546IRGZT PREVIEW VQFN RGZ 48 TBD Call TI Call TI -40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 31-Oct-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS5546IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Aug-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS5546IRGZT VQFN RGZ 48 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Aug-2013
Pack Materials-Page 2
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