MC6850 ASYNCHRONOUS COMMUNICATIONS ADAPTER (ACIA) INTERFACE The MC6850 Asynchronous Communications Interface Adapter provides the data formatting and control to interface serial asynchronous data communications information to bus organized systems such as the MC6800 Microprocessing Unit, The bus interface of the MC68W includes select, enable, read/write, interrupt and bus interface logic to allow data transfer over an 8-bit bidirectional data bus. The parallel data of the bus system is serially transmitted and received by the asynchronous data interface, with proper formatting and error checking. The functional configuration of the ACIA is programmed via the data bus during system initialization. A programmable Control Register provides variable word lengths, clock division ratios, transmit control, receive control, and interrupt control. For peripheral or modem operation, three control lines are provided. These lines allow the ACIA to interface directly with the MC6860L 0-600 bps digital S SUFFIX CERDIP PACKAGE CASE 623 modem. P SUFFIX PLASTIC PACKAGE CASE 7~ L SUFFIX CERAMIC PACKAGE CASE 716 PIN ASSIGNMENT Vss I Rx Data I 2 23 ~ ~D Rx CLK I 3 22 ] DO Tx CLKI 4 21 ] D1 I 5 20 ] D2 Tx Data I 6 19 ] D3 R= ml ? 18 ] D4 Cso I 8 17 ] D5 CT2 I 9 16 ] D6 Csl [ 10 15 ] D7 RS I 11 Vccl )MOTOROLAINC., 12 1985 14 ]E 13 ] Rf~ DS9493R MWIMUM RATINGS Charatieristics Symbol Value Unit Vcc -0.3 to +7.0 v Vin -0.3 to +7.0 v TA TL to TH o to 70 -40 to +85 `c Tstg -55 to +150 `c Symbol Value Unit Supply Voltage Input Voltage Operating Temperature Range MC6850, M C68A50, MC68B50 M C~50C, MC@A50C Storage Temperature Range This device contains circuitry to protect the inputs against damage due to high static voltages or electtic fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this ti~himpedance circuit, Reliability of operaliati@ .,.~,p,% ,,+, enhanced if unused inputs are tied~@q~,~- THERMAL CHARACTERISTICS Characteristic Thermal Resistance Plastic Ceramic Cerdip 120 60 65 OJA Oclw POWER CONSIDERATIONS The average chip-junction TJ =TA+ temperature, TJ, in `C can be obtained from: (1) (PD*OJA) Where: TA= Ambient OJA = Package Temperature, Thermal ~'~.- ~~{?~?,,,,. ,C, ..,,;,. \%,*: `C Resistance, J unction-to-Am bi,~t, O&$ :: )~,1,: ~.$k$':t~ 5.> .*\ `,,,. PINT= ICC x Vcc, Watts - Chip Internal Power J,, $ y, ,~ ~:.:`> PpORT = Port Power Dissipation, Watts - ~~$,:~$~termined w PD=PINT+PpORT For most applications PpORT< PINT and can be neglected. `"~PORT ... .*:> .*F drive Darlington bases or sink LED loads. An approximate relationship may become between PD and TJ,~~$~&~:ORT is neglected) F~:.)~ a."$~ l.].:,l >,:4..$ ,,:$..? Solving equations (1) and (2) for K gives: ,t:@,j. `., .<~v.$y~ *? ,~,.j,"$~:j **$~ K= PD*(TA+2730C) +OJA*PD2 significant if the device is configured to is: PD=K+(TJ+2730C) (2) (3) Where K is a constant pertaining to ~~#&$ficular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using t&s*~~~k~f K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. ..''~?~,i> ,>~a.< ..-+\ ,,,... .:.< >... DC ELECTRICAL CHARAC S (VCC=5.O Vdc *5%, VSS=O, TA=TL to TH unless otherwise ~,~~;~,,:l:. Input High Voltage ,\*- Input Low Voltage &4$tt~,,J# R/W, CSO, CSI, CS2, _-- Enable RS, RxD, RxC, CTS, DCD DO-D7 Hi-Z (Off St%$Yfi~? Current (Vin `@?tO 2*4 V) OutputM?&JM~ltage (I@@&,205 PA, Enable Pulse Width <25 ps) $jjkq~j~= 25 vs) -100 pA, Enable Pulse Width< O~$Put Low Voltage (1Load= 1.6 mA, Enable Pulse Width< D@D7 Tx Data, ~ Internal Power Dissipation I l,, .,, .-- --. Output Capacitance (Vin=O, TA=250C, * For temperatures f=l.O m (Measured at TA=OOC) Internal Input Capacitance (vi"= 0. TA=25C. f=l.O MHz) E. Tx CLK. Rx CLK, R/~, Min Typ Max Unit VIH VSS+2.O - Vcc v vlL VSS- O.3 - VSS+O.8 v Iin -- 1.0 2.5 hA lTSl -- 2.0 10 PA - - -- - - v vo H VSS+2.4 VSS+2.4 -- vOL 25 ps} Output Leakage Current (Off State) (VOH = 2.4V) ILOH - -- PINT DO-D7 ---- -- RS, Rx Data, CSO, CSI, CS2, CTS, DCD I RTS, Tx Data mQ MHz) noted. ) Symbol Ci" "" Cout I - - : MOTOROLA Semiconductor 2 v 10 PA 300 525 * mW I 10 I 17.01 : less than TA= OC, PINT maximum will increase @ VSS+0,4 1,0 Products Inc. 12.5 7.5 10 5,0 I PF I I I pF I SERIAL DATA TIMING CHARACTERISTICS .. Data Clock Pulse Width, Min + 16, -64 Low Modes + 1 Mode (See Figure 1) Data Clock Pulse Width, -16, High + ~ + 16, +W Data Clock FrequencV +1 Data Clock-to-Data DelaV for Transmitter g pWCH ;: Modes fc - -- tTDD - Mode (See Figure 3) Receive Data Sei up Time (See Figure4) + 1 Mode tRDS Receive Data Hol Id Time (See Figure 5) -1 tRDH = Interrupt Reques t Release Time (See Figure 6) I Request-to-Send I DelaV Time (See Figure 6) I Input Rise and Fall Times FIGURE . pWCL 1 - FIGURE 3 - CLOCK (or 10% of the pulse width PULSE TRANSMIT WIDTH, DATA if smaller) Max Mode Min Max MC6BBW Min Max 280 SW - -- - -- ;; - -- -- 4W 6W - - 280 - 5m - 0.8 ~m - -- 1.0 - 7W - 6W - w - Modes + 1 Mode (See Figure 2) MC68AW MC6860 Symbol Charatieriatic - 250 - Im tl R - 1,2 - tRTS - 560 t~, tf - 1.0 - Unit "~ - 0,9 b, I:*Q. LOW-STATE OUTPUT DELAY RX Clock 7 FIGURE 6 - REQUEST-TO-SEND DELAY AND INTERRUPT-REQUEST RELEASE TIMES Enable 1 lRQ -. Note: Timing measurements are referenced m to and from a low voltage MOTOROLA of 0,8 volts and a high voltage Semiconductor 3 of 2.0 volts, unless otherwise Products Inc. noted. BUS TIMING CHARACTERISTICS Ident. Number (See Notes 1 and 2 and Figure 7) Characteristic symbol MC= Min Max MC88AW Min Max 1.0 10 MC~BW Min Max Unit 1 Cycle Time 10 0.5 Pulse Width, E Low tcyc PWEL 0.67 2 430 9m 280 9500 210 9m 10 ps ns 3 Pulse Width, E High PWEH 450 9m 280 9m 220 9W ,,:,ns 4 Clock Rise and Fall Time t~, tf - 25 - 25 - 9 Address Hold Time tA H 10 - 10 - 10 13 Address Setup Time Before E tAS 80 - 60 - 40: fJ,~~)j,})# ns 14 Chip Select Setup Time Before E tcs 80 - 60 - #g:.\,'{":* 15 Chip Select Hold Time tCH 10 - 10 -*p" ,*I Q$t$ *' - 18 Read Data Hold Time tDHR 20 50' 20 ,,$@> $.l,@ W* ns 21 Write Data Hold Time tDHW 10 - 10 ?$:$=J 10 - ns 30 Output Data Delay Time tDDR - 290 .-7;:< .!~t,, 1% - 150 ns 31 Input Data Setup Time tDSW 165 - 60 - ns -,.;''$;:,g'"~f .... i... I 5.0 Test Po(nt A RL=2.5 or `100p ~ or EqLl iv. -- = for = 30 PF for R = 11.7 DOD7 ~ ancl Tx MOTOROLA k~ = 24 k~ Data for for DO-D7 RTS Semiconductor 4 ---- PoInt MM D7000 -- @ Test Equlv. 4 J! 130PF 3 kQ MM D6150 CT R C= kQ v _---- and Tx Data Products Inc. F 20 ,t,~~wa. ::~\,&~vs ns ns FIGURE 9 - WPANDED . Transmit Clock 4 BLOCK DIAGRAM Parity Clock Gen Gen L E"ab" `4 =- -- A A Interrupt Data Request Carrier Detect Request-to-Send . Receive Data clock divider ratios, one or two stop bits, and parity (even, ---- ~pERAT:@~;,,J' ~E"lcE ..$ a number -?,;y,r,?$: ?~;!:$t variable At the bus in~erface, the ACIA,~pe#rs ~, .,,.-.$,:$,as two addressable memory locations. lnternally#fR*ei-are four registers: two :\),, read-only and two wri$e-on~::~~egisters. The read-only registers are Status a#~~& Receive Data; the write-only registers are Control a% ~?$~smit Data. The serial interface consists clocks, of serial k@&%$$nd and thr~e~@T@heral/ !?;,., ....t.\ t~})! - ,. output modem lines with control independent lines, `:*$.- MASTER @~S~$ `" The ~~$~~fi'set (CRO, CR I ) must be set immediately after pow~{;u~~flnsure the reset condition and prepare for progra~m the ACIA functional configuration when the communi~Btions channel is required. During the first master reset, the ~Q and RTS outputs are held at level 1. On all other master resets, the ~ output can be programmed \ high and R= the or low with the ~ output held high. Control bits CR5 CR6 should also be programmed to define the state of whenever master reset is utilized. After master resetting ACIA, the programmable Control Register can be set for MOTOROLA @ odd, of options word length, such as variable or none). TRANSMIT A typical transmitting sequence consists of reading the ACIA Status Register either as a result of an interrupt or in the ACIA'S turn in a polling sequence. A character may be written into the Transmit Data Register if the status read operation has indicated that the Transmit Data Register is empty. This character is transferred to a Shift Register where it is serialized and transmitted from the Transmit Data output preceded by a start bit and followed by one or two stop bits. Internal parity (odd or even) can be optionally added to the character and will occur between the last data bit and the first stop bit. After the first character is written in the Data Register, the Status Register can be read again to check for a Transmit Data Register Empty condition and current peripheral status. If the register is empty, another character can be loaded for transmission even through the first character is in the process of being transmitted (because of Semiconductor 5 Products Inc. turned off and the MPU writes into a selected Therefore, the Read/Write signal is used to select or write-only registers within the ACIA. double buffering). The second character will be automatically transferred into the Shift Register when the first character transmission is completed. This sequence continues until all the characters have been transmitted. Chip Select (CSO, CS1, CS2) - These three highimpedance TTL-compatible input lines are used to address the ACIA. The ACIA is selected when CSO and CSI ar$:high RECEIVE Data is received from a peripheral by means of the Receive Data input. A divide-by-one clock ratio is provided for an externally synchronized clock (to its data) while the divideby-16 and W ratios are Bit synchronization in itiated by the detection line in the divide-by-16 and ~is low. Transfers of data to and from the 4+@,@re then performed under the control of the En@f~JY~nal, :.~. ,* Read/Write, and Register Select. .'~&i) \\"7$j{lp.$:j*, ~$,.,, . ~::* +\~i,, provided for internal synchronization. the divide-by-16 and W modes is inof 8 or 32 low samples on the receive and W modes respectively. False start Register impedance to select bh deletion capability insures that a full half bit of a start bit has been received before the internal clock is synchronized to the bit time. As a character is being received, parity (odd or even) will be checked and the error indication will be available in the Status Register along with framing error, overrun error, and Receive Data Register full. In a typical receiving sequence, the Status Register is read to determine Select (RS) - The Register ~~f~~$ne is a highinput that is TTL compatjbl,~~#'~~gh level is used the Transmit/Receive D.~ta ;~$wkters and a low level the Control/ Status Regis~~rs.b')?~,@* Read/Write signal line is used in conjunction wit~k,~gister Select to select the read-only or write-only regi~%~~:i~~ach register pair. .* `:...,., -~,,.~,:$l. Interrupt Request (~~~,~:$ Interrupt Request is a TTL- compatible, open-dr#$;J$*b"'internal pullup), @ve low output that is used},$~ int~+rupt the MPU. The IRQ output re- if a character has been received from a peripheral. If the Receiver Data Register is full, the character is placed on the 8-bit ACIA bus when a Read Data command is received from mains low as lo~~~m.tie cause of the interrupt is present and the approp~~~~d$~'krrupt enable within the ACIA is set. The ~Q staty#$&l@t@hen high, indicates the ~output is in the active s%.~. l~$~rrup~ result from conditions in both the transmitter the MPU, When parity has been selected for a 7-bit word (7 bits plus parity), the receiver strips the parity bit (D7= O) so that data alone is transferred to the MPU. This feature reduces MPU programming. The Status Register can continue to available register. read-only f~~, `~eiver sections of the ACIA. The transmitter $$au~ an interrupt when the~ansmitter Interrupt be read to determine when another character is in the Receive Data Register. The receiver is also section Enabled ,,,,.~:$~~emdition is selected (CR5*CR6), and the Transmit Data double buffered so that a character can be read from the `S~~%egister Empty (TDRE) status bit is high. The TDRE status ,,, `s" bit indicates the current status of the Transmitter Data data register as another character is being received in the i.. shift register. The above sequence continues until .:%11 Register except when inhibited by Clear-to-Send (~) be~l>i~$.s, \ .*, 4.,. ing high or the ACIA being maintained in the Reset condicharacters have been received. ,.!:3,} `~s *-. tion. The interrupt is cleared by writing data into the Transmit Data Register. The interrupt is masked by disabling ACIA The INTERFACE ACIA bidirectional SIGNALS interfaces the Transmitter Interrupt via CR5 or CR6 or by the loss of ~ which inhibits the TDRE status bit. The Receiver section causes an interrupt when the Receiver Interrupt Enable is set and the Receive Data Register Full (R DRF) status bit is high, an Overrun has occurred, or Data Carrier Detect (~) has gone high. An interrupt resulting from the RDRF status bit can be cleared by reading data or resetting the ACIA, interrupts caused by Overrun or loss of ~ are cleared by reading the status register after the error condition has oc- FOR ~&,,@R%> to the M6~0 ~~U data bus, three chip$@~Y*$fies, with an 8-bit a register select line, an interrupt request linQw~~d#Write line, and enable line. These signals permit tkf~~ `to have complete control . ".t::\,i,\:\ ,.:. over the AC IA. -$,:!*.,lP ,,!,,~,y- ,.. ACIA Bidirectio~alfka&J?fi@ D7) - The bidirectional data lines (DO-D7) all~?&$data transfer between the ACIA and the MPU. Th%d+~~~ws output drivers are three-state devices that remai~~~~~e `high-impedance (off) state except when the MPU ~erfWms an ACIA read operation. ~:.:k.:$t,,.:.,.+: ?? curred and then reading the Receive ting the ACIA. The receiver interrupt the Receiver Interrupt Enable. CLOCK or MC6809 frequencies selected. of 1, 16, or M times the Read/Write (R/~) - The Read/Write line is a highimpedance input that is TTL compatible and is used to con- MOTOROLA rate may be Receive Clock (Rx CLK) - The Receive Clock input is used for synchronization of received data. (In the + 1 mode, the clock and data must be synchronized externally. ) The receiver samples the data on the positive transition of the clock. ACIA'S input/outis high (MPU Read on and a selected output drivers are -- @ data Transmit Clock (Tx CLK) - The Transmit Clock input is used for the clocking of transmitted data. The transmitter initiates data on the negative transition of the clock. E clock. trol the direction of data flow through the put data bus interface. When Read/Write cycle), ACIA output drivers are turned register is read. When it is low, the ACIA INPUTS Separate high-impedance TTL-compatible inputs are provided for clocking of transmitted and received data. Clock E, is a high~QIA~~#able (E) - The Enable signal, im~~~&ce TTL-compatible input that enables the bus inputF&utput data buffers and clocks data to and from the ACIA. This signal will normally be a derivative of the MC6800 42 Clock Data Register or resetis masked by resetting Semiconductor 6 Products Inc. been read. The reset. Character RDRF bit remains set until the Overrun is synchronization is maintained during the Overrun condition. The Overrun indication reading of data from the Receive Data Master Reset. character is in the RDR. If no parity is selected, then both the transmitter parity generator output and the receiver partiy check results are inhibited. is reset after the Register or by a Interrupt Request (~Q), Bit 7 - The ~ bit indicates the state of the ~ output. Any interrupt condition with its applicable enable will be indicated in this status bit. An~time the IRQ output is low the mbit will be high to indi~L~~he Pafity Error (PE), Bit 6 - The parity error flag indicates that the number of highs (ones) in the character does not agree with the preselected odd or even parity. Odd parity is defined to be when the total number of ones is odd. The parity error indication will be present Package Type as long as the interrupt data status. Frequency (MHz) Temperature I 1.0 1.0 1.5 1.5 2.0 Ooc to 70"C 1.0 1.0 1.5 1.5 2.0 0 0c:.$q,,70ocd~ - ~C ~i,850C #~F\Q 70c S{$h* to 85C WJWWQC to 700c Plastic P suffix 1.0 1.0 .,ip `:' 1.5+$ -'~':a> li@,>rk `" I '3' O"c to 700c -40C to 85C Ooc to 70"C -40C to 85C Semiconductor is cleare@~~~$$~read or a ~~if~b~~gration ,.,,.lm. ! ,.,::~i,.$,~., ~.+, :;%3,3K$<X ` ,..i..~'~ , ,,F~,> <.?.,t::~ ` `...$l.,:+ ,:w>..,>.~ ,,.$:, *.?l:b*,P~ >.~,,,,.$, ~` "'+q:t,,,:,:;: "~~:\ ,, w~umber M C68A50CL MC68E50C Cerdip s suffix MOTOROLA ~ Data Register Data Register, 9 -- request to the Receive to the Transmit Ceramic L Suffix m or service operation M C6850S MC6850CS MC68A50S MC68A50CS MC68B50S MC6850P M C6850C P MC68A50P MCMA50CP Products Inc. CONTROL STATUS REGISTER The ACIA Control Register consists ofeight Counter Divide Select Request-to-Send peri - Bits (CRO and CR I ) - The Counter ACIA. Additionally, these bits are used to provide a master reset for the ACIA which clears the Status Register (except for external conditions on ~and DCD) and initializes both being power fail/restart, these bits must be set high to reset the ACIA. After resetting, the clock divide ratio maybe selected. These counter select bits provide for the following clock CRO Function 0 1 _1 1 1 0 1 high also causes Transmit Data +16 +M Master Reset D.@&ct && will CR3 CR2 o 0 o 0 0 1 0 1 0 o 1 1 1 0 0 0 1 0 1 1 1 Word buffered 1 1 length, Parity and therefore $Y g'~ng `???~tien Even Parity+2 Stop Bits !? $$ ~~~ $\.:i Odd Parity+ 2 Stop Bits$~& Even Paritv + 1 Stop, ~~~;t,~$, ..$,,,., Odd ParitV+ 1 stQ#e~t<l~. ~.,'. -.. >.} .\~. ,~ Stop Bits ~'"i, *.\\,,?~w 8 Bits+ 1 Stop Bit ~R,~~$, ~ 8 Bits+ Even parit~~$$:$~@p Bit 8 Bits+ Odd Pa~~~~$~t,~top Bit ,:..!..., ,~.i.,.,,!:.' ~, 1 Bits+ Bits+ Bits+ Bits+ 8its+2 Select, a~~$$~o~ becom~"eff~~ve ..,*:; . '33 ,<V, w>),;? CR6 The f~t~~~~~ encoding ~*~R'$Je " Function a modem This bit after the DCD input is returned low until cleared by first readina the Status Resister and then the Data Resister or until a master reset occurs. If the ~D input remains high Receiver Overrun (OVRN), the Bit 5 - Overrun time that the is an error flag that indicates that one or more characters in the data stream were lost. That is, a character or a number of characters were received but not read from the Receive Data Register (RDR) prior to subsequent characters being received. The overrun condition begins at the midpoint of the last bit of the second character received in succession without a read of the RDR having occurred. The Overrun does not occur in the Status Register until the valid character prior to Overrun has Full, Overrun, Detect (~) MOTOROLA from high causes an Interrupt Request to be generated the~eive Interrupt Enable is set. It remains high ror indicator is present throughout associated character is available. Receive Interrupt Enable Bit (CR7) - The following interrupts will be enabled by a high level in bit position 7 of the @ input Framing Error (FE), Bit 4 - Framing error indicates that the received character is improperly framed by a start and a stop bit and is detected by the absence of the first stop bit, This error indicates a synchronization error, faulty transmission, or a break condition. The framing error flag is set or reset during the receive data transfer time. Therefore, this er- is used: (CR7): Receive Data Register transition on the Data Carrier the ~ that a carrier is not present. bit is inhibited and the Clear-to-Send status bit will be high. Master reset does not affect the Clear-to-Send status bit. ~= low, Transmitting Interrupt Disabled. ~= low, Transmitting Interrupt Enabled, ~= high, Transmitting Interrupt Disabled. RTS = low, Transmits a Break level on the Transmit Data Output. Transmitting interrupt Disabled. Control Register or a low-to-high signal line. The Clear-to-Send (=), Bit 3 - The Clear-to-Send bit indicates the state of the Clear-to-Send input from a modem. A low = indicates that there is a Clear-to-Send from the modem. In the high state, the Transmit Data Register Empty Bit changes are not immediately. format 1 - after read status and read data or master reset has occurre~, the interrupt is cleared, the DCD status bit remains high and will follow the ~ input. Transmitter Control Bit#~.&l~$ and CR6) - Two Transmitter Control bits prov[%~''f.or the control of the interrupt from the Transmit Data R~@#;~@Empty condition, the Request-toSend (~) outRNt&}& the transmission of a Break level (space). be high when :$.Q~S&Qne high to indicate `g~? .. Function 7 7 7 7 8 RDRF ~ inti~ate empty. ,'j''.:i,>,>, ,?*, .<. .{,.>.,.., Regi,~$$P@p& (TDRE), Bit dicates that t~~$l~~ter is full and that transmission of a new character ,~a~$~~i begun since the last write data command. ., ~*,' .;::.?, >~~1$ ; .." * \,$ Dat&~::#arrler Detect (~D), Bit 2 - The Data Carrier Word Select Bits (CR2, CR3, and CR4) - The Word Select bits are used to select word length, parity, and the number of stop bits. The encoding format is as follows: CR4 to the Transmit Data Regis~h:@fi@ty bit being set high indicates that the Transmit Q~@l~@gister contents have been trans,.,..... ,,..,, ferred and that,~ew ~ta may be entered, The low state in- divide ratios: o 0 is available M PU read of the Receive Data Regisl,@,~r by% master reset. The cleared or empty state indicat~$$~$~@'e contents of the Receive Data Register are not c@i$fen$. `bata Carrier Detect Master reset does not affect Note that after power-on or a CR1 of the ACIA Receive Data Register Full (RDRF), Bit O.= ~~~<$}e Data Register Full indicates that received dat~:fi~~'''b~en transferred to the Receive Data Register. R D~~,@*~{&9red after an Divide Select Bits (CRO and CRI) determine the divide ratios utilized in both the transmitter and receiver sections of the the receiver and transmitter. other Control Register bits. on the status MPU by reading the ACIA Status Register. This read-only register is selected when RS is low and R/~ is high. information stored in this register indicates the status of the Transmit Data Register, the Receive Data Register and error logic, and the peripheral/modem status inputs of ,$$$CIA. .:;? ~>b.'`"i only buffer that are selected when RS and Rl~are low. This register controls the function of the receiver, transmitter, interrupt enables, and the pheral/modem control output. REGISTER Information bits of write- Semiconductor 8 Products Inc. LINES ACIA REGISTERS Receive Data (Rx Data) - The Receive Data line is a highimpedance TTL-compatible input through which data is received in a serial format, Synchronization with a clock for detection of data is accomplished internally when clock rates of 16 or W times the bit rate are used. The expanded block diagram for the ACIA indicates the internal registers on the chip that are used for the status, control, receiving, and transmitting of data. The content of each of the registers is summarized in Table 1. SERIAL lNPUT/OUTPUT .! ,. A),,),, l.~:~.:. *L~\,\. ,,,.~t:l$:> `J..\+,,, Data is written in the Transmit Data Register.l#~~~& the negative transition of the enable (E) when the A~~~~$@%been addressed with RS high and Rl~ low. Wti@fi$:,Q~ta into the register causes the Transmit Data Regis~@r~P~@~ybit in the Status Register to go low. Data can th&~$,@transmitted. If the transmitter is idling and no ch~'c$~~~ being transmitted, then the transfer will take p!~ce'~~~fiin l-bit time of the trailing edge of the Write com~~d. If a character is being t,,..~\a!i*. transmitted, the new data <~;~{wter will commence as soon as the previous characte~~%.tqtiplete. The transfer of data causes the Transmit Da~~,R#ster Empty (TDRE) bit to in:+;~~\y\..T\ ~h dicate empty. ,:},,.\ .,$t..= ., ,<!~j, RECEIVE DAT~~&~WSTER (RDR) ~t+<t:t??>:.,' .::, Data is a~to~t[cally transferred to the empty Receive Data Regf$~$*t#DR) from the receiver deserializer (a shift regist~r) "~~~n receiving a complete character. This event caq*, the `Receive Data Register Full bit (RDRF) in the $$at~s%uffer to go high (full). Data may then be read TRANSMIT Transmit Data {Tx Data) - The Transmit Data output line transfers serial data to a modem or other peripheral. . PERIPHERAL/MODEM CONTROL The ACIA includes several functions that permit limited control of a peripheral or modem. The functions included are Clear-to-Send, Request-to-Send and Data Carrier Detect. Clear-to-Send (~) - This high-impedance TTLcompatible input provides automatic control of the transmitting end of a communications link via the modem Clear-toSend active low output by inhibiting the Transmit Data Register Empty (TDRE) status bit. Request-to-Send (~S) - The Request-to-Send output enables the MPU to control a peripheral or modem via the data bus. The RTS output corresponds to the state of the Control Register bits CR5 and CR6, When CR6= O or both CR5 and CR6= 1, the ~ output is low (the active state). This output can also be used for Data Terminal Ready (DTR). DATA REGISTER (TDR) ~$,~~o,@h the bus by addressing the ACIA~nd selecting the Data Carrier Detect (~D) - This high-impedance TTL~,:~~Q~Uelve Data Register with RS and R/W high when the compatible input provides automatic control, such as in the `v*~t&'&CIAis enabled. The non-destructive read cycle causes the ,+,r. RDR F bit to be cleared to empty although the data is rereceiving end of a communications link by means of a modem Data Carrier Detect output. The ~ input inhi~$, tained in the RDR. The status is maintained by RDRF as to and initializes the receiver section of the ACIA when hig&$,,~-*!~ whether or not the data is current. When the Receive Data low-to-high transition of the Data Carrier Detect ini~-;$p Register is full, the automatic transfer of data from the interrupt to the MPU to indicate the occurrence ~$~!o% of Receiver Shift Register to the Data Register is inhibited and the RDR contents remain valid with its current status stored carrier when the Receive Interrupt ~ble bi~$$~~f+' The Rx CLK must be running for proper DCD ~iw$~. in the Status Register. $!,.. .,.'.~.~. .{J. l.,:?..,%>,:, ..,>.+:$ ~,.i"..:,:<~ .,.`>.. *...'. ..,. ,,\w;~~~$lE 1 - DEFINITION OF ACIA REGISTERCONTENTS .,.r .:,~. \:.,.. ,., ..,:~, ~.,.;4 .' Buffer Address ,<::' `~'J t.. ~~ Rs R/m "~>q.$:$ G Ts. m Bus , ,~'~ ~.,.! .,.? Line );> ~>~ :$: .l}:,:. Data NU*t;~ ",.., J'\@* ,+,3{ . * \>~~\ :$\{,$@&;;'" *,\$l$\ \*,~..,, ~ 8,, .~.t' *i. " , .:.,:\:i`%::,,C3${, ." ~ .,,:{ .<,:*:...\>\:),), `~"i. 2 ~ii:';":s r.:.++;,,, ,,v k;j ~) . . \A\> 3 "f Transmit Data Data Control Status Register Register Register Register (Write Data Only) Bit (Read 0. Oata (Write Only) Bit Select Data Data Bd Bit Data 1 2 Data Bitl Bit OnIV) Counter O Di"ide Select2 (c RI) Select Transm, Bit 3 Data Word B!t 3 Data Bit 4 Data Blt Word 4 1 Data Data Bit 5 Data B,t 5 Transm)t Data Bit 6 Data Select 2 Clear-to-Send (CTS) Select Fram, 3 ng Error (FE) Control Transm!t Bit 6 Detect (DCD) 1 (CR5) 6 Reg!ster (T DRE) Carrier (CR4; 5 Register t Data Empty (CR2) Data OnIv) Data F"II{RDRF) 1 (CRO) Counter Word 2 (Read Recei"e D!vide (CR3) 4 Ws R/fi Receive Receiver Overrun (OVRN) Control 2 Par, tV Error [PE) (CR6) Data 7 Bit 7.*' Data Bit Rece, ve l"terr"~t 7.* Enable ` Leading " ` Oata `" ` Data bit bit bit = LSB = Bit Interrupt Request (~Q) O will be zero in 7-bit plus parity modes. modes. is "don't care" in 7-bit plus paritv MOTOROLA @ (CR7) Semiconductor 7 Products Inc. PACKAGE DIMENSIONS nnnnnnmnnnnn 24 CASE 6~-~ (CERDIPI 13 IT DIM A B c o F o J K L M N MI LLIMETE2S[ MIN [ MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 6SC 0.20 0.30 4.06 2.29 15.24 BSC 00 ,~o INCHES MIN MAx 1.230 1,290 0.500 0,610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 6SC 0.008 0.012 0.090 0.160 0.600 6SC ,50 00 w" 0.51 1.27 0.020 NOTES: 1. DIM "~' TO CENTER OF LEAOSWHEN FORMEO PARALLEL, 2. LEAOSWITHIN 0.13 mm (0.005] RAOIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONOITION. (WHEN FORMED PARALLEL) oIM/ MIN I MAX I 13137 132.13 I B I 13,72 I 14.22 I 3.94 I c o I 0.36 \ c r , ,". ,,..' c ?q~ RTC :!.4 "S1.PdSITIONALT OLEflANc EOFLEAOs( 0), Ml N MA, ,, `" "...:~:,j$>:~, 1.23511 .2.@, s SHALL 6EWlTHl N025mm(0.OIO)AT ,:.:. 0,540]Q MAXIMUM MATERIAL CONDITION, IN y,: .<* RELATION TO SEATING PLANE AND )!. ` EACH OTHER. "."+" .*" d 100 .6 "''.0.00 `&l15 4 2 DIMENSION LTOCENTEROFLEAOS WHEN FORMEO PARALLEL. c 0.080 0.015 0.135 3, DIMENSION BOO ES NOT IN CLUOEMOLO FLASH, 0.050 ... H - .,". !--, ,.. ,.. "= - NOTE: 1. LEAOSTRUE POSITIONED WITHIN 0.25mm (0.010) OIA (AT SEATING PLANE) AT MAXIMUM MATERIAL CONOITION, 2. OIM''L''TO CENTER OF LEAOS WHEN FORMEO PARALLEL. Motorola reserves the right out of the application to make changes oruseof anvproduct to any products or circuit MOTOROLA herein described to improve herein; ne!ther reliability, does Semiconductor @ function or design. ifconvevanyl;cense Motorola under P.1~~ IX "S. 4-85 lm~,.. .1,"0 ,30469 18,000 not assume rights any Iiabilityarising northerights of others. Products Inc. 3501 ED BLUESTEIN BLVD., AUSTIN, TEXAS 78721 .,!225-7 does itspatent A SUBSIDIARY OF MOTOROLA INC ,$9,93.4