MC6850S - Motorola / Freescale Semiconductor

ASYNCHRONOUS COMMUNICATIONS INTERFACE

ADAPTER (ACIA)

The MC6850 Asynchronous Communications Interface Adapter pro-

vides the data formatting and control to interface serial asynchronous

data communications information to bus organized systems such as the

MC6800 Microprocessing Unit,

The bus interface of the MC68W includes select, enable, read/write,

interrupt and bus interface logic to allow data transfer over an 8-bit

bidirectional data bus. The parallel data of the bus system is serially

transmitted and received by the asynchronous data interface, with pro-

per formatting and error checking. The functional configuration of the

ACIA is programmed via the data bus during system initialization. A

programmable Control Register provides variable word lengths, clock

division ratios, transmit control, receive control, and interrupt control.

For peripheral or modem operation, three control lines are provided.

These lines allow the ACIA to interface directly with the MC6860L

0-600 bps digital modem.

●

MC6850

SSUFFIX

CERDIP PACKAGE

CASE 623

PSUFFIX

PLASTIC PACKAGE

CASE 7~

LSUFFIX

CERAMIC PACKAGE

CASE 716

Vss I

Rx Data I

Rx CLK I

Tx CLKI

R= I

Tx Data I

Cso I

CT2 I

Csl [

RS I

Vccl

PIN ASSIGNMENT

23 ~~D

22 ]DO

21 ]D1

20 ]D2

19 ]D3

18 ]D4

17 ]D5

16 ]D6

15 ]D7

14 ]E

13 ]Rf~

)MOTOROLAINC., 1985 DS9493R

MWIMUM RATINGS

Charatieristics Symbol Value Unit This device contains circuitry to protect the

Supply Voltage Vcc –0.3 to +7.0 vinputs against damage due to high static

Input Voltage Vin –0.3 to +7.0 vvoltages or electtic fields; however, it is ad-

Operating Temperature Range TL to TH vised that normal precautions be taken to

MC6850, MC68A50, MC68B50 TA oto 70 ‘c avoid application of any voltage higher than

MC~50C, MC@A50C –40 to +85 maximum rated voltages to this ti~h-

Storage Temperature Range Tstg –55 to +150 ‘c impedance circuit, Reliability of operaliati@

.,.~,p,%,,+,

enhanced if unused inputs are tied~@q~,~-

THERMAL CHARACTERISTICS

Characteristic Symbol Value Unit

Thermal Resistance

Plastic OJA 120

Ceramic 60 Oclw

Cerdip 65

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in ‘C can be obtained from:

TJ =TA+ (PD*OJA)

Where: (1)

,C,

~’~.-

TA= Ambient Temperature, ‘C ~~{?~?,,,,.

..,,;,.\%,*:

OJA =Package Thermal Resistance, Junction-to-Am bi,~t, O&$w

PD=PINT+PpORT :: )~,1,:

~.$k$’:t~5.> ‘,,,.

.*\

PINT= ICC xVcc, Watts –Chip Internal Power J,, $

y, ,~~:.:‘>

PpORT =Port Power Dissipation, Watts –~~$,:~$~termined

For most applications PpORT< PINT and can be neglected. ‘“~PORT may become significant if the device is configured to

drive Darlington bases or sink LED loads. ...

.*:> .*F

An approximate relationship between PD and TJ,~~$~&~:ORT is neglected) is:

PD=K+(TJ+2730C) F~:.)~

a.“$~l.].:,l>,:4..$ (2)

,,:$..?

Solving equations (1) and (2) for Kgives: ,t:@,j. ‘.,

.<~v.$y~

K= PD*(TA+2730C) +OJA*PD2 *? (3)

,~,.j,“$~:j**$~

Where Kis aconstant pertaining to ~~#&$ficular part. Kcan be determined from equation (3) by measuring PD (at

equilibrium) for aknown TA. Using t&s*~~~k~f K, the values of PD and TJ can be obtained by solving equations (1) and (2)

iteratively for any value of TA. ..’’~?~,i>

,>~a.<..-+\,,,...

.:.< >...

DC ELECTRICAL CHARAC S(VCC=5.O Vdc *5%, VSS=O, TA=TL to TH unless otherwise noted. )

Symbol

~,~~;~,,:l:. Min Typ Max Unit

Input High Voltage ,\*- VIH VSS+2.O –Vcc v

Input Low Voltage &4$tt~,,J# vlL VSS– O.3 –VSS+O.8 v

R/W, CSO, CSI, CS2, Enable

_—

RS, RxD, RxC, CTS, DCD Iin —1.0 2.5 hA

Hi-Z (Off St%$Yfi~? Current DO-D7

(Vin ‘@?tO 2*4 V) lTSl —2.0 10 PA

OutputM?&JM~ltage

(I@@&,- 205 PA, Enable Pulse Width <25 ps) D@D7 vo HVSS+2.4 ––v

$jjkq~j~= -100 pA, Enable Pulse Width< 25 vs) Tx Data, ~VSS+2.4 ––

O~$Put Low Voltage (1Load= 1.6 mA, Enable Pulse Width< 25 ps} vOL — — VSS+0,4 v

Output Leakage Current (Off State) (VOH =2.4V) mILOH –1,0 10 PA

Internal Power Dissipation (Measured at TA=OOC) PINT —300 525*mW

Internal Input Capacitance

(vi”= 0. TA=25°C. f=l.O MHz) DO-D7 Ci” –I10 I12.5 IPF I

Il,, .,, .— —. E. Tx CLK. Rx CLK, R/~, RS, Rx Data, CSO, CSI, CS2, CTS, DCD I““ I–

—— — 17.01 7.5 I I

Output Capacitance

(Vin=O, TA=250C, f=l.O MHz) RTS, Tx Data Cout : : 10

mQ 5,0 pF I

*For temperatures less than TA= O°C, PINT maximum will increase

@MOTOROLA Semiconductor Products Inc.

SERIAL DATA TIMING CHARACTERISTICS

Charatieriatic Symbol MC6860 MC68AW MC6BBW

Min Max Min Max Min Max Unit

Data Clock Pulse Width, Low +16, -64 Modes 280 –“~

(See Figure 1) +1Mode pWCL g–;; –SW

———

Data Clock Pulse Width, High -16, + ~ Modes —4W – 280 –

pWCH ;: –6W –5m –

(See Figure 2) +1Mode

Data Clock FrequencV +16, +W Modes 0.8 –

fc –~m 1.0 –

+1 Mode — — 7W –

Data Clock-to-Data DelaV for Transmitter (See Figure 3) tTDD –6W –w–

up Time (See Figure4) +1Mode tRDS

Id Time (See Figure 5) -1 Mode tRDH 250 – Im –

tRelease Time (See Figure 6) tl R–1,2 –0,9 b,

IDelaV Time (See Figure 6) tRTS – 560

IInput Rise and Fall Times (or 10% of the pulse width if smaller) t~, tf –1.0 –I:*Q.

Receive Data Sei

Receive Data Hol

Interrupt Reques

IRequest-to-Send

FIGURE 1 – CLOCK PULSE WIDTH, LOW-STATE

FIGURE 3 – TRANSMIT DATA OUTPUT DELAY

Note: Timing measurements are

RX Clock

FIGURE 6 – REQUEST-TO-SEND DELAY AND

INTERRUPT-REQUEST RELEASE TIMES

Enable

lRQ

referenced to and from alow voltage of 0,8 volts and ahigh voltage of 2.0 volts, unless otherwise noted.

mMOTOROLA Semiconductor Products Inc.

BUS TIMING CHARACTERISTICS (See Notes 1 and 2 and Figure 7)

Ident. Characteristic MC=

symbol Min Max MC88AW MC~BW

Number Min Max Min Max Unit

1Cycle Time tcyc 1.0 10 0.67 10 0.5 10 ps

2Pulse Width, ELow PWEL 430 9m 280 9500 210 9m ns

3Pulse Width, EHigh PWEH 450 9m 280 9m 220 9W ,,:,ns

4Clock Rise and Fall Time t~, tf – 25 – 25 – 20 ,t,~~wa.

9Address Hold Time tA H10 – 10 – 10 ::~\,&~vs

13 Address Setup Time Before EtAS 80 – 60 – 40: fJ,~~)j,})# ns

14 Chip Select Setup Time Before Etcs 80 – 60 – #g:.\,’{”:* ns

15 Chip Select Hold Time tCH 10 – 10

18 –*p” ,*I Q$t$*’ –ns

Read Data Hold Time tDHR 20 50’ 20 ,,$@> $.l,@ W* ns

21 Write Data Hold Time tDHW 10 – 10 ?$:$=J10 – ns

30 Output Data Delay Time tDDR – 290 .-7;:< 1% – 150 ns

.!~t,,

31 Input Data Setup Time tDSW 165 -,.;’’$;:,g’”~f -60 -ns

.... i...

ARL=2.5 kQ

Test Po(nt MM D6150

or Equlv. Test PoInt

CT R~

‘100p F

MM D7000

or EqLl iv.

—

—=

C= 130PF for DOD7 R=11.7 k~ for DO-D7

=30 PF for ~ancl Tx Data =24 k~ for RTS and Tx Data

@MOTOROLA Semiconductor Products Inc.

—— _——

5.0 v

3kQ

FIGURE 9 – WPANDED BLOCK DIAGRAM

Transmit Clock 4Clock Parity

E“ab” ‘4 =- —

Gen Gen

A A

——

~E”lcE ~pERAT:@~;,,J’

-?,;y,r,?$:

..$ ?~;!:$t

At the bus in~erface, the ACIA,~pe#rs as two addressable

~,.,,.-.$,:$,

memory locations. lnternally#fR*ei-are four registers: two

:\),,

read-only and two wri$e-on~::~~egisters. The read-only

registers are Status a#~~& Receive Data; the write-only

registers are Control a% ~?$~smit Data. The serial interface

consists of serial k@&%$$nd output lines with independent

clocks, and thr~e~@T@heral/ modem control lines,

!?;,.,.\ t~})!,

....t -.

‘:*$.-

MASTER @~S~$ ‘“

The ~~$~~fi’set (CRO, CR I)must be set immediately after

pow~{;u~~flnsure the reset condition and prepare for pro-

gra~m the ACIA functional configuration when the com-

muni~Btions channel is required. During the first master

reset, the ~Q and RTS outputs are held at level 1. On all

other master resets, the ~output can be programmed

high or low with the ~output held high. Control bits CR5

and CR6 should also be programmed to define the state of

R= whenever master reset is utilized. After master resetting

the ACIA, the programmable Control Register can be set for

@MOTOROLA

Interrupt Request

Data Carrier Detect

Request-to-Send

Receive Data

anumber of options such as variable clock divider ratios,

variable word length, one or two stop bits, and parity (even,

odd, or none).

TRANSMIT

Atypical transmitting sequence consists of reading the

ACIA Status Register either as aresult of an interrupt or in

the ACIA’S turn in apolling sequence. Acharacter may be

written into the Transmit Data Register if the status read

operation has indicated that the Transmit Data Register is

empty. This character is transferred to aShift Register where

it is serialized and transmitted from the Transmit Data output

preceded by astart bit and followed by one or two stop bits.

Internal parity (odd or even) can be optionally added to the

character and will occur between the last data bit and the

first stop bit. After the first character is written in the Data

Transmit Data Register Empty condition and current

peripheral status. If the register is empty, another character

can be loaded for transmission even through the first

character is in the process of being transmitted (because of

Semiconductor Products Inc.

double buffering). The second character will be automatical-

ly transferred into the Shift Register when the first character

transmission is completed. This sequence continues until all

the characters have been transmitted.

RECEIVE

Data is received from aperipheral by means of the Receive

Data input. Adivide-by-one clock ratio is provided for an ex-

ternally synchronized clock (to its data) while the divide-

by-16 and Wratios are provided for internal synchronization.

Bit synchronization in the divide-by-16 and Wmodes is in-

itiated by the detection of 8or 32 low samples on the receive

line in the divide-by-16 and Wmodes respectively. False start

bh deletion capability insures that afull half bit of astart bit

has been received before the internal clock is synchronized

to the bit time. As acharacter is being received, parity (odd

or even) will be checked and the error indication will be

available in the Status Register along with framing error,

overrun error, and Receive Data Register full. In atypical

receiving sequence, the Status Register is read to determine

if acharacter has been received from aperipheral. If the

Receiver Data Register is full, the character is placed on the

8-bit ACIA bus when aRead Data command is received from

the MPU, When parity has been selected for a7-bit word (7

bits plus parity), the receiver strips the parity bit (D7= O) so

that data alone is transferred to the MPU. This feature

reduces MPU programming. The Status Register can con-

tinue to be read to determine when another character is

available in the Receive Data Register. The receiver is also

double buffered so that acharacter can be read from the

data register as another character is being received in the

shift register. The above sequence continues until .:%11

~l>i~$.s,

characters have been received. 4.,.\

.*, ,.!:3,}

‘~s*-.

ACIA INTERFACE SIGNALS FOR ~&,,@R%>

The ACIA interfaces to the M6~0 ~~U with an 8-bit

bidirectional data bus, three chip$@~Y*$fies, aregister select

line, an interrupt request linQw~~d#Write line, and enable

line. These signals permit tkf~~ ‘to have complete control

over the AC IA. .

“.t::\,i,\:\

,.:.

-$,:!*.,lP

,,!,,~,y-,..

ACIA Bidirectio~alfka&J?fi@ D7) –The bidirectional data

lines (DO-D7) all~?&$data transfer between the ACIA and

the MPU. Th%d+~~~ws output drivers are three-state devices

that remai~~~~~e ‘high-impedance (off) state except when

the MPU ~erfWms an ACIA read operation.

t,,.:.,.+:??~:.:k.:$

~QIA~~#able (E) –The Enable signal, E, is ahigh-

im~~~&ce TTL-compatible input that enables the bus in-

putF&utput data buffers and clocks data to and from the

ACIA. This signal will normally be a derivative of the MC6800

42 Clock or MC6809 Eclock.

Read/Write (R/~) –The Read/Write line is ahigh-

impedance input that is TTL compatible and is used to con-

trol the direction of data flow through the ACIA’S input/out-

put data bus interface. When Read/Write is high (MPU Read

cycle), ACIA output drivers are turned on and a selected

—

turned off and the MPU writes into aselected register.

Therefore, the Read/Write signal is used to select read-only

or write-only registers within the ACIA.

Chip Select (CSO, CS1, CS2) –These three high-

impedance TTL-compatible input lines are used to address

the ACIA. The ACIA is selected when CSO and CSI ar$:high

and ~is low. Transfers of data to and from the 4+@,@re

then performed under the control of the En@f~JY~nal,

Read/Write, and Register Select. :.~. ,*

.’~&i)\\“7$j{lp.$:j*,

~$,.,, .

~::*+\~i,,

impedance input that is TTL compatjbl,~~#’~~gh level is used

to select the Transmit/Receive D.~ta ;~$wkters and a low

level the Control/ Status Regis~~rs.b’)?~,@*Read/Write signal

line is used in conjunction wit~k,~gister Select to select the

read-only or write-only regi~%~~:i~~ach register pair.

.* ‘:...,.,

-~,,.~,:$l.

Interrupt Request (~~~,~:$ Interrupt Request is aTTL-

compatible, open-dr#$;J$*b”’internal pullup), @ve low out-

put that is used},$~ int~+rupt the MPU. The IRQ output re-

mains low as lo~~~m.tie cause of the interrupt is present and

the approp~~~~d$~’krrupt enable within the ACIA is set. The

~Q staty#$&l@t@hen high, indicates the ~output is in the

active s%.~.

l~$~rrup~ result from conditions in both the transmitter

f~~, ‘~eiver sections of the ACIA. The transmitter section

$$au~ an interrupt when the~ansmitter Interrupt Enabled

,,,,.~:$~~emdition is selected (CR5*CR6), and the Transmit Data

‘S~~%egister Empty (TDRE) status bit is high. The TDRE status

,,, ‘s” bit indicates the current status of the Transmitter Data

i.. Register except when inhibited by Clear-to-Send (~) be-

ing high or the ACIA being maintained in the Reset condi-

tion. The interrupt is cleared by writing data into the

Transmit Data Register. The interrupt is masked by disabling

the Transmitter Interrupt via CR5 or CR6 or by the loss of

~which inhibits the TDRE status bit. The Receiver sec-

tion causes an interrupt when the Receiver Interrupt Enable

is set and the Receive Data Register Full (R DRF) status bit is

high, an Overrun has occurred, or Data Carrier Detect (~)

has gone high. An interrupt resulting from the RDRF status

bit can be cleared by reading data or resetting the ACIA, in-

terrupts caused by Overrun or loss of ~are cleared by

reading the status register after the error condition has oc-

curred and then reading the Receive Data Register or reset-

ting the ACIA. The receiver interrupt is masked by resetting

the Receiver Interrupt Enable.

CLOCK INPUTS

Separate high-impedance TTL-compatible inputs are pro-

vided for clocking of transmitted and received data. Clock

frequencies of 1, 16, or Mtimes the data rate may be

selected.

Transmit Clock (Tx CLK) –The Transmit Clock input is

used for the clocking of transmitted data. The transmitter in-

itiates data on the negative transition of the clock.

Receive Clock (Rx CLK) –The Receive Clock input is

used for synchronization of received data. (In the +1mode,

the clock and data must be synchronized externally. )The

receiver samples the data on the positive transition of the

clock.

@MOTOROLA Semiconductor Products Inc.

been read. The RDRF bit remains set until the Overrun is character is in the RDR. If no parity is selected, then both the

reset. Character synchronization is maintained during the transmitter parity generator output and the receiver partiy

Overrun condition. The Overrun indication is reset after the check results are inhibited.

reading of data from the Receive Data Register or by a

Master Reset. Interrupt Request (~Q), Bit 7 – The ~bit indicates the

state of the ~output. Any interrupt condition with its ap-

Pafity Error (PE), Bit 6 – The parity error flag indicates plicable enable will be indicated in this status bit. An~time

that the number of highs (ones) in the character does not the IRQ output is low the mbit will be high to indi~L~~he

agree with the preselected odd or even parity. Odd parity is interrupt or service request status. ~is cleare@~~~$$~read

defined to be when the total number of ones is odd. The operation to the Receive Data Register or a~~if~b~~gration

parity error indication will be present as long as the data to the Transmit Data Register, ,.,,.lm.!

,.,::~i,.$,~.,

~.+,

:;%3,3K$<X‘

,..i..~’~,,,F~,>

<.?.,t::~ ‘

‘...$l.,:+,:w>..,>.~

,,.$:,*.?l:b*,P~

>.~,,,,.$, ~‘

“’+q:t,,,:,:;:

“~~:\ ,,

Package Type Frequency (MHz) Temperature Iw~umber

Ceramic 1.0 Ooc to 70”C

LSuffix 1.0

1.5

1.5 MC68A50CL

2.0

Cerdip MC68E50C

1.0 00c:.$q,,70ocd~ MC6850S

ssuffix 1.0 -~°C ~i,850C MC6850CS

1.5 #~F\Q 70°c

S{$h* to 85°C MC68A50S

1.5 MC68A50CS

2.0 WJWWQC to 700c MC68B50S

Plastic 1.0

’3’O“c to 700c MC6850P

Psuffix 1.0 .,ip ‘:’ –40°C to 85°C MC6850C P

1.5+$ -’~’:a> Ooc to 70”C MC68A50P

li@,>rk ‘“ –40°C to 85°C MCMA50CP

mMOTOROLA Semiconductor Products Inc.

—

CONTROL REGISTER

The ACIA Control Register consists ofeight bits of write-

only buffer that are selected when RS and Rl~are low. This

terrupt enables, and the Request-to-Send peri -

pheral/modem control output.

Counter Divide Select Bits (CRO and CR I)–The Counter

Divide Select Bits (CRO and CRI) determine the divide ratios

utilized in both the transmitter and receiver sections of the

ACIA. Additionally, these bits are used to provide amaster

reset for the ACIA which clears the Status Register (except

for external conditions on ~and DCD) and initializes both

the receiver and transmitter. Master reset does not affect

other Control Register bits. Note that after power-on or a

power fail/restart, these bits must be set high to reset the

ACIA. After resetting, the clock divide ratio maybe selected.

These counter select bits provide for the following clock

divide ratios:

CR1 CRO Function

o0_1

01+16

10 +M

11Master Reset

Word Select Bits (CR2, CR3, and CR4) –The Word

Select bits are used to select word length, parity, and the

number of stop bits. The encoding format is as follows:

CR4 CR3 CR2 Function

o007Bits+ Even Parity+2 Stop Bits $$

0 0 1 !?~~~$\.:i

7Bits+ Odd Parity+ 2Stop Bits$~&

o 1 0 7Bits+ Even Paritv +1Stop, ~~~;t,~$,

o 1 1 ..$,,,.,

7Bits+ Odd ParitV+ 1stQ#e~t<l~.

1 0 0 88its+2 Stop Bits ~.,’.-.. >.}

.\~.,~

~’”i, *.\\,,?~w

10 1 8 Bits+1Stop Bit ~R,~~$, ~

1 1 08Bits+ Even parit~~$$:$~@p Bit

111 8 Bits+ Odd Pa~~~~$~t,~top Bit

,~.i.,.,,!:.’~,

,:..!...,

Word length, Parity Select, a~~$$~o~ Bit changes are not

buffered and therefore becom~”eff~~ve immediately.

... ’33

,<V,,*:; w>),;?

Transmitter Control Bit#~.&l~$ and CR6) –Two Transmit-

ter Control bits prov[%~’’f.or the control of the interrupt from

the Transmit Data R~@#;~@Empty condition, the Request-to-

Send (~) outRNt&}& the transmission of aBreak level

(space). The f~t~~~~~ encoding format is used:

CR6 ~*~R’$Je“Function

~= low, Transmitting Interrupt Disabled.

~= low, Transmitting Interrupt Enabled,

~= high, Transmitting Interrupt Disabled.

RTS =low, Transmits aBreak level on the

Transmit Data Output. Transmitting inter-

rupt Disabled.

Receive Interrupt Enable Bit (CR7) –The following inter-

rupts will be enabled by ahigh level in bit position 7of the

Control Register (CR7): Receive Data Register Full, Overrun,

or alow-to-high transition on the Data Carrier Detect (~)

signal line.

@MOTOROLA

STATUS REGISTER

Information on the status of the ACIA is available to the

MPU by reading the ACIA Status Register. This read-only

mation stored in this register indicates the status of the

Transmit Data Register, the Receive Data Register and error

logic, and the peripheral/modem status inputs of ,$$$CIA.

.:;? ~>b.’‘“i

Receive Data Register Full (RDRF), Bit O.= ~~~<$}e Data

ferred to the Receive Data Register. RD~~,@*~{&9red after an

MPU read of the Receive Data Regisl,@,~r by% master reset.

The cleared or empty state indicat~$$~$~@’e contents of the

Receive Data Register are not c@i$fen$. ‘bata Carrier Detect

being high also causes RDRF ~inti~ate empty.

,’j’’.:i,>,>,,?*,

.<. .{,.>.,..,

Transmit Data Regi,~$$P@p& (TDRE), Bit 1 – The

Transmit Data Regis~h:@fi@ty bit being set high indicates

that the Transmit Q~@l~@gister contents have been trans-

,.,.....,,..,,

ferred and that,~ew ~ta may be entered, The low state in-

dicates that t~~$l~~ter is full and that transmission of anew

character ,~a~$~~i begun since the last write data command.

~*,’ .;::.?,>~~1$

;..” *\,$

Dat&~::#arrler Detect (~D), Bit 2 – The Data Carrier

D.@&ct && will be high when the ~input from amodem

:$.Q~S&Qne high to indicate that acarrier is not present. This bit

$Y g’~ng high causes an Interrupt Request to be generated

‘???~tien the~eive Interrupt Enable is set. It remains high

‘g~? after the DCD input is returned low until cleared by first

.. readina the Status Resister and then the Data Resister or

until amaster reset occurs. If the ~D input remains high

after read status and read data or master reset has occurre~,

the interrupt is cleared, the DCD status bit remains high and

will follow the ~input.

Clear-to-Send (=), Bit 3 – The Clear-to-Send bit in-

dicates the state of the Clear-to-Send input from amodem.

Alow =indicates that there is aClear-to-Send from the

modem. In the high state, the Transmit Data Register Empty

bit is inhibited and the Clear-to-Send status bit will be high.

Master reset does not affect the Clear-to-Send status bit.

Framing Error (FE), Bit 4 – Framing error indicates that

the received character is improperly framed by astart and a

stop bit and is detected by the absence of the first stop bit,

This error indicates asynchronization error, faulty transmis-

sion, or abreak condition. The framing error flag is set or

reset during the receive data transfer time. Therefore, this er-

ror indicator is present throughout the time that the

associated character is available.

Receiver Overrun (OVRN), Bit 5 – Overrun is an error flag

that indicates that one or more characters in the data stream

were lost. That is, acharacter or anumber of characters

were received but not read from the Receive Data Register

(RDR) prior to subsequent characters being received. The

overrun condition begins at the midpoint of the last bit of the

second character received in succession without aread of

the RDR having occurred. The Overrun does not occur in the

Status Register until the valid character prior to Overrun has

Semiconductor Products Inc.

SERIAL lNPUT/OUTPUT LINES

Receive Data (Rx Data) –The Receive Data line is ahigh-

impedance TTL-compatible input through which data is

received in aserial format, Synchronization with aclock for

detection of data is accomplished internally when clock rates

of 16 or Wtimes the bit rate are used.

Transmit Data {Tx Data) –The Transmit Data output line

transfers serial data to amodem or other peripheral.

PERIPHERAL/MODEM CONTROL

The ACIA includes several functions that permit limited

control of aperipheral or modem. The functions included are

Clear-to-Send, Request-to-Send and Data Carrier Detect.

Clear-to-Send (~) –This high-impedance TTL-

compatible input provides automatic control of the transmit-

ting end of acommunications link via the modem Clear-to-

Send active low output by inhibiting the Transmit Data

Request-to-Send (~S) –The Request-to-Send output

enables the MPU to control aperipheral or modem via the

data bus. The RTS output corresponds to the state of the

Control Register bits CR5 and CR6, When CR6= Oor both

CR5 and CR6= 1, the ~output is low (the active state).

This output can also be used for Data Terminal Ready (DTR).

Data Carrier Detect (~D) –This high-impedance TTL-

compatible input provides automatic control, such as in the

receiving end of acommunications link by means of a

modem Data Carrier Detect output. The ~input inhi~$,

and initializes the receiver section of the ACIA when hig&$,,~-*!~

low-to-high transition of the Data Carrier Detect ini~-;$p

interrupt to the MPU to indicate the occurrence ~$~!o% of

carrier when the Receive Interrupt ~ble bi~$$~~f+’ The

Rx CLK must be running for proper DCD ~iw$~.

,.’.~.~.

$!,....{J.

l.,:?..,%>,:,

..,>.+:$

~,.i”..:,:<~

.,.‘>..*...’.

ACIA REGISTERS

The expanded block diagram for the ACIA indicates the in-

ternal registers on the chip that are used for the status, con-

trol, receiving, and transmitting of data. The content of each

of the registers is summarized in Table 1.

.! ,.

TRANSMIT DATA REGISTER (TDR) A),,),,

l.~:~.:.*L~\,\.,,,.~t:l$:>

Data is written in the Transmit Data Register.l#~~~& the

‘J..\+,,,

negative transition of the enable (E) when the A~~~~$@%been

addressed with RS high and Rl~ low. Wti@fi$:,Q~ta into the

Status Register to go low. Data can th&~$,@transmitted. If

the transmitter is idling and no ch~’c$~~~ being transmit-

ted, then the transfer will take p!~ce’~~~fiin l-bit time of the

trailing edge of the Write com~~d. If acharacter is being

t,,..~\a!i*.

transmitted, the new data <~;~{wter will commence as soon

as the previous characte~~%.tqtiplete. The transfer of data

causes the Transmit Da~~,R#ster Empty (TDRE) bit to in-

dicate empty. :+;~~\y\..T\~h

.,$t..=

,:},,.\ .,

,<!~j,

RECEIVE DAT~~&~WSTER (RDR)

~t+<t:t??>:.,’.::,

Data is a~to~t[cally transferred to the empty Receive

Data Regf$~$*t#DR) from the receiver deserializer (a shift

regist~r)“~~~n receiving acomplete character. This event

caq*, the ‘Receive Data Register Full bit (RDRF) in the

$$at~s%uffer to go high (full). Data may then be read

~$,~~o,@h the bus by addressing the ACIA~nd selecting the

~,:~~Q~Uelve Data Register with RS and R/W high when the

‘v*~t&’&CIAis enabled. The non-destructive read cycle causes the

,+,r. RDRFbit to be cleared to empty although the data is re-

tained in the RDR. The status is maintained by RDRF as to

whether or not the data is current. When the Receive Data

Receiver Shift Register to the Data Register is inhibited and

the RDR contents remain valid with its current status stored

in the Status Register.

..,.

,,\w;~~~$lE 1 – DEFINITIONOF ACIA REGISTERCONTENTS

.,.r \:.,..

.:,~. ,.,

..,:~,~.,.;4.’

,<::’‘~’Jt..~~ Buffer Address

Data ,“~>q.$:$ GRs ●R/m Ts. mWs●R/fi

Bus ,~’~ “f

~.,.! .,.? Transmit Receive

Line ~>~ :$: );>

.l}:,:. Data Data Control Status

NU*t;~ Register Register

“,.., Register Register

,+ J’\@*

,3{ .*(Write Only) (Read Only) (Write OnIV)

\>~~\ (Read OnIv)

:$\{,$@&;;’” Data Bit 0. Oata Bit O

*,\$l$\\*,~..,, Counter D!vide Recei”e Data Register

.~.t’ ~8,, Select 1(CRO) F“II{RDRF)

*i. “,

.:.,:\:i‘%::,,C3${, Data Bd 1Data Bitl Counter Di”ide Transm, tData Reg!ster

.“ ~

.,,:{

.<,:*:...\>\:),), Select2 (c RI) Empty (T DRE)

‘~”i.

~ii:’;”:sr.:.++;,,,,,v2Data Bit 2Data Bit 2Word Select 1Data Carrier Detect

k;j~) .. (CR2)

\A\> (DCD)

3Data Bit 3Data B!t 3Word Select 2Clear-to-Send

(CR3) (CTS)

4Data Bit 4Data Blt 4Word Select 3Fram, ng Error

(CR4; (FE)

5Data Bit 5Data B,t 5Transm)t Control 1Receiver Overrun

(CR5) (OVRN)

6Data Bit 6Data Bit 6Transm!t Control 2Par, tV Error [PE)

(CR6)

7Data Bit 7.*’ Data Bit 7.* Rece, ve l“terr”~t Interrupt Request

Enable (CR7) (~Q)

‘Leading bit =LSB =Bit O

“‘Oata bit will be zero in 7-bit plus parity modes.

‘“ ‘Data bit is “don’t care” in 7-bit plus paritv modes.

@MOTOROLA Semiconductor Products Inc.

PACKAGE DIMENSIONS

nnnnnnmnnnnn

24 13

CASE 6~-~

(CERDIPI

MILLIMETE2S[ INCHES

DIM MIN [MAX MIN MAx NOTES:

1. DIM “~’ TO CENTER OF

w“

A31.24 32.77 1.230 1,290 LEAOSWHEN FORMEO

B12.70 15.49 0.500 0,610 PARALLEL,

c4.06 5.59 0.160 0.220 2. LEAOSWITHIN 0.13 mm

o0.41 0.51 0.016 0.020 (0.005] RAOIUS OF TRUE

F1.27 1.52 0.050 0.060 POSITION AT SEATING

o2.54 6SC 0.100 6SC PLANE AT MAXIMUM

J0.20 0.30 0.008 0.012 MATERIAL CONOITION.

K2.29 4.06 0.090 0.160 (WHEN FORMED PARALLEL)

L15.24 BSC 0.600 6SC

M00 ,~o 00 ,50

N0.51 1.27 0.020 0.050

BI13,72 I14.22 I0,540]Q

c3.94 I

oI0.36 \

oIM/ MIN IMAX I‘“ “S1.PdSITIONALT OLEflANc EOFLEAOs( 0),

MlNMA, ,, “...:~:,j$>:~,

13137 132.13 I1.23511 .2.@, sSHALL 6EWlTHl N025mm(0.OIO)AT

,:.:.

MAXIMUM MATERIAL CONDITION, IN

y,: .<*

)!. ‘RELATION TO SEATING PLANE AND

r,,“. ,,..’ “.”+” .*” dEACH OTHER.

c?q~ RTC :!.4 100 c 2DIMENSION LTOCENTEROFLEAOS

.6 0.080 WHEN FORMEO PARALLEL.

“’’.0.00 0.015 3, DIMENSION BOO ES NOT INCLUOEMOLO

‘&l15 0.135 FLASH,

... H-!—, .,”. ,.. ,.. ”= -

NOTE:

1. LEAOSTRUE POSITIONED WITHIN

0.25mm(0.010) OIA (AT SEATING

PLANE) AT MAXIMUM MATERIAL

CONOITION,

2. OIM’’L’’TO CENTER OF LEAOS

WHEN FORMEO PARALLEL.

Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume any Iiabilityarising

out of the application oruseof anvproduct or circuit described herein; ne!ther does ifconvevanyl;cense under itspatent rights northerights of others.

@MOTOROLA Semiconductor Products Inc.

3501 ED BLUESTEIN BLVD., AUSTIN, TEXAS 78721 ●ASUBSIDIARY OF MOTOROLA INC

.,!225-7 P.1~~ IX “S. 4-85 lm~,.. .1,”0 ,30469 18,000 ,$9,93.4