SSI2N60B - Fairchild Semiconductor

April 2001

Rev. A, April 2001

SSW2N60B / SSI2N60B

600V N-Ch annel MOSFET

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for high efficiency switch mode power supplies.

Features

• 2.0A, 600V, RDS(on) = 5.0Ω @VGS = 10 V

• Low gate charge ( typical 12.5 nC)

• Low Crss ( typical 7.6 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

Absolute Maximum Ratin gs TC = 25°C unless otherwise noted

Thermal Characteri stics

Symbol Parameter SSW2N60B / SSI2N60B Units

VDSS Drain-Source Voltage 600 V

IDDrain Current - Continuous (TC = 25°C) 2.0 A

- Continuous (TC = 100°C) 1.3 A

IDM Drain Current - Pulsed (Note 1) 6.0 A

VGSS Gate-Source Voltage ± 30 V

EAS Single Pulsed Avalanche Energy (Note 2) 120 mJ

IAR Avalanche Current (Note 1) 2.0 A

EAR Repetitive Avalanche Energy (Note 1) 5.4 mJ

dv/dt Peak Diode Recovery dv/dt (Note 3) 3.0 V/ns

PDPower Dissipation (TA = 25°C) * 3.13 W

Power Dissipation (TC = 25°C) 54 W

- Derate above 25°C 0.43 W/°C

TJ, Tstg Operating and Storage Temperature Range -55 to +150 °C

TLMaximum lead temperature for soldering purposes,

1/8" from case for 5 seconds 300 °C

Symbol Parameter Typ Max Units

RθJC Thermal Resistance, Junction-to-Case -- 2.32 °C/W

RθJA Thermal Resistance, Junction-to-Ambient * -- 40 °C/W

RθJA Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W

* When mounted on the minimum pad size recommended (PCB Mount)

D2-PAK

SSW Series I2-PAK

SSI Serie s

Rev. A, April 2001

SSW2N60B / SSI2N60B

(Note 4)

(Note 4, 5)

(Note 4)

Electrical Characteristics TC = 25°C unless otherwise noted

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 55mH, IAS = 2.0A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ 2.0A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C

4. Pulse Test : Pulse width ≤300µs, Duty cycle ≤2%

5. Essentially independent of operating temperature

Symbol Parame ter Test Condition s Min Typ Max Units

Off Characteristics

BVDSS Drain-S ource Breakdown Vo ltage VGS = 0 V, ID = 250 µA600 -- -- V

∆BVDSS

/ ∆TJ

Breakdown Voltage Temperature

Coefficient ID = 250 µA, Referenced to 25°C -- 0.65 -- V/°C

IDSS Zero Gate Voltage Drain Current VDS = 600 V, VGS = 0 V -- -- 10 µA

VDS = 480 V, TC = 125°C -- -- 100 µA

IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA

IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA

On Characteri st ics

VGS(th) G ate Threshold Voltage VDS = VGS, ID = 250 µA2.0 -- 4.0 V

RDS(on) Static Drain-Source

On-Resistance VGS = 10 V, ID = 1.0 A -- 3.8 5.0 Ω

gFS Forward Transconductance VDS = 40 V, ID = 1.0 A -- 2.05 -- S

Dynamic Characteristics

Ciss Input Capacitance VDS = 25 V, VGS = 0 V,

f = 1.0 MHz

-- 380 490 pF

Coss Output Capacitance -- 35 46 pF

Crss Reverse Transfer Capacitance -- 7.6 9. 9 pF

Switching Characteristics

td(on) Turn-On Delay Time VDD = 300 V, ID = 2.0 A,

RG = 25 Ω

-- 16 40 ns

trTurn-On Rise Time -- 50 110 ns

td(off) Turn-Off De l a y Time -- 40 90 ns

tfTurn -Off Fa ll Time -- 4 0 90 ns

QgTotal Gate Charge VDS = 480 V, ID = 2.0 A,

VGS = 10 V

-- 12.5 17 nC

Qgs Gate-Source Charge -- 2.2 -- nC

Qgd Gate-Drain Charge -- 5.4 -- nC

Drain-Source Diode Characteristics and Maximum Ratings

ISMaximum Continuous Drain-Source Diode Forward Current -- -- 2.0 A

ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 6.0 A

VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.0 A -- -- 1.4 V

trr Reverse Recovery Time VGS = 0 V, IS = 2.0 A,

dIF / dt = 100 A/µs

-- 250 -- ns

Qrr Reverse Recovery Charge -- 1.31 -- µC

SSW2N60B / SSI2N60B

0.2 0.4 0.6 0.8 1.0 1.2 1.4

10-1

100

150$

% Note s :

1. VGS = 0V

2. 250&s P ulse Test

25$

IDR, Reverse Drain Current [A]

VSD, Source-Drain voltage [V]

246810

10-1

100150oC

25oC

-55oC% N otes :

1. VDS = 40V

2. 250&s P ulse Test

ID, Drain Current [A]

VGS, Gate-Source Voltage [V]

02468101214

VDS = 300V

VDS = 120V

VDS = 480V

% Note : ID = 2.0 A

VGS, Gate-Source Voltage [V]

QG, T o ta l G a te Cha rg e [n C ]

10-1 100101

200

400

600

800

Coss

Ciss = Cgs + Cgd (Cds = shorted)

Coss = Cds + Cgd

Crss = Cgd

N o te s :

1 . V GS = 0 V

2 . f = 1 MHz

Crss

Ciss

Capacitance [pF]

VDS, D rain-Source Voltage [V]

0123456

VGS = 20V

VGS = 10V

N o te : TJ = 25$

RDS(ON) [ '],

Drain-Source On-Resistance

ID, Drain Current [A]

10-1 100101

10-2

10-1

100

V GS

Top : 1 5 .0 V

1 0 .0 V

8 .0 V

7 .0 V

6 .5 V

6 .0 V

5 .5 V

Bottom : 5.0 V

% N otes :

1. 250 &s Pulse Test

2. TC = 25$

ID, Drain Current [A]

VDS, Drain-Source Voltage [V]

Typical Characteristics

Figure 5. Capacitanc e Ch aracterist ics Figure 6. Gate Charge C haracteris tics

Figure 3. On-Resistanc e Variation vs

Drain Current and Gate Voltage Figure 4. Body Diode Fo rwa rd Voltage

Va riation with Source Cur r ent

and Temperature

Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Character i st ics

SSW2N60B / SSI2N60B

-100 -50 0 50 100 150 200

0.0

0.5

1.0

1.5

2.0

2.5

3.0

N o te s :

1 . V GS = 10 V

2 . ID = 1.0 A

RDS(ON) , (Normalized)

Drain-Source On-Resistance

TJ, Junction Tem perature [oC]

-100 -50 0 50 100 150 200

0.8

0.9

1.0

1.1

1.2

N o te s :

1 . V GS = 0 V

2 . ID = 250 &A

BV DSS , (No r ma liz e d )

Drain-Source Breakdown Voltage

TJ, Junction Tem perature [oC]

10-5 10-4 10-3 10-2 10-1 100101

10-2

10-1

100% Notes :

1 . Z(JC(t) = 2 .32 $/W Ma x .

2 . Du ty Fa c to r, D = t1/t2

3 . TJM - TC = PDM * Z (JC(t)

s in g le p u ls e

D=0.5

0.02

0.2

0.05

0.1

0.01

Z(JC

(t), T he rma l Res p o ns e

t1, Square Wave Pulse D uration [sec]

25 50 75 100 125 150

0.0

0.4

0.8

1.2

1.6

2.0

ID, D ra in C u rre n t [A]

TC, Case Temperature [$

]

100101102103

10-2

10-1

100

101

10 ms

1 ms 100 µs

Operation in Th is Area

is Limited by R DS(on)

% N otes :

1. TC = 25 oC

2. TJ = 15 0 oC

3. Single Pulse

ID, Drain Current [A]

VDS, Drain-Source Voltage [V]

Typical Characteristics (Continued)

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs Case Temperature

Figu re 7. Breakdown Voltage Variation

vs Temperature Figure 8. On-Resistance Variation

vs Temperature

Figure 11. Transi ent Ther m al Res pons e Cur ve

PDM

SSW2N60B / SSI2N60B

Charge

VGS

10V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K)

200nF

12V

Same Type

as DUT

Charge

VGS

10V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K)

200nF

12V

Same Type

as DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS RL

DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS RL

DUT

VGS

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

EAS =LI

AS2

----

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

Gate Charge Test Circuit & Waveform

Resistive Switching Test Circuit & Waveforms

Unclamped Inductive Switching Test Circuit & Waveforms

SSW2N60B / SSI2N60B

Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

VDS

Driver

RGSame Type

as DUT

VGS • dv/dt controlled by RG

•I

SD con trol l e d by pulse peri od

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

DUT

VDS

Driver

RGSame Type

as DUT

VGS • dv/dt controlled by RG

•I

SD con trol l e d by pulse peri od

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

SSW2N60B / SSI2N60B

Package Dimensions

10.00 ±0.20

(8.00)

(4.40)

1.27 ±0.10 0.80 ±0.10

0.80 ±0.10

(2XR0.45)

9.90 ±0.20 4.50 ±0.20

0.10 ±0.15

2.40 ±0.20

2.54 ±0.30

15.30 ±0.30

9.20 ±0.20

4.90 ±0.20

1.40 ±0.20

2.00 ±0.10

(0.75)

(1.75)

(7.20)

0°~3°

1.20 ±0.20

9.20 ±0.20

15.30 ±0.30

4.90 ±0.20

(0.40)

2.54 TYP 2.54 TYP

1.30 +0.10

–0.05

0.50 +0.10

–0.05

D2PAK

SSW2N60B / SSI2N60B

Package Dimensions (Continued

9.90 ±0.20

2.40 ±0.20

4.50 ±0.20

1.27 ±0.10 1.47 ±0.10

(45°)

0.80 ±0.10

10.00 ±0.20

2.54 TYP2.54 TYP

13.08 ±0.20

9.20 ±0.20

1.20 ±0.20

10.08 ±0.20 MAX13.40

MAX 3.00

(0.40)

(1.46)

(0.94)

1.30 +0.10

–0.05

0.50 +0.10

–0.05

I2PAK

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not intended to be an exhaustive list of all such trademarks.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.

As used herein:

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systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT ST A TUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Formative or

In Design

First Production

Full Production

Not In Production

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