EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 1 of 10
Enpirion EN5364QI 6A and EN5394QI 9A
DCDC Converter w/Integrated Inductor
Evaluation Board
Introduction
Thank you for choosing Enpirion, the source for Ultra small foot print power
converter products. This user guide should be used together with the latest
device datasheet.
• The EN5364QI and EN5394QI (collectively referred to as EN53x4QI in the
remainder of this document) features integrated inductor, power
MOSFETS, Controller, bulk of the compensation Network, and protection
circuitry against system faults. This level of integration delivers a
substantial reduction in footprint and part count over competing solutions.
However, the evaluation board is not optimized for minimum footprint;
rather for engineering ease of evaluation through programming options,
clip leads, test points etc.
• The EN53x4QI device is feature rich and supports the following additional
functions:
o Margining – The output voltage can be changed by ±2.5%, ±5% or
±10% about the nominal, under digital control using ternary pins
MAR[1:2] Margining is highly valued for system robustness
verification and reliability studies. Note: POK automatically scales
with margining.
o Phase Lock - The internal switching frequency can be phase
locked to an external clock source (or another EN53x4QI) by
connecting such a clock source to pin S_IN. This feature is highly
valued to keep beat frequencies (between a system sampling clock
and the DC/DC converter switching frequency) out of the desired
signal band.
o Delay - A delayed version of the internal switching clock (or the
PWM signal) is available at pin S_OUT. This may be input to
another EN53x4QI device.
o The delay is programmable by means of a single resistor
connected between pin S_delay and AGND. This feature allows the
control of input ripple when multiple EN53x4QI devices are used on
a system board.
o Pre-bias operation – When the device pre-bias is enabled (jumper
provided), the device will monotonically ramp-up its output voltage
from a pre-bias voltage level to the programmed output voltage
level under control of Enable signal. The pre-bias (Back-feed)
EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 2 of 10
voltage may be coupled to the output via a diode. This diode (D2) is
populated on the board. Back-feed voltage may be applied at
BF_IN (TP18)
o Parallel Mode operation – Up to 4 EN53x4QI devices may be
operated in parallel when load currents greater than 6A/9A is
desired. In parallel mode, one device is designated the Master and
up to 3 devices operate in slave mode, controlled by the Master.
The PWM output of the Master is routed to slave devices. By daisy
chaining the Slave devices even more devices can be operated in
parallel but practical considerations, such as board layout would
limit the number of slave devices to three.
o Soft-Start – A 15nF (C11) soft-start capacitor is populated on the
evaluation board for an output voltage ramp time of ~1ms. This may
be swapped for a different value capacitor if a different ramp time is
desired. To limit the inrush current this capacitor value should be
greater than 4.7nF. The output voltage rise time is ~65k*CSS.
• The EN53x4QI features a customer programmable output voltage by
means of a resistor divider. The resistor divider allows the user to set the
VOUT to any value within the range 0.6V to approximately (VIN-0.5V).
`Referring to Figure 1, the evaluation board, as shipped is populated with
a single RA, a single CA, and four possible RB resistors. A jumper selects
one of the 4 RB resistors to produce a voltage of 0.804, 0.998, 1.2 or
1.8Volts. You can populate more than one RB jumper position to get even
higher output voltages. See “VOUT Programming” section in the
evaluation board schematic (Figure 7).
• The EN53x4QI includes the bulk of the compensation network internally.
However, an external phase-lead (zero) capacitor is required as part of the
feedback. This network is shown in Figure -1. Appropriate component
values allow for optimum compensation for a given Input voltage and
choice of loop bandwidth. The equations in Figure 1 provide the details to
calculate component values.
• MAR1 and MAR2 are ternary input signals. The pins are allowed to be in a
low state (tied to GND), a high state (tied to VIN), or a float state. Table-1
shows the margining truth table. Accordingly, the output voltage can be
nominal or ±2.5%, ±5% or ±10% about the nominal. 7 out of 9 possible
states of MAR[1:2] are used for margining. The other two states are
reserved for diagnostics. If tying MAR[1,2] to VIN, a series resistor is
recommended to reduce the pin input current (see Figure 2).
• A footprint is provided for a SMC connector (not populated) for S_IN. A
clock source (3.6 to 4.4MHz) may be applied to S_IN to synchronize the
device switching frequency to the external source. S_OUT will output a
clock signal synchronous with the switching frequency, with a phase
delay. S_OUT of one EN53x4QI may be connected to S_IN of another
EN53x4QI device in different modes of operation.
EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 3 of 10
• The phase delay is set by connecting a resistor from S_delay to AGND.
The delay is approximately:
Delay (nsec) = 2*[S_delay resistance in kΩ.]
A 49.9kΩ (populated on Evaluation board) resistor value delays the clock
signal by ~100nsec.
• EN53x4QI supports pre-bias mode operation. To use this option set the
EN_PB jumper to pre-bias enable position with device powered down.
When the device is subsequently powered and enabled, the output
voltage will ramp monotonically from its pre-bias value to the programmed
value. Pre-bias voltage may be applied to clip lead BF_IN on the
evaluation board. A diode D2 is populated on the board between BF_IN
and VOUT.
• Jumpers are provided for ease of logical high/low programming of the
following signals:
o Enable
o Pre-bias Enable
o MAR1 and MAR2 Margining ternary inputs
o Master/Slave ternary input
Enable may also be controlled using an external switching source by
removing the jumper and applying the enable signal to the middle pin and
ground.
o Jumpers are also provided for selecting one of 4 possible output
voltages.
• The board comes with input decoupling and reverse polarity protection to
guard the device against common setup mishaps.
V
OUT
R
A
C
A
R
B
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,(
1072.4
)(000,30
6
FBOUT
FB
B
A
A
A
A
A
VV RAV
R
inR
FaradsinC
R
C
invalueVinR
−
×
=
Ω
×
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×
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V
FB
EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 4 of 10
Figure - 1 : Output voltage programming and loop compensation. RA and CA
correspond R17 & C20 on the board. RB corresponds to a combination of
R13, R14, R16, or R18 on the board, depending on which jumpers are
populated on J13.
Rext
R1
100k
R2
100k
R3
3k
D1
2.5V
VIN
AGND
To Gates
IC Package
Vf ~ 2V
250
Quick Start Guide
Figure – 3 : J1 Mode Selection Jumpers
In Figure 3, the jumper on ENA pin as shown is in disable mode. For all the J1
positions, when the jumper is between the middle and right pins the signal pin is
connected to ground or logic low. When the jumper is between the left and
middle pins, the signal pin is connected to VIN or logic High. When there is no
jumper, MAR1, MAR2 and M_S pins will be in Float mode, however ENA and
EN_PB are internally pulled low.
WARNING: complete steps 1 through 4 before applying power to the EN53x4QI
evaluation board.
STEP 1: Set the “ENA” and “ENA_PB” jumper to the Disable Position. Select
MAR1, MAR2, and M/S to float (no jumper).
STEP 2: Set the output voltage select jumper for the desired setting as shown
below:
VIN
SIDE
GND
SIDE
Figure 2: Equivalent circuit of a ternary pin
(MAR1, MAR2, or M/S) input buffer. To get a
logic High on a ternary input, pull the pin to VIN
through an external resistor REXT. The board is
populated with a 10kΩ REXT for all three ternary
pins.
EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 5 of 10
Figure – 4 : J13 Voltage Selection Jumpers
In Figure 4, output Voltages, from left to right, are 0.804V, 0.998V, 1.2V
and 1.0V.Jumper as shown, selects 1.2V output. Higher output voltages
can be achieved by populating multiple J13 jumper positions. See Figures
1 and 7.
CAUTION: Except for ENA, NONE of the J1 & J13 jumpers can be
changed while the EN53x4QI is enabled. Doing so could damage the part.
STEP 3: Connect Power Supply to the input power connectors, VIN (+) and
GND (−) as indicated in Figure - 5 and set the power supply to the desired
voltage. The compensation components for the board have been optimized for
an input voltage of 5V (see Figures 1 & 7). To optimize the board for another
input voltage, calculate new values RA, CA, and RB using the equations in Figure
1. The caption in Figure 1, states which components on the PCB correspond to
RA, CA, & RB.
CAUTION: be mindful of the polarity. Even though the evaluation board
comes with reverse polarity protection diodes, it is rarely a good idea to
reverse the input polarity.
STEP 4: Connect the load to the output connectors VOUT (+) and GND (−), as
indicated in Figure -5.
STEP 5: Power up the board and move the ENA jumper to the enabled position.
The EN53x4QI is now powered up and generating the desired output. You are
free to make Efficiency, Ripple, Line/Load Regulation, Load transient, Power OK,
over current limit and temperature related measurements. You may also view the
delayed switching clock at S_OUT. However, you do not have a reference to
measure the delay against!
STEP 5A: Power Up/Down Behavior – Remove ENA jumper and connect a
pulse generator (output disabled) signal to the middle pin of ENA and Ground.
Set the pulse amplitude to swing from 0 to 2.5 volts. Set the pulse period to
10msec., duty cycle to 50% and fast transition (<1usec.) Hook up oscilloscope
probes to ENA, SS, POK and VOUT with clean ground returns. Enable pulse
generator output. Observe the SS capacitor and VOUT voltage ramps as ENA
goes high and again as ENA goes low.
STEP 6: Margining – Disable device by moving the ENA jumper. Set MAR-1
and MAR-2 jumpers to the desired amount (percentage) voltage shift according
to Table 1. Re-Enable device and continue as in Step 5.
VIN
SIDE
EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 6 of 10
MAR-1 MAR-2 Output Modulation
Float Float 0%
Low Low -2.5%
High Low +2.5%
Low High -5%
High High +5%
Low Float -10%
High Float +10%
Float High 0%, Delay Bypass
Float Low Reserved
Table-1 : Margin Block Truth Table
STEP 7: Phase Lock – Disable device by moving ENA jumper. Power down the
device. Connect a pulse generator (properly terminated and output disabled)
signal between S_IN and GND. Set the pulse amplitude to swing from 0 to 2.5
volts. Set the pulse frequency to 4MHz. Connect oscilloscope probes to S_IN &
S_OUT. Power up device. Enable device. Note S_OUT – it is the free running
switching frequency. Now enable the pulse generator output. S_OUT should be
locked to S_IN with a fixed delay (depending on the value of the S_Delay
resistor.) Sweep the clock frequency between 3.6 and 4.4 MHz and note the lock
range at both extremes.
You may next wish to observe the delay as a function of S_Delay resistor.
ALWAYS power down device before changing board level components!
STEP 8: Pre-Bias Operation – Disable device by removing Enable jumper.
Power down device. Set EN_PB jumper to logical “1.” Connect a pulse generator
(output disabled) signal to the middle pin of ENA and Ground. Set the pulse
amplitude to swing from 0 to 2.5 volts. Set the pulse period to 10msec., duty
cycle to 50% and fast transition (<1usec.) Hook up oscilloscope probes to ENA,
SS, POK and VOUT with clean ground returns. Connect a power supply (set
desired voltage but output disabled) to TP18 (BF_IN.) D2 is a diode connecting
BF_IN to VOUT. Turn the back feed supply on. VOUT will charge to BF_IN minus
a diode drop. Set the output voltage to a level greater than the back feed voltage.
Enable pulse generator output. Observe the output voltage and SS voltage in
relation to the Enable pulse. Sweep the back feed voltage up and down but
always less than VOUT and note device operation.
EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 7 of 10
Figure – 5 : Evaluation Board Layout.
EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 8 of 10
Test Recommendations
To guarantee measurement accuracy, the following precautions should be
observed:
1. Make all input and output voltage measurements at the board using
the test points provided. This will eliminate voltage drop across the line
and load cables that can produce false readings.
2. Measure input and output current with series ammeters or accurate
shunt resistors. This is especially important when measuring efficiency.
3. Use a low-loop-inductance probe shown here to measure switching
signals to avoid noise coupling into the probe ground lead. J10 is a
convenient point to measure output ripple and load transient deviation.
Please refer to Enpirion’s Output Ripple Measurement application note
for more accurate ripple measurements.
Figure – 6 : Low-loop-inductance Oscilloscope Probe
4. The board includes a 10k pull-up for the POK signal and ready to
monitor the power OK status.
5. A 15nF soft-start capacitor is populated on the board for ~1msec soft-
start time.
6. Please consult Enpirion Applications Support if you are planning to
perform any special EMI or noise measurements on this evaluation
board.
Input and Output Capacitors
The input capacitance requirement is between 20-40uF for the EN5364QI and
30-40uF for the EN5394QI. The voltage rating should be high enough to provide
adequate margin for your application. This evaluation board is populated with
2x22uF, 1206, X5R capacitors.
The output capacitance requirement is approximately 50uF at the voltage
sensing point for the EN5364QI and approximately 100uF for the EN5394QI. The
board is populated with a 47uF, 1206, X5R and a 10uF, 0805, X7R capacitor for
the EN5364QI and 2 x 47uF, 1206, X5R capacitor for the EN5394QI evaluation
board.
NOTE: Capacitors must be X5R or X7R dielectric formulations to ensure
adequate capacitance over operating voltage and temperature ranges.
EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 9 of 10
R1
AGND
R2
R20
R21
C10
C11
TP12
0402
TP13
R4
TP5
TP3
TP2
J101
2
J12
1
2
GND OUT
GND IN
TP17
R6
TP4
TP23
J2
1
2
J3
1
2
TP6TP7
TP20
TP21
S_DEL
D2
TP18
AVIN
AGND
0805
0805
C6
C7
TP8
TP9
TP10
TP11
J4
J6
J5
J7
AGND
TP14
TP15
TP16
U1
EN5364Q I / EN 5394Q I
PGND
1
PGND
2
PGND
3
PGND
4
VOUT
5
VOUT
6
VOUT
7
VOUT
8
VOUT
9
VOUT
10
VOUT
11
VOUT
12
VOUT
13
NC14
14
NC15
15
NC16
16
NC17
17
NC18
18
NC19
19
NC20
20
NC21
21
NC22
22
NC23
23
NC24
24
NC(SW)
25
NC(SW)
26
PGND
27
PGND
28
PGND
29
PGND
30
PGND
31
PGND
32
PGND
33
PVIN
34
S_IN 49
S_OUT 48
NC47 47
NC46 46
NC45 45
NC44 44
PVIN 43
PVIN 42
PVIN 41
PVIN 40
PVIN 39
PVIN 38
PVIN 37
PVIN 36
PVIN 35
PGND 68
PGND 67
PGND 66
PGND 65
PGND 64
VSENSE 63
MAR2 62
MAR1 61
S_DELAY 60
SS 59
OCP_ADJ 58
EAOUT 57
VFB 56
AGND 55
POK 54
AVIN 53
ENABLE 52
EN_PB 51
M/S 50
TP22
GND
OUT
MAR2
MAR1
ENA
EN_PB
M/S
TP19
VOUT
S_OUT
POK
EN_PB
M/S
R11
ENA
R12
MAR1
R19
SS
MAR2
BF_IN
08050805
0805
VOUT
VIN
PVIN
VOUT
AGND
0805
0402
0402
0402
0402
0402
0402
R7
VFB
R3
EAOUT
C5C4
VSENSE
1206/0805
SW PGND
C2
C3
AGND
1206
1210
1210
C12
AGND
J8
1
2
TP1
AVIN
J9
C8
Figure – 7 : Evaluation Board Schem atic
AVIN
J1
1
2
3
5
6
7
9
10
11
13
14
15
17
18
19
FB1
C13
AGND
M/S
EN_PB
ENA
MAR2
MAR1
MAR1
MAR2
EN_PB
ENA
M/S
AGND
U2 D1
S2A
+
C1
AGND
PVIN
Eval Board In put Pr ote cti on
EAOUT
VFB R8 C14
C15
Additional Compensation Components
R10
S_DEL
R5
Top turn pot
AGND
0805
Sync Delay Programming
R17
C20
R13
R18
AGND
VSENSE
R14
R16
VFB
J13
1
3
5
2
4
6
87
0805
0805
0805
0805
0805
0805
VOUT Progra mming
EN5364QI-EN5394QI Evaluation Board Application Note
November 2009 V_3
Page 10 of 10
Contact Information
Enpirion, Inc.
Perryville III
53 Frontage Road, Suite 210
Hampton, NJ 08827
Phone: +1-908-894-6000
Fax: +1-908-894-6090
www.enpirion.com
Enpirion reserves the right to make changes in circuit design and/or
specifications at any time without notice. Information furnished by Enpirion is
believed to be accurate and reliable. Enpirion assumes no responsibility for its
use or for infringement of patents or other third party rights, which may result
from its use. Enpirion products are not authorized for use in nuclear control
systems, as critical components in life support systems or equipment used in
hazardous environment without the express written authority from Enpirion.
