MPC555LFAZP40 - NXP SEMICONDUCTORS

This document provides an overview of the MPC555 microcontroller, including a block

diagram s howing th e major mod ular compone nts and sec tions that li st the majo r feat ures. The

MPC555 member of the Freescale MPC500 RISC Microcontroller family.

1 Introduction

The MPC555 device offers the following features:

• PowerPC™ core with floating-point unit

• 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM

• 448 Kbytes Flash EEPROM with 5-V programming

• 5-V I/O system

• Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B

controller

modules (TouCANTM)

• 50-channel timer system: dual time processor units (TPU3), modular I/O system

(MIOS1)

• 32 analog inputs: dual queued analog-to-digital converters (QADC64)

• Submicron HCMOS (CDR1) technology

• 272-pin plastic ball grid array (PBGA) packaging

• 40-MHz operation, -40 °C to 125 °C wi th dua l supply (3.3 V, 5 V) ( -5 5 °C to 125 °C

for the suffix A device)

• 32-bit archit ecture (PowerP C ISA a rchit ectur e compliant)

• Core performance measured at 52.7-Kbyte Dhrystones (v2.1) @ 40 MHz

• Fully static, low power operation

• Integrated double-precision floating-point unit

• Precise exception model

Table 1. MPC555 Features

Device Flash Code Compress ion

MPC555 448 Kbytes Code compression not supported

Product Brief

MPC555PB/D

Rev. 3, 2/2003

MPC555 Product Brief

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2MPC555 Product Brief

Block Diagram

• Extensive system development support

— On-chip watchpoints and breakpoints

— Program flow tracking

— BDM on-chip emulation development interface

1.1 Block Diagram

Figure 1 is a block diagram of the MPC555.

Figure 1. MPC555 Block Diagram

1.2 Key Features

The MPC555 key features are explained in the following sections.

1.2.1 Four-Bank Memory Controller

• Works with SRAM, EPROM, Flash EEPROM, and other peripherals

• Byte write enables

• 32-bit address decodes with bit masks

USIU

RCPU

Burst

Interface

256 Kbytes

Flash

192 Kbytes

Flash

16 Kbytes

SRAM

10 Kbytes

SRAM

L2U

E-bus

UIMB

QADC QADC QSMCM TouCAN

TPU3 DPTRAM TPU3 TouCAN MIOS1

L-bus

IMB3

U-bus

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MPC555 Product Brief 3

Key Features

1.2.2 U-Bus System Interface Unit (USIU)

• Clock synt he siz er

• Power management

• Reset controller

• MPC555 decrementer and time base

• Real-time clock register

• Periodic interrupt timer

• Hardware bus monitor and software watchdog timer

• Interrupt controller that supports up to eight external and eight internal interrupts

• IEEE 1149.1 JTAG test access port

• External bus interface

— 24 address pins, 32 data pins

— Supports multiple master designs

— Four-beat transfer bursts, two-clock minimum bus transactions

— Supports 5V inputs, provides 3.3-V outputs

1.2.3 Flexible Memory Protection Unit

• Four instruction regions and four data regions

• 4-Kbyte to 16-Mbyte region size support

• Default attributes available in one global entry

• Attribute supp ort for speculative accesses

1.2.4 448-Kbyte Flash EEPROM Memory

• One 256-Kbyte and one 192-Kbyte module

• Page read mode

• Block (32 -Kbyte) eras able

• External 4.75-V to 5.25-V program and erase power supply

1.2.5 26-Kbytes of Static RAM

• One 16-Kbyte and one 10-Kbyte module

• Fast (one-clock) access

• Keep-alive power

• Soft defect detection (SDD)

1.2.6 General-Purpose I/O Support

• Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode

• Nine general-purpose I/O pins in MIOS1 unit

• Many peripheral pins can be used for general-purpose I/O when not used for primary function

• 5-V tolerant inputs/outputs

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Key Features

1.2.7 Two Time Processor Units (TPU3)

• Each TPU3 module provides these features:

— A dedicated micro-engine operates independently of the RCPU

— 16 independent programmable channels and pins

— Each channel has an event register consisting of a 16-bit capture register, a 16-bit compare

— Nine pre-programmed timer functions are available

— Any channel can perform any time function

— Each timer function can be assigned to more than one channel

— Two timer count registers with programmable prescalers

— Each channel can be synchronized to one or both counters

— Selectable channel priority levels

— 5-V tolerant inputs/outputs

• 6-Kbyte dual port TPU RAM (DPTRAM) is shared by the two TPU3 modules for TPU microcode

1.2.8 18-Channel Modular I/O System (MIOS1)

• Ten double action submodules (DASM)

• Eight dedicated PWM sub-modules (PWMSM)

• Two 16-bit modulus counter submodules (MCSM)

• Two parallel port I/O submodules (PIOSM)

• 5-V tolerant inputs/outputs

1.2.9 Two Queued Analog-to-Digital Converter Modules

(QADC64)

Each QADC provides:

• Up to 16 analog input channels, using internal multiplexing

• Up to 41 total input channels, using internal and external multiplexing

• 10-bit A/D converter with internal sample/hold

• Typical conversion time of 10 µs (100,000 samples per second)

• Two conversion command queues of variable length

• Automated queue modes initiated by:

— External edge trigger/level gate

— Software co mmand

• 64 resu lt regi sters

• Output data that is right- or left-justified, signed or unsigned

• 5-V reference and range

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MPC555 Product Brief 5

Key Features

1.2.10 Two CAN 2.0B Controller Modules (TouCAN)

Each TouCAN provides these features:

• Full implementation of CAN protocol specification, version 2.0A and 2.0B

• Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length

• Glo bal mask reg ister for message b uffers 0 to 13

• Independent mask registers for message buffers 14 and 15

• Programmable transmit-f irst sc heme: lowest ID or lowes t buffer number

• 16-bit free-running time r for message time-stamp ing

• Low power sleep mode with programmable wake-up on bus activity

• Programmable I/O modes

• Maskable interrupts

• Independent of the transmission medium (external transceiver is assumed)

• Open network architecture

• Multimaster concept

• Hig h immunity to EMI

• Short latency time for hi gh-priority messages

• Low power sleep mode with programmable wakeup on bus activity

1.2.11 Queued Serial Multi-Channel Module (QSMCM)

• Qu eued serial peripheral interface (QS PI)

— Provides full-duplex communication port for peripheral expansion or interprocessor

communication

— Up to 32 preprogrammed transfers, reducing overhead

— 160-byte queue buffer

— Programmable transfer length: from 8 to 16 bits, inclusive

— Synchronous interface with baud rate of up to system clock divided by 4

— Four programmable peripheral-select pins support up to 16 devices

— Wrap-around mode allows continuous sampling for efficient interfacing to serial peripherals

(e.g., – serial A/D converters, I/O latches, etc.)

• Two serial communications interfaces (SCI). Each SCI offers these features:

— UART mode provides NRZ format and half-or full-duplex interface

— 16 regi ster receive buffer and 16 regi ster transmit buffer (SCI1 only)

— Advanced error de tection and optional pari ty generation and detection

— Word length programmable as 8 or 9 bits

— Separate transmitter and receiver enable bits and double buffering of data

— Wakeup functi ons al low the CPU to run uni nterr upt ed unt il ei ther a true idle l ine i s de tect ed or

a new address byte is received

— External source clock for baud generation

— Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete

inputs, allowing realization of a low-speed serial protocol

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Key Features

2 MPC555 Addre ss Map

The internal memory map is shown in Figure 2.

Figure 2. MPC555 Internal Memory Map

0x30 7

0x2F

0x30 0000

USIU & Flash

16 Kbytes

0x38 0000

(10 Kbytes)

0x3F

USIU Control Registers

FLASH Module A (64 b ytes)

FLASH Module B (64 bytes)

Kbytes

0x2F C000

0x2F

0x30 8000

0x 37 FFFF

(4 80 Kbytes)

SR A M C ontr ol A

(8bytes)

0x3F 9800

(485.98 Kbytes)

0x38 0010

Res erved for USIU

2F C880

BFFF

FFFF

FFF

FFFF

0x2F C000

0x30 0000

0x30 7F80

0x30 7FFF

0x30 7080

0x30 7480

0x30 7884

DPTRAM (6 Kbytes)

QSMCM (4 Kbytes)

MIOS1 (4 Kbytes)

TouCAN_A (1 Kbyte)

TouCAN_B (1 Kbyte)

UIMB Registers

(128 bytes)

TPU3_A (1 Kbyte)

TPU3_B (1 Kbyte)

QADC_A (1 Kbyte)

QADC_B (1 Kbyte)

DPTRAM Control

Reserved (8180 bytes)

Reserved (2 Kbytes)

0x30 2000

0x30 4000

0x30 5000

0x30 6000

Reserved (1920 bytes)

(12 bytes)

IMB3 Address Space

0x2F C800

0x2F C840

UIMB Interface &

(32 Kbytes)

IMB3 Modules

CMF Flash A

Reserved for Flash

Control

Reserved for IMB3

Reserved

SRAM A

256

0x07 0000

0x00 0000

0x06 FFFF

0x30 4400

0x30 4800

0x30 4C00

Kbyte

Kbytes

CMF Flash B

192

SR A M C ontr ol B

0x38 0008

(8 bytes)

(16 Kbytes)

SRAM B

0x04 0000

0x3F C000

(2.6 Mbytes - 16 Kbytes)

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MPC555 Product Brief 7

Key Features

3 MPC555 Pinout Diagram

Figure 3 shows the pinout for the MPC555.

Figure 3. MPC555 Pinout Diagram

MPC555 Ball Map

12345678

11 12 13 14 15 16

718

920

VDDH

A_TPUC

TPUCH

4A_

TPU

CH8

_TPUCH

A_T

VRL AAN

0_PQ

B0 AA

N48_

PQB4

52_P

QA0

AAN5

4_PQ

2BA

N0_

BAN2

_PQB2

AN3_

PQB3

N51_

B7 VDDH MD

A11 M

DA12 MD

3 VDDH

B_T2CLK VDDH A_

PUCH6 A_TPUCH10 A_TPUCH11 A_TPUCH14 VRH AAN3_PQB3 AAN49_PQB5 AAN53_PQA1 AAN57_PQA5 BAN1_PQB1 BAN48_PQB4 BAN52_PQA0 BAN54_PQA2 E

RIG2 MDA14

DA15 VDDH

DA28

TPU

A_T

2CLK A_

TPUCH

3A_

TPU

CH7

_TP

UCH

9A_T

3 VDDA

AAN

2_PQ

B2 AA

N51_

PQB7

56_P

QA4

AAN5

9_PQ

7 BAN49

QB5 B

PQA1

N56_P

4BA

N57_

A5 E

G1 MD

A27 M

DA29 MD

0MDA

PUCH11 B_

PUCH13 A_

PUCH0 A_

PUCH2 A_TPUCH5 VDDI VSSA AAN1_PQB1 AAN50_PQB6 AAN55_PQA3 AAN58_PQA6 BAN50_PQB6 BAN55_PQA3 BAN58_PQA6 BAN59_PQA7 VDDI VDDL

PWM1 MPWM2

TPU

CH7 B_

PUCH10 B_T

PUCH

DL M

PWM

MPWM

PWM19 MPIO6

PUCH5 B_TPUCH6 B_

PUCH8 B_TPUCH12 MPW

PIO7 MPIO9

CH2 B_TPUC

3B_

TPU

4B_

TPU

CH9

PIO5 MPIO8

MPI

O11

PIO12

B_TPUCH1 B_TPUCH0 B_CNRX0 B_CNTX0 MPIO10 MPIO15 MPIO14 MPIO13

CK_ DSCK TDO_

DO TRST_B VDD SRAM VSS VSS VSS VSS V

2 _MPIO2 VFLS0

_MPIO3 VF0 _MPIO0 V

1 _

PIO1

TMS TDI_D

SDI S

DL VS

S VSS

VSS

VSS V

LVFLS1

_MPIO4

_CNTX0

_CN

LS I

0 _VFLS

Q3B

_SGP

IRQ4

_SGP VSS VSS VSS VSS

CS1

_QGP

_QGP MISO _QGP4

OSI _QGP5

IRQ0B

IRQ1B

_SGP

IRQ2B

SGP_

IRQOUTB VS

S VSS

VSS V

PCS3

_QGP

PCS2

_QGP ECK

SCK

_ QGP6

WEB_ A

[0] BRB_IWP2 BGB_LWP1 BBB _IWP3

Note

The pinout

is a

op down vie

he package.

D1_

QGPI

TXD1_

QGPO RXD2_ QGPI TXD2_

QGPO

B_ A

]

WEB_

AT[

2] WEB_ AT[3

]

CS0B VPP EPEE

DDH

RD_

BCS1B

VDD

L VDDF XFC

DSYN

OEB TEAB

1 VDDL VDDI KAPWR VSSSYN EXTAL

TSI

TAB TS

BBDIP

BVDD

IAddr_

GP31 Add

_ SGP30

ddr_

28 Add

GP29 VDDL Data_

GP29

a_ SGP27

ata_

SGP25 Da

DDL Data_

20 R

CFB

_TXP

EXT

CLK EC

BUCK XTAL

BURSTB BIB_STSB Addr_ SGP11 Addr_ SGP10 Addr_ SGP9 Addr_ SGP8 Addr_ SGP22 Addr_ SGP27 Data_ SGP31 Data_ SGP30 Data_ SGP28 Data_ SGP26 Data_ SGP24 Data_ SGP22 Data_ SGP21 Data_ SGP19 Data_ SGP18 CLKOUT PORESETB SRESETB

SGP12 V

HAdd

GP14

ddr_

SGP16 Addr_

18 Addr_

GP20 Addr_ SG

23 Addr_

a_ SGP1 Data_

GP5

ata_ SG

7Da

9Da

SGP11

a_ SGP13 Data_

15 Da

SGP17 I

_SGP VDD

H HRE

SETB

VDDH Addr_ SGP13 Addr_ SGP15 Addr_ SGP17 Addr_ SGP19 Addr_ SGP21 Addr_ SGP24 Addr_ SGP25 Data_ SGP0 Data_ SGP2 Data_ SGP4 Data_ SGP6 Data_ SGP8 Data_ SGP10 Data_ SGP12 Data_ SGP14 Data_ SGP16 IRQ6B _mck2 IRQ7B _mck3 VDDH

VDD

powe

(I/O

)

DDi

3 v

wer

(in

rnal

ound VDDH =5

vol

powe

=Misc

wer

Dees

bst

te 9

/30

/97

21 N

vembe

1997 V

ersio

10.2

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8MPC555 Product Brief

Key Features

4 Supporting Documentation List

This list contains references to currently available and planned documentation.

•MPC555 User ’s Manual (MPC555UM/AD)

•RCPU Reference Manual (RCPURM/AD)

•Board Strategies for Ensuring Optimum Frequency Synthesizer Performance (AN1282/D)

•Using the MIOS on the MPC555 Evaluation Board (AN1778/D)

•Exception Table Relocation and Multi-Processor Address Mapping in the Embedded MPC5XX

Family (AN1821/D)

•Non-Volatile Memory Technology Overview (AN1837/D)

•Designing Expansion Boards for the Freescale EVB555/ETAS ES200 (AN2001/D)

•MPC555 Interrupts (AN2109/D)

•EMC Guidelines for MPC500-Based Automotive Powertrain Systems (AN2127/D)

• Nexus Standard Specification (non-Freescale document)

• Nexus Web Site: http://www.nexus5001.org/

• IEEE 1149.1 Specification (non-Freescale document)

5 Revision History

Table 2. Revision History

Revision Number Substa ntive Changes Date of Release

2 Existing Document. September 2001

2.1 Added temperature range for suffix A device. 11 December 2002

3 Updated template and formats. 11 February 2003

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Key Features

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Key Features

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MPC555PB/D

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