September 2012 I
© 2012 Microsemi Corporation
SmartFusion Customizable System-on-Chip (cSoC)
Microcontroller Subsystem (MSS)
Hard 100 MHz 32-Bit ARM® Cortex™-M3
1.25 DMIPS/MHz Throughput from Zero Wait State
Memory
Memory Protection Unit (MPU)
Single Cycle Multiplication, Hardware Divide
JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Single Wire Viewer (SWV) Interfaces
Internal Memory
Embedded Nonvolatile Flash Memory (eNVM), 128
Kbytes to 512 Kbytes
Embedded High-Speed SRAM (eSRAM), 16 Kbytes
to 64 Kbytes, Implemented in 2 Physical Blocks to
Enable Simultaneous Access from 2 Different
Masters
Multi-Layer AHB Communications Matrix
Provides up to 16 Gbps of On-Chip Memory
Bandwidth,1 Allowing Multi-Master Schemes
10/100 Ethernet MAC with RMII Interface 2
Programmable External Memory Controller, Which
Supports:
Asynchronous Memories
NOR Flash, SRAM, PSRAM
Synchronous SRAMs
•Two I
2C Peripherals
Two 16550 Compatible UARTs
Two SPI Peripherals
Two 32-Bit Timers
32-Bit Watchdog Timer
8-Channel DMA Controller to Offload the Cortex-M3
from Data Transactions
Clock Sources
32 KHz to 20 MHz Main Oscillator
Battery-Backed 32 KHz Low Power Oscillator with
Real-Time Counter (RTC)
100 MHz Embedded RC Oscillator; 1% Accurate
Embedded Analog PLL with 4 Output Phases (0, 90,
180, 270)
High-Performance FPGA
Based on proven ProASIC®3 FPGA Fabric
Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,
Flash-Based CMOS Process
Nonvolatile, Live at Power-Up, Retains Program When
Powered Off
350 MHz System Performance
Embedded SRAMs and FIFOs
Variable Aspect Ratio 4,608-Bit SRAM Blocks
x1, x2, x4, x9, and x18 Organizations
True Dual-Port SRAM (excluding x18)
Programmable Embedded FIFO Control Logic
Secure ISP with 128-Bit AES via JTAG
FlashLock® to Secure FPGA Contents
Five Clock Conditioning Circuits (CCCs) with up to 2
Integrated Analog PLLs
Phase Shift, Multiply/Divide, and Delay Capabilities
Frequency: Input 1.5–350 MHz, Output 0.75 to
350 MHz
Programmable Analog
Analog Front-End (AFE)
Up to Three 12-Bit SAR ADCs
500 Ksps in 12-Bit Mode
550 Ksps in 10-Bit Mode
600 Ksps in 8-Bit Mode
Internal 2.56 V Reference or Optional External
Reference
One First-Order ΣΔ DAC (sigma-delta) per ADC
8-Bit, 16-Bit, or 24-Bit 500 Ksps Update Rate
Up to 5 High-Performance Analog Signal Conditioning
Blocks (SCB) per Device, Each Including:
Two High-Voltage Bipolar Voltage Monitors (with 4
input ranges from ±2.5 V to –11.5/+14 V) with 1%
Accuracy
High Gain Current Monitor, Differential Gain = 50, up
to 14 V Common Mode
Temperature Monitor (Resolution = ¼°C in 12-Bit
Mode; Accurate from –55°C to 150°C)
Up to Ten High-Speed Voltage Comparators
(tpd =15ns)
Analog Compute Engine (ACE)
Offloads Cortex-M3–Based MSS from Analog
Initialization and Processing of ADC, DAC, and SCBs
Sample Sequence Eng ine for ADC and DAC Parameter
Set-Up
Post-Processing Engine for Functions such as Low-
Pass Filtering and Linear Transformation
Easily Configured via GUI in Libero® System-on-Chip
(SoC) Software
I/Os and Operating Voltage
FPGA I/Os
LVDS, PCI, PCI-X, up to 24 mA IOH/IOL
Up to 350 MHz
MSS I/Os
Schmitt Trigger, up to 6 mA IOH, 8 mA IOL
Up to 180 MHz
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
External 1.5 V Is Allowed by Bypassing Regulator
(digital VCC = 1.5 V for FPGA and MSS, analog VCC =
3.3 V and 1.5 V)
1 Theoretical maximum
2 A2F200 and larger devices
Revision 9
SmartFusion Custo m izable System-on-Chip (cSoC)
II Revision 9
SmartFusion cSoC Family Product Table
FPGA Fabric
A2F060 A2F200 A2F500
TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484
System Gates 60,000 200,000 500,000
Tiles (D-flip-flops) 1,536 4,608 11,520
RAM Blocks (4,608 bits) 8 8 24
Microcontroller Subsystem (MSS)
A2F060 A2F200 A2F500
TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484
Flash (Kbytes) 128 256 512
SRAM (Kbytes) 16 64 64
Cortex-M3 pr oce sso r with MPU Yes Yes Yes
10/100 Ethernet MAC No Yes Yes
Externa l Memory Cont roller (EMC ) 26-/16-bit address/d ata 26-bit address,16-bi t data 26-/16-bit address/data
DMA 8 Ch 8 Ch 8 Ch
I2C222
SPI 1 2 1 2 1 2
16550 UART 2 2 2
32-Bit Timer 2 2 2
PLL 1 1 1 2 1 2
32 KHz Low Power Oscillator 1 1 1
100 MHz On-Chip RC Oscillator 1 1 1
Main Oscillator (32 KHz to 20 MHz) 1 1 1
Programmable Analog
A2F060 A2F200 A2F500
TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484
ADCs (8-/10-/12-bit SAR) 1 2 2 3
DACs (8-/16-/24-bit sigma-delta) 1 2 2 3
Signal Conditioning Blocks (SCBs) 1 4 4 5
Comparator* 2 8 8 10
Current Monitors* 1 4 4 5
Temperature Monito rs* 1 4 4 5
Bipolar High Voltage Monitors* 2 8 8 10
Note: *These functions sha re I/O pins and may no t all be available at the same ti me. See the "Analog Front-End Overview" section in
the SmartFusion Programmable Analog User’s Guide for details.
SmartFusion Customizable System-on-Ch ip (cSoC)
Revisi o n 9 III
Package I/Os: MSS + FPGA I/Os
SmartFusion cSoC Device Status
Device A2F060 A2F200 A2F500
Package TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484
Direct Analog Inputs 11 11 11 8 8 8 8 8 8 8 12
Shared Analog Inputs14 4 4 16 16 16 16 16 16 16 20
Total Analog Inputs 15 15 15 24 24 24 24 24 24 24 32
Total Analog Outputs1111222 1223
MSS I/Os2,3 21428426422 31 25 41 22 31 25 41
FPGA I/Os 33 68 66 66 78 66 94 66578 66 128
Total I/Os 70 112 108 113 135 117 161 113 135 117 204
Notes:
1. These pins are shared between direct analog inputs to th e ADCs and voltage/current/temperatur e monitors.
2. 16 MSS I/Os are multiplexed and can be used as F PGA I/Os, if not needed for MSS. The se I/Os support Schmitt triggers and
support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards.
3. 9 MSS I/Os are primarily for 10/100 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if Ethernet MAC is
not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V
standards.
4. 10/100 Ethernet MAC is not available on A2F060.
5. EMC is not available on the A2F500 PQ208 package.
Table 1 • SmartFusion cSoC Package Sizes Dimensions
Package TQ144 PQ208 CS288 FG256 FG484
Length × Width (mm\mm) 20 × 20 28 × 28 17 × 17 23 × 23
Nominal Area (mm2)400 784 289 529
Pitch (mm) 0.5 0.5 1.0 1.0
Height (mm) 1.40 3.40 1.60 2.23
Device Status
A2F060 Preliminary: CS288, FG256, TQ144
A2F200 Production: CS288, FG25 6, FG484, PQ208
A2F500 Production: CS288, FG25 6, FG484, PQ208
SmartFusion Custo m izable System-on-Chip (cSoC)
IV Revision 9
SmartFusion cSoC Block Diagram
Legend:
SDD – Sigma-delta DAC
SCB – Signal conditioning block
PDMA – Peripheral DMA
IAP – In-application programming
ABPS – Active bipolar prescaler
WDT – Watchdog Timer
SWD – Serial Wire Debug
Microcontroller Subsystem
Programmable Analog
FPGA Fabric
SRAM SRAM SRAM SRAM SRAM SRAM
SysReg
ENVM
10/100
EMAC
ESRAM
Timer2
Timer1
APB
I2C 2
UART 2
SPI 2
DAC
(SDD)
DAC
(SDD)
PPB
........
........
............
VersaTiles
3 V
I2C 1
UART 1
SPI 1
IAP PDMA APB EMC
AHB Bus Matrix
EFROM
APB
Sample Sequencing
Engine
Post Processing
Engine
ADC
Analog Compute
Engine
PLL
Supervisor
WDT
OSC
32 KHz
RC
+
RTC
JTAG
Cortex
-M3
SWD
NVIC SysTick
MPU
SDI
Volt Mon.
(ABPS)
Temp.
Mon.
SCB
Curr.
Mon. Comparator
ADC
Volt Mon.
(ABPS)
Temp.
Mon.
SCB
Curr.
Mon. Comparator
3
V
............
....
SmartFusion Customizable System-on-Ch ip (cSoC)
Revisi o n 9 V
SmartFusion cSoC System Architecture
Note: Architecture for A2F200
Bank 4 Bank 5
Bank 0
Bank 3
Bank 1 Bank 2
PLL/CCC MSS FPGA Analog
ISP AES Decryption Charge Pumps
Embedded NVM
(eNVM)
Cortex-M3 Microcontroller Subsystem (MSS)
Embedded SRAM
(eSRAM)
Embedded FlashROM
(eFROM)
SCB SCB ADC and DAC ADC and DAC SCB SCB
Osc. CCC
SmartFusion Custo m izable System-on-Chip (cSoC)
VI Revision 9
Product Ordering Codes
Temperature Grade Offerings
Note: *Most devices in the SmartFusion cSoC family can be ordered with the Y suffix. D evice s with a package size greater or equal to
5x5 mm are supported. Contact your local Microsemi SoC Products Group sales re prese ntative for more information.
SmartFusion cSoC A2F060 A2F200 A2F500
TQ144 C, I
PQ208 C, I C, I
CS288 C, I C, I C, I
FG256 C, I C, I C, I
FG484 C, I C, I
Notes:
1. C = Commercial Temperature Range: 0°C to 85°C Junction
2. I = Industrial Temperature Range: –40°C to 100°C Junction
A2F200 FG
_
Part Number
SmartFusion Devices
Speed Grade
–1 = 100 MHz MSS Speed; FPGA Fabric 15% Faster than Standard
= 80 MHz MSS Speed; FPGA Fabric at Standard Speed
CPU T ype
M3
M3 = Cortex-M3
Package T ype
484 IG
Package Lead Count
256
208
288
484
Application (junction temperature range)
Y
Security Feature*
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Commercial (0 to +85°C)
I = Industrial (–40 to +100°C)
ES = Engineering Silicon (room temperature only)
200,000 System Gates
A2F200 =
60,000 System Gates
A2F060 =
500,000 System Gates
A2F500 =
PQ =Plastic Quad Flat Pack (0.5 mm pitch)
TQ =Thin Quad Flat Pack (0.5 mm pitch)
FG =Fine Pitch Ball Grid Array (1.0 mm pitch)
CS =Chip Scale Package (0.5 mm pitch)
F
eNVM Size
A= 8 Kbytes
B=16 Kbytes
C=32 Kbytes
D=64 Kbytes
E=128 Kbytes
F=256 Kbytes
G=512 Kbytes
Lead-Free Packaging Options
G = RoHS-Compliant (green) Packaging
Blank = Standard Packaging
1
Blank
Currently only the following eNVM sizes are available
per device:
A2F500M3 – G
A2F200M3 – F
A2F060M3 – E