Internally Trimmed
Precision IC Multiplier
Data Sheet
AD632
Rev. D Document Feedback
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FEATURES
Pretrimmed to ±0.5% maximum 4-quadrant error
All inputs (X, Y, and Z) differential, high impedance for
[(X1 − X2)(Y1 − Y2)/10] + Z2 transfer function
Scale-factor adjustable to provide up to ×10 gain
Low noise design: 90 mV rms, 10 Hz to 10 kHz
Low cost, monolithic construction
Excellent long-term stability
APPLICATIONS
High quality analog signal processing
Differential ratio and percentage computations
Algebraic and trigonometric function synthesis
Accurate voltage controlled oscillators and filters
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD632 is an internally trimmed monolithic four-quadrant
multiplier/divider. The AD632B has a maximum multiplying
error of ±0.5% without external trims.
Excellent supply rejection, low temperature coefficients, and
long-term stability of the on-chip thin film resistors and buried
zener reference preserve accuracy even under adverse conditions.
The simplicity and flexibility of use provide an attractive alternative
approach to the solution of complex control functions.
The AD632 is pin-for-pin compatible with the industry
standard AD532 but with improved specifications and a fully
differential high impedance Z input. The AD632 is capable of
providing gains of up to ×10, frequently eliminating the need
for separate instrumentation amplifiers to precondition the
inputs. The AD632 can be effectively employed as a variable
gain differential input amplifier with high common-mode
rejection. The effectiveness of the variable gain capability is
enhanced by the inherent low noise of the AD632 at 90 µV rms.
PRODUCT HIGHLIGHTS
1. Guaranteed performance over temperature.
2. The AD632A and AD632B are specified for maximum
multiplying errors of ±1.0% and ±0.5% of full scale,
respectively, at +25°C and are rated for operation from
−25°C to +85°C.
3. Maximum multiplying errors of ±2.0% (AD632S) and
±1.0% (AD632T) are guaranteed over the extended
temperature range of −55°C to +125°C.
4. High reliability.
5. The AD632S and AD632T series are available with MIL-
STD-883 Level B screening.
6. All devices are available in either the hermetically sealed
TO-100 metal can or ceramic DIP package.
STABLE
REFERENCE
AND BIAS
+V
S
–V
S
TRANSFER FUNCTION
HIGH GAIN
OUTPUT
AMPLIFIER
OUT
TRANSLINEAR
MULTIPLIER
ELEMENT
0.75 AT TEN
V
O
= A – (Z
1
– Z
2
)
(X
1
– X
2
) (Y
1
– Y
2
)
10
A
V-I
X
1
X
2
V-I
Y
1
Y
2
V-I
Z
1
Z
2
V
OS
2.7kΩ
25kΩ
09040-007
AD632 Data Sheet
Rev. D | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance .......................................................................5
Pin Configurations and Function Descriptions ............................6
Typical Performance Characteristics ..............................................7
Operation As a Multiplier ................................................................8
Operation As a Divider .....................................................................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 11
REVISION HISTORY
5/13—Rev. C to Rev. D
Changes to Table 1 ............................................................................. 3
Changes to Ordering Guide ........................................................... 11
12/11—Rev. B to Rev. C
Updated Format .................................................................. Universal
Added Figure 1, Renumbered Sequentially ................................... 1
Deleted Chip Dimensions and Pad Layout Section ...................... 5
Changes to Figure 3 and Figure 4 ................................................... 6
Added Table 3 and Table 4 .............................................................. 6
Changes to the Operations as a Divider Section .......................... 9
Updated Outline Dimensions ....................................................... 10
4/10—Rev. A to Rev. B
Changes to Pin Configurations and Product Highlights
Sections .............................................................................................. 1
Changes to Thermal Characteristics Section ................................ 3
Updated Outline Dimensions ......................................................... 6
Changes to Ordering Guide ............................................................ 6
Data Sheet AD632
Rev. D | Page 3 of 12
SPECIFICATIONS
@ +25°C, VS = ±15 V, R ≥ 2 kΩ, unless otherwise noted. Specifications shown in boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoing quality levels.
Table 1.
AD632A AD632B AD632S AD632T
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
MULTIPLIER PERFORMANCE
Transfer Function
2
2121
Z
YYXX
+
−−
V10
)()(
2
2121
Z
YYXX
+
−−
V10
)()(
2
2121 Z
YYXX
+
−−
V10
)()(
2
2121
Z
YYXX
+
−−
V10
)()(
Total Error1 (−10 V ≤ X, Y ≤ +10
V)
±1.0 ±0.5 ±1.0 ±0.5 %
TA = Min to Max ±1.5 ±1.0 ±2.0 ±1.0 %
Total Error vs. Temperature
±0.022
±0.015
±0.02
±0.01
%/°C
Scale Factor Error
(SF = 10,000 V Nominal)
2
±0.25 ±0.1 ±0.25 ±0.1 %
Temperature Coefficient of
Scaling Voltage
±0.02 ±0.01 ±0.2 ±0.005 %/°C
Supply Rejection (±15 V ± 1 V) ±0.01 ±0.01 ±0.01 ±0.01 %
Nonlinearity
X (X = 20 V p-p, Y = 10 V) ±0.4 ±0.2 ±0.3 ±0.4 ±0.2 ±0.3 %
Y (Y = 20 V p-p, X = 10 V) ±0.2 ±0.1 ±0.1 ±0.2 ±0.1 ±0.1 %
Feedthrough3
X (Y Nulled, X = 20 V p-p 50 Hz) ±0.3 ±0.15 ±0.3 ±0.3 ±0.15 ±0.3 %
Y (X Nulled, Y = 20 V p-p 50 Hz) ±0.01 ±0.01 ±0.1 ±0.01 ±0.01 ±0.1 %
Output Offset Voltage ±5 ±30 ±2 ±15 ±5 ±30 ±2 ±15 mV
Output Offset Voltage Drift
200
100
500
300
µV/°C
DYNAMICS
Small Signal BW, (VOUT = 0.1 rms) 1 1 1 1 MHz
1% Amplitude Error
(CLOAD = 1000 pF)
50 50 50 50 kHz
Slew Rate (VOUT 20 p-p) 20 20 20 20 V/µs
Settling Time (to 1%, ΔVOUT = 20 V) 2 2 2 2 µs
NOISE
Noise Spectral Density
SF = 10 V 0.8 0.8 0.8 0.8 µV/√Hz
SF = 3 V4 0.4 0.4 0.4 0.4 µV/√Hz
Wideband Noise
A = 10 Hz to 5 MHz 1.0 1.0 1.0 1.0 mV/rms
P = 10 Hz to 10 kHz 90 90 90 90 µV/rms
OUTPUT
Output Voltage Swing ±11 ±11 ±11 ±11 V
Output Impedance (f ≤ 1 kHz) 0.1 0.1 0.1 0.1 Ω
Output Short-Circuit Current
(RL = 0, TA = Min to Max) 30 30 30 30 mA
Amplifier Open-Loop Gain
(f = 50 Hz)
70 70 70 70 dB
INPUT AMPLIFIERS (X, Y, and Z)
5
Signal Voltage Range
(Differential or Common-
Mode Operating Diff.)
±10 ±12 ±10 ±12 ±10 ±12 ±10 ±12 V
Offset Voltage X, Y ±5 ±20 ±2 ±10 ±5 ±20 ±2 ±10 mV
Offset Voltage Drift X, Y 100 50 100 150 µV/°C
Offset Voltage Z ±5 ±30 ±2 ±15 ±5 ±30 ±2 ±15 mV
Offset Voltage Drift Z 200 100 500 300 µV/°C
CMRR 60 80 70 90 60 80 70 90 dM
Bias Current 0.8 2.0 0.8 2.0 0.8 2.0 0.8 2.0 µA
Offset Current 0.1 0.1 0.1 0.1 µA
Differential Resistance 10 10 10 10 MΩ
AD632 Data Sheet
Rev. D | Page 4 of 12
AD632A AD632B AD632S AD632T
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
DIVIDER PERFORMANCE
Transfer Function(X1 > X2)
1
21
1
2
Y
X
X
ZZ
+
−
−
)
(
)
(
V
10
1
2
1
1
2
Y
XX
Z
Z
+
−
−
)
(
)
(
V
10
1
21
1
2Y
X
X
Z
Z
+
−
−
)
(
)
(
V
10
1
2
1
12
Y
X
X
Z
Z
+
−
−
)
(
)
(
V10
Total Error1
(X = 10 V, −10 V ≤ Z ≤ +10 V) ±0.75 ±0.35 ±0.75 ±0.35 %
(X = 1 V, −1 V ≤ Z ≤ +1 V) ±2.0 ±1.0 ±2.0 ±1.0 %
(0.1 V ≤ X ≤ 10 V, −10 V ≤ Z ≤
10 V)
±2.5 ±1.0 ±2.5 ±1.0 %
SQUARER PERFORMANCE
Transfer Function
2
21
Z
XX
+
−
V10
)(
2
2
21
Z
XX
+
−
V10
)(
2
2
21
Z
XX
+
−
V10
)(
2
2
21
Z
XX
+
−
V10
)(
2
Total Error (−10 V ≤ X ≤ 10 V) ±0.6 ±0.3 ±0.6 ±0.3 %
SQUARE-ROOTER PERFORMANCE
Transfer Function, (Z1 ≤ Z2)
212 XZZ +− )(V10
2
1
2XZ
Z+− )
(V
10
2
1
2XZ
Z+− )
(V
10
212
XZZ +− )(V10
Total Error1 (1 V ≤ Z ≤ 10 V) ±1.0 ±0.5 ±1.0 ±0.5 %
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance
±15
±15
±15
±15
V
Operating ±8 ±18 ±8 ±18 ±8 ±22 ±8 ±22 V
Supply Current
Quiescent 4 6 4 6 4 6 4 6 mA
1 Figures given are percent of full-scale, ±10 V (that is, 0.01% = 1 mV).
2 Can be reduced to 3 V using an external resistor between –VS and SF.
3 Irreducible component due to nonlinearity: excludes effect of offsets.
4 Using an external resistor adjusted to give a value of SF = 3 V.
5 See the functional block diagram (Figure 1) for definition of sections.
Data Sheet AD632
Rev. D | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 2. Thermal Resistance
Package Type θJA θ
JC Unit
10-Lead TO-100 150 25 °C/W
14-Lead SBDIP 95 25 °C/W
AD632 Data Sheet
Rev. D | Page 6 of 12
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration, H-Package, TO-100
Figure 3. Pin Configuration, D-Package, SBDIP
Table 3. Pin Function Descriptions, 10-Pin TO-100
Pin No. Mnemonic Description
1 Y1 Y Multiplicand Noninverting Input.
2 +VS Positive Supply Voltage.
3 Z1 Summing Node Noninverting Input.
4 OUT Product.
5 −VS Negative Supply Voltage.
6 X1 X Multiplicand Noninverting Input.
7 X2 X Multiplicand Inverting Input.
8 Z2 Summing Node Inverting Input.
9 VOS Offset Voltage Adjustment.
10 Y2 Y Multiplicand Inverting Input.
Table 4. Pin Function Descriptions, 14-Lead SBDIP
Pin No. Mnemonic Description
1 Z1 Summing Node Noninverting Input.
2 OUT Product.
3 −VS Negative Supply Voltage.
4, 5, 6, 8 NC No Connection. Do not connect to
this pin.
7 X1 X Multiplicand Noninverting Input.
9 X2 X Multiplicand Noninverting Input.
10 Z2 Summing Node Inverting Input.
11 VOS Offset Voltage Adjustment.
12 Y2 Y Multiplicand Inverting Input.
13 Y1 Y Multiplicand Noninverting Input.
14 +VS Positive Supply Voltage.
V
OS
Z2 (GND)
Y2
–V
S
Z1 OUT
+V
S
Y1
X2
X1
6
7
8
9
10
34
2
1
5
(Not to Scale)
AD632
09040-001
1
2
3
4
+V
S
14
Y1
13
Y2
12
V
OS
11
5
Z2
10
6
X2
9
Z1
OUT
–V
S
NC
NC
NC
X1
7
NC
8
NC = NO CONNECT
AD632
TOP VIEW
(Not to Scale)
09040-002
Data Sheet AD632
Rev. D | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
Typical @ 25°C with ±VS = 15 V.
Figure 4. AC Feedthrough vs. Frequency
Figure 5. Frequency Response as a Multiplier
Figure 6. Frequency Response vs. Divider Denominator Input Voltage
1000
0.110 10M
09040-004
FE E DTHROUGH (mV p-p )
FRE QUENCY ( Hz )
100 1k 10k 100k 1M
100
10
1
Y F E E DTHROUGH
X F E E DTHROUGH
–30
10k 10M
09040-005
OUTPUT RESPONSE (dB)
FREQUENCY ( Hz )
100k 1M
0
–10
–20
CL = 0pF
CL = 1000pF
NORMAL
CONNECTION
CL ≤ 1000pF
CF ≤ 200pF
WI TH ×10
FEEDBACK
ATTENUATOR
CL ≤ 1000pF
CF = 0pF
0dB = 0.1V rms, RL = 2kΩ
40
20
0
V
O
V
z
–201k 10M
09040-006
OUTPUT (dB )
FREQUENCY ( Hz )
10k 100k 1M
V
X
= 100mV DC
V
Z
= 10mV rms
V
X
= 1V DC
V
Z
= 100mV rms
V
X
= 10V DC
V
Z
= 1V rms
0dB = 1V rms, R
L
= 2kΩ
AD632 Data Sheet
Rev. D | Page 8 of 12
OPERATION AS A MULTIPLIER
Figure 7 shows the basic connection for multiplication. Note
that the circuit meets all specifications without trimming.
Figure 7. Basic Multiplier Connection
When needed, the user can reduce ac feedthrough to a minimum
(as in a suppressed carrier modulator) by applying an external
trim voltage (±30 mV range required) to the X or Y input. Figure 4
shows the typical ac feedthrough with this adjustment mode.
Note that the feedthrough of the Y input is a factor of 10 lower
than that of the X input and is to be used for applications where
null suppression is critical.
The Z2 terminal of the AD632 can be used to sum an additional
signal into the output. In this mode, the output amplifier behaves
as a voltage follower with a 1 MHz small signal bandwidth and
a 20 V/μs slew rate. Always reference this terminal to the ground
point of the driven system, particularly if this is remote. Like-
wise, reference the differential inputs to their respective signal
common potentials to realize the full accuracy of the AD632.
A much lower scaling voltage can be achieved without any reduc-
tion of input signal range using a feedback attenuator, as shown
in Figure 8. In this example, the scale is such that VOUT = XY, so
that the circuit can exhibit a maximum gain of 10. This connection
results in a reduction of bandwidth to about 80 kHz without the
peaking capacitor, CF. In addition, the output offset voltage is
increased by a factor of 10 making external adjustments necessary
in some applications.
Feedback attenuation also retains the capability for adding a
signal to the output. Signals can be applied to the Z terminal,
where they are amplified by −10, or to the common ground
connection where they are amplified by −1. Input signals can
also be applied to the lower end of the 2.7 kΩ resistor, giving a
gain of +9.
Figure 8. Connections for Scale Factor of Unity
X
1
+V
S
X
2
V
OS
OUT
Z
1
Z
2
Y
1
Y
2
–V
S
–15V
+15V
X INPUT
±10V FS
±12V PK
Y INPUT
±10V FS
±12V PK
OUTPUT, ±12V PK
(X
1
– X
2
) (Y
1
– Y
2
)
OPTIONAL SUMMIN
G
INPUT, Z, ±10V PK;
V
OS
TERMINAL
NOT USED
10 + Z
2
=
09040-008
X
1
+V
S
X
2
OUT
Z
1
Z
2
V
OS
Y
1
Y
2
–V
S
–15V
+15V
X INPUT
±10V FS
±12V PK
Y INPUT
±10V FS
±12V PK
OUTPUT, ±12V PK
= (X
1
– X
2
) (Y
1
– Y
2
)
(SCALE = 1)
09040-009
Data Sheet AD632
Rev. D | Page 9 of 12
OPERATION AS A DIVIDER
Figure 9 shows the connection required for division. Unlike
earlier products, the AD632 provides differential operation on
both the numerator and the denominator, allowing the ratio of
two floating variables to be generated. Further flexibility results
from access to a high impedance summing input to Y1. As with
all dividers based on the use of a multiplier in a feedback loop,
the bandwidth is proportional to the denominator magnitude,
as shown in Figure 6.
The accuracy of the AD632 B-model is sufficient to maintain a
1% error over a 10 V to 1 V denominator range.
Figure 9. Basic Divider Connection
X
1
+V
S
X
2
+V
S
OUT
V
OS
Z
1
–V
S
Z
2
Y
1
Y
2
–V
S
–15V
+15V
X INPUT
(DENOMINATOR)
+10V FS
+12V PK
Z INPUT
(NUMERATOR)
±10V FS, ±12V PK
OPTIONAL
SUMMING INPUT
±10V PK
+
–
+15V
–15V
2kΩ
TO
200kΩ
10 (Z
2
– Z
1
)
(X
1
– X
2
)+ Y
1
=
OUTPUT, ±12V PK
09040-010
AD632 Data Sheet
Rev. D | Page 10 of 12
OUTLINE DIMENSIONS
Figure 10. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-14)
Dimensions shown in inches and (millimeters)
Figure 11. 10-Pin Metal Header Package [TO-100]
(H-10)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
14
17
80.310 (7.87)
0.220 (5.59)
PIN 1
0.080 (2.03) MAX
0.005 (0.13) MIN
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18) 0.070 (1.78)
0.030 (0.76)
0.100 (2.54)
BSC
0.150
(3.81)
MIN
0.765 (19.43) MAX
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH E QUIVALENTS FOR
REF E RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
DIMENSIONS PER JEDEC STANDARDS M O-006- AF
0.500 (12.70)
MIN
0.185 ( 4.70)
0.165 ( 4.19)
REF E RE NCE P LANE
0.050 ( 1.27) MAX
0.040 ( 1.02) MAX
0.335 ( 8.51)
0.305 ( 7.75)
0.370 ( 9.40)
0.335 ( 8.51)
0.021 ( 0.53)
0.016 ( 0.40)
10.034 ( 0.86)
0.025 ( 0.64)
0.045 ( 1.14)
0.025 ( 0.65)
0.160 ( 4.06)
0.110 (2.79)
6
2
8
7
5
4
3
0.115
(2.92)
BSC 9
10
0.230 ( 5.84)
BSC
BASE & S EATING PLANE
36° BSC
022306-A
Data Sheet AD632
Rev. D | Page 11 of 12
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
AD632AD −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632ADZ −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632AHZ −25°C to +85°C 10-Pin Metal Header Package [TO-100] H-10
AD632BD −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632BDZ −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632BHZ −25°C to +85°C 10-Pin Metal Header Package [TO-100] H-10
AD632SD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632SH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD632SH/883B −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD632TD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632TD/883B −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632TH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD632TH/883B
−55°C to +125°C
10-Pin Metal Header Package [TO-100]
H-10
1 Z = RoHS Compliant Part.
