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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DDesigned for High-Speed Multipoint Data
Transmission Over Long Cables
DOperates With Pulse Widths as Low
as 30 ns
DLow Supply Current ...5 mA Max
DMeets or Exceeds the Standard
Requirements of ANSI RS-485 and
ISO 8482:1987(E)
DCommon-Mode Voltage Range of −7 V
to 12 V
DPositive- and Negative-Output Current
Limiting
DDriver Thermal Shutdown Protection
DPin Compatible With the SN75179B
description
The SN65LBC179, SN65LBC179Q, and
SN75LBC179 d i fferential driver and receiver pairs
are monolithic integrated circuits designed for
bidirectional data communication over long
cables that take on the characteristics of
transmission lines. They are balanced, or
differential, voltage mode devices that meet or
exceed the requirements of industry standards
ANSI RS-485 and ISO 8482:1987(E). Both
devices are designed using TI’s proprietary
LinBiCMOS with the low power consumption of
CMOS and the precision and robustness of
bipolar transistors in the same circuit.
The SN65LBC179, SN65LBC179Q, and
SN75LBC179 combine a differential line driver
and differential line receiver and operate from a
single 5-V supply. The driver differential outputs
and the receiver differential inputs are connected
to separate terminals for full-duplex operation and
are designed to present minimum loading to the
bus when powered off (VCC = 0). These parts
feature a wide common-mode voltage range
making them suitable for point-to-point or
multipoint data bus applications. The devices also
provide positive- and negative-current limiting
and thermal shutdown for protection from line fault
conditions. The line driver shuts down at a junction
temperature of approximately 172°C.
Copyright 1994 − 2006, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments.
l
ogic symbol†
l
ogic diagram (positive logic)
Y
Z
B
A
R
D5
6
7
8
2
3
R
D
B
A
Z
Y
7
8
6
5
2
3
†This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
INPUT
DOUTPUTS
Y Z
DRIVER
DIFFERENTIAL INPUTS
A−B
VID ≥ 0.2 V
−0.2 V < VID < 0.2 V
VID ≤ − 0.2 V
Open circuit
OUTPUT
R
H
?
L
H
RECEIVER
H = high level, L = low level,
? = indeterminate
Function Tables
1
2
3
4
8
7
6
5
VCC
R
D
GND
A
B
Z
Y
D OR P PACKAGE
(TOP VIEW)
H
LH
LL
H
SLLS173F − JANUARY 1994 − REVISED APRIL 2006
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The SN65LBC179, SN65LBC179Q, and SN75LBC179 are available in the 8-pin dual-in-line and small-outline
packages. The SN75LBC179 is characterized for operation over the commercial temperature range of 0°C to
70°C. The SN65LBC179 is characterized over the industrial temperature range of −40°C to 85°C. The
SN65LBC179Q is characterized over the extended industrial or automotive temperature range of − 40°C to
125°C.
schematics of inputs and outputs
RECEIVER A INPUTEQUIVALENT OF DRIVER INPUT RECEIVER B INPUT
DRIVER OUTPUT TYPICAL OF RECEIVER OUTPUT
Output
VCC
VCC
100 kΩ
NOM
3 kΩ
NOM
Input
18 kΩ
NOM
1.1 kΩ
NOM
1.1 kΩ
NOM
3 kΩ
NOM
18 kΩ
NOM
100 kΩ
NOM
Input
VCC
Input
VCC
22 kΩ
VCC
R Output
12 kΩ12 kΩ
SLLS173F − JANUARY 1994 − REVISED APRIL 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings†
Supply voltage range, VCC −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at A, B, Y, or Z (see Note 1) −10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at D or R (see Note 1) −0.3 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver output current, IO ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation (see Note 2) Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The maximum operating junction temperature is internally limited. Uses the dissipation rating table to operate below this
temperature.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
High-level input voltage, VIH D 2 V
Low-level input voltage, VIL D 0.8 V
Differential input voltage, VID −6‡6 V
Voltage at any bus terminal (separately or common-mode), VO, VI, or VIC A, B, Y, or Z −7 12 V
High-level output current, IOH
Y or Z −60
mA
High-level output current, IOH R−8 mA
Low-level output current, IOL
Y or Z 60
mA
Low-level output current, IOL R 8 mA
Junction temperature, TJ140 °C
SN65LBC179 −40 85
Operating free-air temperature, T
A
SN65LBC179Q −40 125 °C
Operating free-air temperature, TA
SN75LBC179 0 70
C
‡The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for differential
input voltage, voltage at any bus terminal (separately or common mode), operating temperature, input threshold voltage, and common-mode
output voltage.
DISSIPATION RATING TABLE
PACKAGE THERMAL
MODEL TA < 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
D
Low K†526 mW 5.0 mW/°C301 mW 226 mW
DHigh K‡882 mW 8.4 mW/°C 504 mW 378 mW
P840 mW 8.0 mW/°C480 mW 360 mW
†In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3.
‡In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7.
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DRIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input clamp voltage II = −18 mA −1.5 V
RL = 54 Ω,
See Figure 1
SN65LBC179,
SN65LBC179Q 1.1 2.2 5
|VOD|
Differential output voltage (see Note 3)
L
See Figure 1
SN75LBC179 1.5 2.2 5
V
|VOD|Differential output voltage (see Note 3) RL = 60 Ω,
See Figure 2
SN65LBC179,
SN65LBC179Q 1.1 2.2 5 V
L
See Figure 2
SN75LBC179 1.5 2.2 5
∆|VOD|Change in magnitude of differential output voltage
(see Note 4) See Figures 1 and 2 ±0.2 V
VOC Common-mode output voltage 1 2.5 3 V
∆|VOC|Change in magnitude of common-mode output
voltage (see Note 4) RL = 54 Ω,See Figure 1 ±0.2 V
IOOutput current with power off VCC = 0, VO = −7 V to 12 V ±100 µA
IIH High-level input current VI = 2.4 V −100 µA
IIL Low-level input current VI = 0.4 V −100 µA
IOS Short-circuit output current −7 V ≤ VO ≤ 12 V ±250 mA
ICC
Supply current
No load
SN65LBC179,
SN75LBC179 4.2 5 mA
ICC
Supply current
No load
SN65LBC179Q 4.2 7 mA
†All typical values are at VCC = 5 V and TA = 25°C.
NOTES: 3. The minimum VOD specification of the SN65179 may not fully comply with ANSI RS-485 at operating temperatures below 0°C.
System designers should take the possibly lower output signal into account in determining the maximum signal transmission
distance.
4. ∆|VOD| and ∆|VOC| are the changes in the steady-state magnitude of VOD and VOC, respectively, that occur when the input is
changed from a high level to a low level.
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(OD) Differential-output delay time
RL = 54 Ω
See Figure 3
7 18 ns
tt(OD) Differential transition time
R
L
= 54
Ω,
See Figure 3
5 20 ns
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RECEIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage IO = −8 mA 0.2 V
VIT− Negative-going input threshold voltage IO = 8 mA −0.2 V
Vhys Hysteresis voltage (VIT+ − VIT−) 45 mV
VOH High-level output voltage VID = 200 mV, IOH = −8 mA 3.5 4.5 V
VOL Low-level output voltage VID = −200 mV, IOL = 8 mA 0.3 0.5 V
VI = 12 V,
Other inputs at 0 V,
SN65LBC179,
SN75LBC179 0.7 1 mA
Other inputs at 0 V,
VCC = 5 V SN65LBC179Q 0.7 1.2 mA
VI = 12 V,
Other inputs at 0 V,
SN65LBC179,
SN75LBC179 0.8 1 mA
II
Bus input current
Other inputs at 0 V,
VCC = 0 V SN65LBC179Q 0.8 1.2 mA
I
I
Bus input current
VI = −7 V,
Other inputs at 0 V,
SN65LBC179,
SN75LBC179 −0.5 −0.8 mA
Other inputs at 0 V,
VCC = 5 V SN65LBC179Q −0.5 −1.0 mA
VI = −7 V,
Other inputs at 0 V, SN65LBC179,
SN75LBC179 −0.5 −0.8 mA
Other inputs at 0 V,
VCC = 0 V SN65LBC179Q −0.5 −1.0 mA
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHL Propagation delay time, high- to low-level output
VID = −1.5 V to 1.5 V,
See Figure 4
15 30 ns
tPLH Propagation delay time, low- to high-level output VID = −1.5 V to 1.5 V, See Figure 4 15 30 ns
tsk(p) Pulse skew (tPHL − tPLH)
See Figure 4
3 6 ns
ttTransition time
See Figure 4
3 5 ns
PARAMETER MEASUREMENT INFORMATION
VOD
RL
2
0 V or 3 V
Z
D
Y
RL
2VOC
Figure 1. Differential and Common-Mode Output Voltage Test Circuit
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOD
Vtest
R1
375 Ω
0 V or 3 V
Z
D
R2
375 Ω
Vtest
Y
RL = 60 Ω
−7 V < Vtest < 12 V
Figure 2. Differential Output Voltage Test Circuit
0 V
3 V
tt(OD)
tt(OD)
1.5 V
td(ODH)
50%
Output
Input
TEST CIRCUIT VOLTAGE WAVEFORMS
td(ODL)
RL = 54 ΩOutput
Generator
(see Note A) 50 Ω
1.5 V
50% ≈2.5 V
≈ − 2.5 V
CL = 50 pF
(see Note B)
1.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO=50Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuits and Differential Output Delay and Transition Time Voltage Waveforms
TEST CIRCUIT VOLTAGE WAVEFORMS
VOL
VOH
3 V
0 V
tPHL
tPLH
Output
Input
1.3 V
1.5 V
1.3 V
50 ΩOutput
1.5 V
Generator
(see Note A)
A
B
tt
90%
10%10%
90%
tt
CL = 15 pF
(see Note B)
1.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO=50Ω.
B. CL includes probe and jig capacitance.
Figure 4. Receiver Test Circuit and Propagation Delay and Transition Time Voltage Waveforms
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TYPICAL CHARACTERISTICS
2.5
1.5
1
00102030
− High-Level Output Voltage − V
3.5
4
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
40 50 60
VOH
IOH − High-Level Output Current − mA
4.5
3
2
0.5
VCC = 5 V
TA = 25°C
2.5
1.5
1
00204060
− Low-Level Output Voltage − V
3.5
4
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
80 100 120
VOL
IOL − Low-Level Output Current − mA
4.5
3
2
0.5
VCC = 5 V
TA = 25°C
70 80 90 100
Figure 5 Figure 6
2
1.5
0.5
00102030405060
− Differential Output Voltage − V
2.5
3.5
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4
70 80 90 100
1
3
VCC = 5 V
TA = 25°C
VOD
IO − Output Current − mA
2
1.5
0.5
0
− 50 − 25 0 25
2.5
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
50 75
1
3VCC = 5 V
Load = 54 Ω
VIH = 2 V
TA − Free-Air Temperature − °C100 125
− Differential Output Voltage − V
VOD
Figure 7 Figure 8
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TYPICAL CHARACTERISTICS
2
1
00 −10 − 20 − 30
− High-Level Output Voltage − V
3
4
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
− 40 − 50
IOH − High-Level Output Current − mA
VOH
20
15
5
0
− 50 − 25 0 25
− Differential Delay Times − ns
DRIVER
DIFFERENTIAL DELAY TIME
vs
FREE-AIR TEMPERATURE
50 75
10
VCC = 5 V
Load = 54 Ω
TA − Free-Air Temperature − °C100 125
td(ODH)
td(ODL)
6VID = 200 mV
td(OD)
Figure 9 Figure 10
0.3
0.2
0.1
00510
− Low-Level Output Voltage − V
0.4
0.5
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
15 20 25 30
IOL − Low-Level Output Current − mA
VOL
VCC = 5 V
TA = 25°C
VID = − 200 mV
0.7
0.8
0.9
1
35 40
2
1
0
− Output Voltage − V
3
4
RECEIVER
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
5
VID − Differential Input Voltage − mV
VO
− 80 − 60 − 40 − 20 0 20 40 60 80
6
VIC = 12 V
VIC = 0 V
VIC = −7 V
Figure 11 Figure 12
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TYPICAL CHARACTERISTICS
40
5
25
15
0
50
30
10 K 100 K 1 M 10 M 100 M
45
10
20
AVERAGE SUPPLY CURRENT
vs
FREQUENCY
35
60
55
− Average Supply Current − mAICC
f − Frequency − Hz
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
− 0.4
− 0.6
− 0.8
− 1
− 8 − 6 − 4 − 2 0 2
− Input Current − mA
− 0.2
0
RECEIVER
INPUT CURRENT
vs
INPUT VOLTAGE
(COMPLEMENTARY INPUT AT 0 V)
0.2
468
10 12
0.4
0.6
0.8
II
VI − Input Voltage − V
1TA = 25°C
VCC = 5 V
The shaded region of this graph represents
more than 1 unit load per RS-485.
Receiver Load = 50 pF
Driver Load = Receiver Inputs
Figure 13 Figure 14
23.5
23
22.5
22
− 40 − 20 0 20 40 60
− Propagation Delay Time − ns
24
24.5
RECEIVER
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
80 100
TA − Free-Air Temperature − °C
tPHL
tPLH
VCC = 5 V
CL = 15 pF
VIO = ±1.5 V
tpd
Figure 15
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THERMAL CHARACTERISTICS − D PACKAGE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Junction−to−ambient thermal reisistance, θJA†
Low-K board, no air flow 199.4
Junction−to−ambient thermal reisistance, θJA
†
High-K board, no air flow 119
°C/W
Junction−to−board thermal reisistance, θJB High-K board, no air flow 67 °C/W
Junction−to−case thermal reisistance, θJC 46.6
Average power dissipation, P(AVG) RL = 54 Ω, input to D is 10 Mbps 50% duty
cycle square wave, VCC = 5.25 V, TJ = 130
°C. 330 mW
Thermal shutdown junction temperature, TSD 165 °C
†See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
SLLS173F − JANUARY 1994 − REVISED APRIL 2006
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THERMAL CHARACTERISTICS OF IC PACKAGES
ΘJA (Junction-to-Ambient Thermal Resistance) i s defined as the difference in junction temperature to ambient temperature
divided by the operating power
ΘJA is NOT a constant and is a strong function of
Dthe PCB design (50% variation)
Daltitude (20% variation)
Ddevice power (5% variation)
ΘJA can be used to compare the thermal performance of packages if the specific test conditions are defined and used.
Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures. ΘJA is often misused when it is used to calculate junction temperatures for other
installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in ΘJA can be measured between these two test cards
ΘJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.
ΘJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict
junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with ΘJB in 1-dimensional thermal simulation of a package system.
ΘJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is only
defined for the high-k test card.
ΘJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance
(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see Figure 16).
Surface Node
qJC Calculated/Measured
Junction
qJB Calculated/Measured
PC Board
qCA Calculated
Ambient Node
Figure 16. Thermal Resistance
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LBC179D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC179DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC179DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC179DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC179P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65LBC179PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65LBC179QD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC179QDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC179QDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC179QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC179D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC179DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC179DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC179DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC179P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75LBC179PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 26-Mar-2010
Addendum-Page 1
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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PACKAGE OPTION ADDENDUM
www.ti.com 26-Mar-2010
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LBC179DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75LBC179DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Mar-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC179DR SOIC D 8 2500 340.5 338.1 20.6
SN75LBC179DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Mar-2010
Pack Materials-Page 2
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