SLLS173F - JANUARY 1994 - REVISED APRIL 2006 D Designed for High-Speed Multipoint Data D D D D D D D D OR P PACKAGE (TOP VIEW) Transmission Over Long Cables Operates With Pulse Widths as Low as 30 ns Low Supply Current . . . 5 mA Max Meets or Exceeds the Standard Requirements of ANSI RS-485 and ISO 8482:1987(E) Common-Mode Voltage Range of - 7 V to 12 V Positive- and Negative-Output Current Limiting Driver Thermal Shutdown Protection Pin Compatible With the SN75179B VCC R D GND The SN65LBC179, SN65LBC179Q, and SN75LBC179 combine a differential line driver and differential line receiver and operate from a single 5-V supply. The driver differential outputs and the receiver differential inputs are connected to separate terminals for full-duplex operation and are designed to present minimum loading to the bus when powered off (VCC = 0). These parts feature a wide common-mode voltage range making them suitable for point-to-point or multipoint data bus applications. The devices also provide positive- and negative-current limiting and thermal shutdown for protection from line fault conditions. The line driver shuts down at a junction temperature of approximately 172C. 8 2 7 3 6 4 5 A B Z Y Function Tables DRIVER INPUT D H L OUTPUTS Y Z H L L H RECEIVER description The SN65LBC179, SN65LBC179Q, and SN75LBC179 differential driver and receiver pairs are monolithic integrated circuits designed for bidirectional data communication over long cables that take on the characteristics of transmission lines. They are balanced, or differential, voltage mode devices that meet or exceed the requirements of industry standards ANSI RS-485 and ISO 8482:1987(E). Both devices are designed using TI's proprietary LinBiCMOS with the low power consumption of CMOS and the precision and robustness of bipolar transistors in the same circuit. 1 DIFFERENTIAL INPUTS OUTPUT A -B R H VID 0.2 V ? -0.2 V < VID < 0.2 V L VID - 0.2 V H Open circuit H = high level, ? = indeterminate L = low level, logic symbol R D 8 2 7 6 3 5 A B Z Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) R D 2 3 8 7 5 6 A B Y Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments. Copyright 1994 - 2006, Texas Instruments Incorporated !"# $ %&'# "$ (&)*%"# +"#', +&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$ $#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1 "** (""!'#'$, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLLS173F - JANUARY 1994 - REVISED APRIL 2006 description (continued) The SN65LBC179, SN65LBC179Q, and SN75LBC179 are available in the 8-pin dual-in-line and small-outline packages. The SN75LBC179 is characterized for operation over the commercial temperature range of 0C to 70C. The SN65LBC179 is characterized over the industrial temperature range of - 40C to 85C. The SN65LBC179Q is characterized over the extended industrial or automotive temperature range of - 40C to 125C. schematics of inputs and outputs EQUIVALENT OF DRIVER INPUT RECEIVER A INPUT RECEIVER B INPUT VCC VCC VCC 100 k NOM 22 k 3 k NOM 3 k NOM 18 k NOM Input 18 k NOM Input Input 12 k 12 k 1.1 k NOM DRIVER OUTPUT 100 k NOM 1.1 k NOM TYPICAL OF RECEIVER OUTPUT VCC VCC R Output Output 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLLS173F - JANUARY 1994 - REVISED APRIL 2006 absolute maximum ratings Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V Voltage range at A, B, Y, or Z (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 V to 15 V Voltage range at D or R (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.5 V Receiver output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. The maximum operating junction temperature is internally limited. Uses the dissipation rating table to operate below this temperature. recommended operating conditions Supply voltage, VCC High-level input voltage, VIH D Low-level input voltage, VIL D MIN NOM MAX UNIT 4.75 5 5.25 V 2 V -6 Differential input voltage, VID Voltage at any bus terminal (separately or common-mode), VO, VI, or VIC A, B, Y, or Z -7 Y or Z High-level output current, IOH Low-level output current, IOL 0.8 V 6 V 12 V -60 R -8 Y or Z 60 R 8 Junction temperature, TJ 140 Operating free-air temperature, TA SN65LBC179 -40 85 SN65LBC179Q -40 125 mA mA C C C SN75LBC179 0 70 The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for differential input voltage, voltage at any bus terminal (separately or common mode), operating temperature, input threshold voltage, and common-mode output voltage. DISSIPATION RATING TABLE PACKAGE THERMAL MODEL TA < 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING Low K High K 526 mW 5.0 mW/C 301 mW 226 mW D 882 mW 8.4 mW/C 504 mW 378 mW P 840 mW 8.0 mW/C 480 mW In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51-3. In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51-7. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 360 mW 3 SLLS173F - JANUARY 1994 - REVISED APRIL 2006 DRIVER SECTION electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIK TEST CONDITIONS Input clamp voltage TYP II = - 18 mA RL = 54 , See Figure 1 | VOD | MIN Differential output voltage (see Note 3) RL = 60 , See Figure 2 UNIT -1.5 V SN65LBC179, SN65LBC179Q 1.1 2.2 5 SN75LBC179 1.5 2.2 5 SN65LBC179, SN65LBC179Q 1.1 2.2 5 SN75LBC179 1.5 2.2 5 | VOD | Change in magnitude of differential output voltage (see Note 4) VOC Common-mode output voltage | VOC | Change in magnitude of common-mode output voltage (see Note 4) RL = 54 , See Figure 1 IO IIH Output current with power off VCC = 0, VI = 2.4 V VO = - 7 V to 12 V IIL IOS Low-level input current Short-circuit output current VI = 0.4 V -7 V VO 12 V ICC Supply current No load V See Figures 1 and 2 1 High-level input current MAX SN65LBC179, SN75LBC179 2.5 4.2 0.2 V 3 V 0.2 V 100 A -100 A -100 A 250 mA 5 mA SN65LBC179Q 4.2 7 mA All typical values are at VCC = 5 V and TA = 25C. NOTES: 3. The minimum VOD specification of the SN65179 may not fully comply with ANSI RS-485 at operating temperatures below 0C. System designers should take the possibly lower output signal into account in determining the maximum signal transmission distance. 4. | VOD | and | VOC | are the changes in the steady-state magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. switching characteristics, VCC = 5 V, TA = 25C PARAMETER td(OD) tt(OD) 4 TEST CONDITIONS Differential-output delay time RL = 54 , Differential transition time POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 See Figure 3 MIN MAX 7 18 UNIT ns 5 20 ns SLLS173F - JANUARY 1994 - REVISED APRIL 2006 RECEIVER SECTION electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT + VIT - Positive-going input threshold voltage Vhys VOH Hysteresis voltage ( VIT + - VIT -) VOL Low-level output voltage II MIN IO = - 8 mA IO = 8 mA Negative-going input threshold voltage High-level output voltage MAX 0.2 -0.2 VID = 200 mV, VID = - 200 mV, Bus input current TYP IOH = - 8 mA IOL = 8 mA 3.5 UNIT V V 45 mV 4.5 V 0.3 0.5 VI = 12 V, Other inputs at 0 V, VCC = 5 V SN65LBC179, SN75LBC179 V 0.7 1 mA SN65LBC179Q 0.7 1.2 mA VI = 12 V, Other inputs at 0 V, VCC = 0 V SN65LBC179, SN75LBC179 0.8 1 mA SN65LBC179Q 0.8 1 .2 mA VI = - 7 V, Other inputs at 0 V, VCC = 5 V SN65LBC179, SN75LBC179 -0.5 -0.8 mA SN65LBC179Q -0.5 -1.0 mA VI = - 7 V, Other inputs at 0 V, VCC = 0 V SN65LBC179, SN75LBC179 -0.5 -0.8 mA SN65LBC179Q -0.5 -1.0 mA TYP MAX UNIT switching characteristics, VCC = 5 V, TA = 25C PARAMETER TEST CONDITIONS tPHL tPLH Propagation delay time, high- to low-level output tsk(p) tt Pulse skew ( tPHL - tPLH ) Propagation delay time, low- to high-level output VID = -1.5 V to 1.5 V, MIN See Figure 4 15 30 ns 15 30 ns 3 6 ns 3 5 ns See Figure 4 Transition time PARAMETER MEASUREMENT INFORMATION Y RL 2 D VOD 0 V or 3 V RL 2 VOC Z Figure 1. Differential and Common-Mode Output Voltage Test Circuit POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLLS173F - JANUARY 1994 - REVISED APRIL 2006 PARAMETER MEASUREMENT INFORMATION Vtest R1 375 Y D RL = 60 0 V or 3 V VOD Z R2 375 -7 V < Vtest < 12 V Vtest Figure 2. Differential Output Voltage Test Circuit 3V Input Generator (see Note A) RL = 54 50 1.5 V 1.5 V 0V td(ODL) 2.5 V 50% - 2.5 V td(ODH) CL = 50 pF Output (see Note B) 50% Output tt(OD) TEST CIRCUIT tt(OD) VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. Figure 3. Driver Test Circuits and Differential Output Delay and Transition Time Voltage Waveforms 3V Input 1.5 V A Generator (see Note A) 50 1.5 V 0V Output B tPLH tPHL 1.5 V CL = 15 pF (see Note B) Output 90% 1.3 V 10% tt TEST CIRCUIT VOH 90% 1.3 V 10% VOL tt VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. Figure 4. Receiver Test Circuit and Propagation Delay and Transition Time Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLLS173F - JANUARY 1994 - REVISED APRIL 2006 TYPICAL CHARACTERISTICS DRIVER DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 5 VCC = 5 V TA = 25C 4.5 VCC = 5 V TA = 25C 4.5 VOL- Low-Level Output Voltage - V VOH - High-Level Output Voltage - V 5 4 3.5 3 2.5 2 1.5 1 0.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0 10 20 30 40 50 60 70 80 90 100 IOH - High-Level Output Current - mA 0 80 100 20 40 60 IOL - Low-Level Output Current - mA Figure 5 Figure 6 DRIVER DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 4 3 VCC = 5 V TA = 25C VOD - Differential Output Voltage - V VOD - Differential Output Voltage - V 3.5 3 2.5 2 1.5 1 0.5 0 120 0 10 20 30 40 50 60 70 80 IO - Output Current - mA 90 100 2.5 VCC = 5 V Load = 54 VIH = 2 V 2 1.5 1 0.5 0 - 50 - 25 Figure 7 0 25 50 75 100 TA - Free-Air Temperature - C 125 Figure 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLLS173F - JANUARY 1994 - REVISED APRIL 2006 TYPICAL CHARACTERISTICS DRIVER RECEIVER DIFFERENTIAL DELAY TIME vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 6 20 VID = 200 mV td(ODL) VOH - High-Level Output Voltage - V t d(OD) - Differential Delay Times - ns VCC = 5 V Load = 54 15 td(ODH) 10 5 0 - 50 5 4 3 2 1 0 - 25 100 50 75 0 25 TA - Free-Air Temperature - C 125 0 - 40 -10 - 20 - 30 IOH - High-Level Output Current - mA Figure 9 Figure 10 RECEIVER RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 1 6 VCC = 5 V TA = 25C VID = - 200 mV 0.8 5 VIC = 12 V 0.7 4 VO - Output Voltage - V VOL - Low-Level Output Voltage - V 0.9 0.6 0.5 0.4 0.3 0.2 VIC = 0 V 3 2 VIC = -7 V 1 0.1 0 0 5 10 15 20 25 30 35 IOL - Low-Level Output Current - mA 40 0 - 80 - 60 - 40 - 20 0 Figure 12 POST OFFICE BOX 655303 20 40 60 VID - Differential Input Voltage - mV Figure 11 8 - 50 * DALLAS, TEXAS 75265 80 SLLS173F - JANUARY 1994 - REVISED APRIL 2006 TYPICAL CHARACTERISTICS RECEIVER INPUT CURRENT vs INPUT VOLTAGE (COMPLEMENTARY INPUT AT 0 V) AVERAGE SUPPLY CURRENT vs FREQUENCY 60 1 Receiver Load = 50 pF Driver Load = Receiver Inputs 0.8 50 0.6 45 0.4 I I - Input Current - mA 40 35 30 25 20 15 10 0 10 K 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 5 100 K 1M 10 M IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII TA = 25C VCC = 5 V -1 -8 100 M The shaded region of this graph represents more than 1 unit load per RS-485. -6 -4 -2 0 2 4 6 8 10 12 VI - Input Voltage - V f - Frequency - Hz Figure 13 Figure 14 RECEIVER PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 24.5 t pd - Propagation Delay Time - ns I CC - Average Supply Current - mA 55 VCC = 5 V CL = 15 pF VIO = 1.5 V 24 tPHL 23.5 23 tPLH 22.5 22 - 40 - 20 0 20 40 60 80 100 TA - Free-Air Temperature - C Figure 15 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLLS173F - JANUARY 1994 - REVISED APRIL 2006 THERMAL CHARACTERISTICS - D PACKAGE TEST CONDITIONS PARAMETER Junction-to-ambient thermal reisistance, JA Junction-to-board thermal reisistance, JB TYP 199.4 High-K board, no air flow 119 High-K board, no air flow 67 Junction-to-case thermal reisistance, JC Average power dissipation, P(AVG) MIN Low-K board, no air flow MAX UNIT C/W 46.6 RL = 54 , input to D is 10 Mbps 50% duty cycle square wave, VCC = 5.25 V, TJ = 130 C. 330 mW Thermal shutdown junction temperature, TSD 165 C See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter. 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLLS173F - JANUARY 1994 - REVISED APRIL 2006 THERMAL CHARACTERISTICS OF IC PACKAGES JA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature divided by the operating power JA is NOT a constant and is a strong function of D D D the PCB design (50% variation) altitude (20% variation) device power (5% variation) JA can be used to compare the thermal performance of packages if the specific test conditions are defined and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. JA is often misused when it is used to calculate junction temperatures for other installations. TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in-use condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4% to 50% difference in JA can be measured between these two test cards JC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. JC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and junction temperatures are backed out. It can be used with JB in 1-dimensional thermal simulation of a package system. JB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate structure. JB is only defined for the high-k test card. JB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance (especially for BGA's with thermal balls) and can be used for simple 1-dimensional network analysis of package system (see Figure 16). Ambient Node qCA Calculated Surface Node qJC Calculated/Measured Junction qJB Calculated/Measured PC Board Figure 16. Thermal Resistance POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LBC179D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC179DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC179DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC179DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC179P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65LBC179PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65LBC179QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC179QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC179QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC179QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC179D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC179DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC179DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC179DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC179P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75LBC179PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2010 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LBC179DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN75LBC179DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LBC179DR SOIC D 8 2500 340.5 338.1 20.6 SN75LBC179DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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