This is information on a product in full production.
July 2013 DocID024491 Rev 2 1/15
15
STB9NK80Z
Automotive-grade N-channel 800 V, 1.5 Ω typ., 5.2 A
Zener-protected SuperMESH™ Power MOSFETs in D2PAK package
Datasheet
-
production data
Figure 1. Internal schematic diagram
Features
•Designed for automotive applications and
AEC-Q101 qualified
•Extremely high dv/dt capability
•100% avalanche tested
•Gate charge minimized
•Zener-protected
•Very low intrinsic capacitances
Applications
•Switching application
Description
This device is an N-channel Zener-protected
Power MOSFET developed using
STMicroelectronics' SuperMESH™ technology,
achieved through optimization of ST's well
established strip-based PowerMESH™ layout. In
addition to a significant reduction in on-
resistance, this device is designed to ensure a
high level of dv/dt capability for the most
demanding applications.
D
2
PAK
1
3
TAB
'7$%
*
6
AM01476v1
Type V
DS
(@Tjmax) R
DS(on)
max. I
D
STB9NK80Z 800V 1.8Ω5.2A
Table 1. Device summary
Order codes Marking Package Packaging
STB9NK80Z B9NK80Z D²PAK Tape and reel
www.st.com
Contents STB9NK80Z
2/15 DocID024491 Rev 2
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DocID024491 Rev 2 3/15
STB9NK80Z Electrical ratings
1 Electrical ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
V
DS
Drain-source voltage 800 V
V
GS
Gate- source voltage ± 30 V
I
D
Drain current (continuous) at T
C
= 25 °C 5.2 A
I
D
Drain current (continuous) at T
C
= 100 °C 3.3 A
I
DM (1)
1. Pulse width limited by junction temperature.
Drain current (pulsed) 20.8 A
P
TOT
Total dissipation at T
C
= 25°C 125 W
Derating factor 1 W/°C
ESD Gate-source human body model (C = 100 pF, R = 1.5 kΩ)4 kV
dv/dt
(2)
2. I
SD
≤ 5.2 A, di/dt ≤ 200 A/μs, V
DD
≤ V
(BR)DSS
Peak diode recovery voltage slope 4.5 V/ns
Tj
Tstg
Max operating junction temperature
Storage temperature -55 to 150 °C
Table 3. Thermal data
Symbol Parameter Value Unit
R
thj-case
Thermal resistance junction-case max 1 °C/W
R
thj-amb
Thermal resistance junction-ambient max 62.5 °C/W
Table 4. Avalanche characteristics
Symbol Parameter Value Unit
I
AR
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tj Max) 5.2 A
E
AS
Single pulse avalanche energy
(starting T
J
= 25 °C, I
D
= I
AR
, V
DD
= 50 V) 210 mJ
Ele ctrical characterist ics STB9NK80Z
4/15 DocID024491 Rev 2
2 Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Table 5. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Breakdown voltage I
D
=1 mA, V
GS
= 0 800 V
I
DSS
Zero gate voltage
Drain Current (V
GS
= 0)
V
DS
= 800 V
V
DS
= 800 V, T
C
= 125 °C
1
50
μA
μA
I
GSS
Gate-body leakage
Current (V
DS
= 0) V
GS
= ± 20 V ± 10 μA
V
GS(th)
Gate threshold voltage V
DS
= V
GS
, I
D
= 100 μA 3 3.75 4.5 V
R
DS(on)
Static drain-source on
resistance V
GS
= 10 V, I
D
= 2.6 A 1.5 1.8 Ω
Table 6. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
g
fs (1)
1. Pulsed: pulse duration=300μs, duty cycle 1.5%
Forward transconductance V
DS
= 15 V, I
D
= 2.6 A - 5 - S
C
iss
Input capacitance
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0
-1138- pF
C
oss
Output capacitance - 122 - pF
C
rss
Reverse transfer
capacitance -25- pF
C
oss eq. (2)
2. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
.
Equivalent output
capacitance V
DS
=0 , V
DS
= 0 to 640 V - 50 - pF
t
d(on)
Turn-on delay time
V
DD
= 400 V, I
D
= 2.6 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 15)
-20- ns
t
r
Rise time - 12 - ns
t
r(off)
Turn-off delay time - 45 - ns
t
r
Fall time - 22 - ns
Q
g
Total gate charge V
DD
= 640 V, I
D
= 2.6 A,
V
GS
= 10 V
(see Figure 16)
-40-nC
Q
gs
Gate-source charge - 7 - nC
Q
gd
Gate-drain charge - 2.1 - nC
t
r(Voff)
Off-voltage rise time V
DD
= 640 V, I
D
= 2.6 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 15)
-12- ns
t
r
Fall time - 10 - ns
t
c
Cross-over time - 20 - ns
DocID024491 Rev 2 5/15
STB9NK80 Z Electri cal chara ct er istics
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
Table 7. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
SD
I
SDM(1)
1. Pulsed: pulse duration=300μs, duty cycle 1.5%
Source-drain current
Source-drain current (pulsed) -5.2
20.8
A
A
V
SD(2)
2. Pulse width limited by safe operating area
Forward on voltage I
SD
= 5.2 A, V
GS
= 0 - 1.6 V
t
rr
Reverse recovery time I
SD
= 5.2 A, di/dt = 100
A/μs
V
DD
= 50 V, Tj = 150°C
(see Figure 20)
- 530 ns
Q
rr
Reverse recovery charge - 3.31 μC
I
RRM
Reverse recovery current - 12.5 A
Table 8. Gate-source zener diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR) GSO
Gate-source breakdown voltage I
D
= 0
I
GS
= ± 1mA 30 V
Ele ctrical characterist ics STB9NK80Z
6/15 DocID024491 Rev 2
2.1 Electrica l characterist ics (curves)
Figure 2. Safe operating area Figure 3. Thermal impedance
Figure 4. Output characteristics Figure 5. Transfer characteristics
Figure 6. Transconductance Figure 7. Static drain-source on-resistance
DocID024491 Rev 2 7/15
STB9NK80 Z Electri cal chara ct er istics
Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations
Figure 10. Normalized gate threshold voltage vs
temperature Figure 11. Normalized on-resistance vs
temperature
Figure 12. Source -drain diode forward
characteristic Figure 13. Normali ze d BVDSS vs temperature
Ele ctrical characterist ics STB9NK80Z
8/15 DocID024491 Rev 2
Figure 14. Maximum avalanche energy vs
temperature
DocID024491 Rev 2 9/15
STB9NK80Z Test circuits
3 Test circuits
Figure 15. Switching times test circuit for
resistive load Figure 16. Gate charge test circuit
Figure 17. Test circuit for inductive load
switching and diode recovery times Figure 18. Unclamped inductive load test circuit
Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform
AM01468v1
VGS
PW
VD
RG
RL
D.U.T.
2200
μF
3.3
μFVDD
AM01469v1
VDD
47kΩ1kΩ
47kΩ
2.7kΩ
1kΩ
12V
Vi=20V=VGMAX
2200
μF
PW
IG=CONST
100Ω
100nF
D.U.T.
VG
AM01470v1
A
D
D.U.T.
S
B
G
25 Ω
AA
BB
RG
G
FAST
DIODE
D
S
L=100μH
μF
3.3 1000
μFVDD
AM01471v1
Vi
Pw
VD
ID
D.U.T.
L
2200
μF
3.3
μFVDD
AM01472v1
V(BR)DSS
VDD
VDD
VD
IDM
ID
AM01473v1
VDS
ton
tdon tdoff
toff
tf
tr
90%
10%
10%
0
0
90%
90%
10%
VGS
Package mechanical data STB9NK80Z
10/15 DocID024491 Rev 2
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 9. D²PAK (TO-263) mechanical data
Dim. mm
Min. Typ. Max.
A4.40 4.60
A1 0.03 0.23
b0.70 0.93
b2 1.14 1.70
c0.45 0.60
c2 1.23 1.36
D8.95 9.35
D1 7.50
E 10 10.40
E1 8.50
e2.54
e1 4.88 5.28
H 15 15.85
J1 2.49 2.69
L2.29 2.79
L1 1.27 1.40
L2 1.30 1.75
R0.4
V2 0° 8°
DocID024491 Rev 2 11/15
STB9NK80Z Package mechanical data
Figure 21. D²PAK (TO-263) drawing
Figure 22. D²PAK footprint
(a)
a. All dimension are in millimeters
0079457_T
16.90
12.20
9.75
3.50
5.08
1.60
Footprint
Packagi ng mechanic al da ta STB9NK80 Z
12/15 DocID024491 Rev 2
5 Packaging mechanical data
Table 10. D²PAK (TO-263) tape and reel mechanical data
Tape Reel
Dim. mm Dim. mm
Min. Max. Min. Max.
A0 10.5 10.7 A 330
B0 15.7 15.9 B 1.5
D 1.5 1.6 C 12.8 13.2
D1 1.59 1.61 D 20.2
E 1.65 1.85 G 24.4 26.4
F 11.4 11.6 N 100
K0 4.8 5.0 T 30.4
P0 3.9 4.1
P1 11.9 12.1 Base qty 1000
P2 1.9 2.1 Bulk qty 1000
R50
T 0.25 0.35
W 23.7 24.3
DocID024491 Rev 2 13/15
STB9NK80Z Packaging mechanical data
Figure 23. Tape
Figure 24. Reel
P1
A0 D1
P0
F
W
E
D
B0
K0
T
User direction of feed
P2
10 pitches cumulative
tolerance on tape +/- 0.2 mm
User direction of feed
R
Bending radius
Top cover
tape
AM08852v2
A
D
B
Full radius G measured at hub
C
N
REEL DIMENSIONS
40mm min.
Access hole
At slot location
T
Tape slot
in core for
tape start 25 mm min.
width
AM08851v2
Revision history STB9NK80Z
14/15 DocID024491 Rev 2
6 Revision history
Table 11. Document revision history
Date Revision Changes
05-Jun-2013 1 First issue.
12-Jul-2013 2 Document status promoted from preliminary to production data.
DocID024491 Rev 2 15/15
STB9NK80Z
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