Freescale Semiconductor Technical Data Document Number: MC33897 Rev. 18.0, 4/2012 Single Wire CAN Transceiver 33897 The 33897 series provides a physical layer for digital communication using a Carrier Sense Multiple Access/Collision Resolution (CSMA/CR) data link operating over a single wire medium. This is more commonly referred to as single-wire Controller Area Network (SWCAN). The 33897 series operates directly from a vehicle's 12 V battery system or a broad range of DC-power sources. It can operate at low or high (33.33 kbps or 83.33 kbps) data rates. A high-voltage wake-up feature allows the device to control the regulator used in support of the MCU and other logic. The device includes a control pin that can be used to put the module regulator into Sleep mode. The presence of a defined wake-up voltage level on the bus will reactivate the control line to turn the regulator and the system back ON. The device complies with the GMW3089v2.4 General Motors Corporation specification. SINGLE-WIRE CAN TRANSCEIVER EF (PB-FREE) SUFFIX 98ASB42565B 14-PIN SOICN Features * * * * * * * ORDERING INFORMATION Waveshaping for low Electromagnetic Interference (EMI) Detects and automatically handles loss of ground Worst-case Sleep mode current of only 60 A Current limit prevents damage due to bus shorts Built-in thermal shutdown on bus output Protected against vehicular electrical transients Under-voltage lockout prevents false data with low battery Device Temperature Range (TA) Package -40 to 125 C 14 SOICN MCZ33897TEF/R2 *MC33897CTEF/R2 *Recommended device for all new designs Power source Voltage Regulator EN Battery 33897 VBATT CNTL VCC TXD MCU BUS RXD MODE 0 LOAD MODE 1 GND 4 Figure 1. 33897 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2006 - 2012. All rights reserved. SWC Bus DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations Part No. Load Voltage Sleep Mode See Page 33897T 1.0 V Max 7 *33897CT 0.1 V Max 7 *Recommended device for all new designs 33897 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM TXD BUSDRVR DRVR TX Bus MODE0 MODE1 HV WU E n HVWU Enable Wa ve Sha ping E nEnable Waveshaping Mode Mode Co ntrol Control TX Dat Data a TXD BUS Disab le Disable Bus BUSRCVR RCVR HVWU HV WU De Detect t RX Dat a Disab le RXD Data Disable TXD RXD Timers Undervoltage Detect VBATT BAT Load Switch LOAD Timer OSC GND CNTL Figure 2. 33897 Simplified Internal Block Diagram 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS PIN CONNECTIONS 33897 GND 1 14 GND TXD 2 13 NC MODE0 3 12 BUS MODE1 4 11 LOAD RXD 5 10 VBATT NC 6 9 CNTL GND 7 8 GND Figure 3. 33897 Pin Connections Table 2. Pin Definitions A functional description of each pin can be found in the Functional Pin Description section, beginning on page 12. 33897 Pin Pin Name Formal Name Definition 1, 7, 8, 14 GND Ground Electrical Common Ground and Heat removal. A good thermal path will also reduce the die temperature. 2 TXD Transmit Data Data input here will appear on the BUS pin. A logic [0] will assert the bus, a logic [1] will make the bus go to the recessive state. 3, 4 MODE0, MODE1 Mode Control These Pins control Sleep mode, Transmit Level, and Speed. They have weak pulldowns. 5 RXD Receive Data Open drain output of the data on BUS. A recessive bus = a logic [1], a dominant bus = logic [0]. An external pull-up is required. 6, 13 NC No Connect 9 CNTL Control Provides a battery level logic signal. 10 VBATT Battery Power input. An external diode is needed for reverse battery protection. 11 LOAD Load The external bus load resistor connects here to prevent bus pull-up in the event of loss of module ground. 12 BUS Bus This pin connects to the bus through external components. No internal connection to these Pins. Pin 13 can be connected to GND. 33897 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit VBATT - 0.3 to 40 V VIN - 0.3 to 7.0 V RXD Pin Voltage VRXD - 0.3 to 7.0 V CNTL Pin Voltage VCNTL - 0.3 to 40 V Electrical Ratings Supply Voltage Input Logic Voltage ESD Voltage(1) VESD V Human Body Model All Pins Except BUS 2000 BUS Pin 4000 Machine Model 100 Thermal Ratings Ambient Operating Temperature(1) TA - 40 to 125 C Junction Operating Temperature TJ - 40 to 150 C TSTG - 55 to 150 C RJA 150 C/W TPPRT Note 3. C Storage Temperature Junction-to-Ambient Thermal Resistance Peak Package Reflow Temperature During Reflow (2), (3) Notes 1. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), Machine Model (CZAP = 200 pF, RZAP = 0 ). 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions of -40 C TA 125 C, unless otherwise stated. Voltages are relative to GND, unless otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit IQSLP - 45 60 A IQATDIS - - 4.0 mA IQATEN - - 9.0 Under-voltage Shutdown VBATTUV 4.0 - 5.0 V Under-voltage Hysteresis VUVHYS 0.1 - 0.5 V 150 - 190 GENERAL Quiescent Current Sleep 5.0 V VBATT 13 V (4) Awake with Transmitter Disabled 5.0 V VBATT 26.5 V Awake with Transmitter Enabled 5.0 V VBATT 26.5 V Thermal Shutdown (5) TSD 5.0 V VBATT 26.5 V Thermal Shutdown Hysteresis (5) C TSDHYS 5.0 V VBATT 26.5 V mA C 10 - 20 - - 0.8 2.0 - - LOGIC I /O, MODE0, MODE1, TXD, RXD Logic Input Low Level (MODE0, MODE1, and TXD) VIL 5.0 V VBATT 26.5 V Logic Input High Level (MODE0, MODE1, and TXD) VIH 5.0 V VBATT 26.5 V Mode Pin Pull-down Current (MODE0 and MODE1) V A IPD Pin Voltage = 0.8 V, 5.0 V VBATT 26.5 V Receiver Output Low (RXD) V 10 - 50 - - 0.45 - - 0.8 VOL IIN = 2.0 mA, 5.0 V VBATT 26.5 V V CNTL CNTL Output Low VOLCNTL IIN = 5.0 A, 5.0 V VBATT 26.5 V CNTL Output High IOUT = 180 A, 5.0 V VBATT 26.5 V V VOHCNTL V VBATT - 0.8 - VBATT Notes 4. After tCNTLFDLY 5. Thermal shutdown causes the BUS output driver to be disabled. Guaranteed by characterization. 33897 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions of -40 C TA 125 C, unless otherwise stated. Voltages are relative to GND, unless otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit LOAD LOAD Voltage Rise (6) VLDRISE V Normal Speed and Voltage Mode, Transmit HighVoltage Mode, Transmit High Speed Mode IIN = 1.0 mA, 5.0 V VBATT 26.5 V - - 0.1 33897T - - 1.0 33897CT - - 0.1 - - 1.0 Sleep Mode IIN = 7.0 mA IIN = 7.0 mA (7) Loss of Battery IIN = 7.0 mA LOAD Leakage During Loss of Module Ground (8) A ILDLEAK 0.0 V VBATT 18 V 33897T 0.0 - - 90 0.0 V VBATT 18 V 33897CT -10 - 10 BUS A Passive Out BUS Leakage Passive In 0.0 V VBATT 26.5 V, -1.5 V VBUS < 0 V Active In 0.0 V VBATT 26.5 V, 0 V < VBUS 12.5 V BUS Leakage During Loss of Module Ground ILEAK -5.0 - 5.0 -5.0 - 5.0 -10 - 10 0.0 - -90 ILKAI (9) 0.0 V VBATT 18 V 33897T 0.0 V VBATT 18 V 33897CT IBLKLOG High Voltage Wake-up Mode Output High Voltage V 12 V VBATT 26.5 V, 200 RL 3332 5.0 V VBATT < 12 V, 200 RL 3332 33897T VHVWUOHF 33897CT VHVWUOHO High Speed Mode Output High Voltage 9.7 - 12.5 9.9 - 12.5 Lesser of VBAT 1.5 or 9.7 - VBATT 4.2 - 5.1 VOHHS 8.0 V VBATT 16 V, 75 RL 135 V Normal Mode Output High Voltage V 6.0 V VBATT 26.5 V, 200 RL 3332 VNOHF 4.4 - 5.1 5.0 V VBATT < 6.0 V, 200 RL 3332 VNOHO Lesser of VBATT 1.6 or 4.4 - Lesser of VBATT or 5.1 Notes 6. GMW3089V2.4 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode. The maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.4. 7. 33897CT removes the diode drop during Sleep mode. 8. LOAD pin is at system ground voltage. 9. BUS pin is at system ground voltage 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions of -40 C TA 125 C, unless otherwise stated. Voltages are relative to GND, unless otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max - 0.2 - 0.2 -350 - - 100 Unit BUS (CONTINUED) BUS Low Voltage VOL 5.0 V VBATT 26.5 V, 200 RL 3332 Short-circuit BUS Output Current V IBSC Dominant State, 5.0 V VBATT 26.5 V mA Input Threshold V Awake 5.0 V VBATT 26.5 V VBIA 2.0 - 2.2 VBISF 6.6 - 7.9 VBISO Lesser of 6.6 V or VBATT - 4.3 - Lesser of 7.9 V or VBATT - 3.25 Sleep 12 V VBATT 26.5 V Sleep 5.0 V VBATT < 12 V 33897 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions of -40 C TA 125 C, unless otherwise stated. Voltages are relative to GND unless otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max 2.0 - 6.3 Unit BUS Normal Speed Rising Output Delay s t DLYNORMRO 200 RL 3332 , 1.0 s Load Time Constants 4.0 s Measured from TXD = VIL to VBUS as follows: Max Time to VBUSMOD = 3.7 V, 6.0 V VBATT 26.5 V (10) Min Time to VBUSMOD = 1.0 V, 6.0 V VBATT 26.5 V (10) Max Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (10) Min Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (10) Normal Speed Falling Output Delay s t DLYNORMFO 200 RL 3332 , 1.0 s Load Time Constants 4.0 s 1.8 - 8.5 0.1 - 1.7 0.04 - 3.0 Measured from TXD = VIH to VBUS as follows: Max Time to VBUSMOD = 1.0 V, 6.0 V VBATT 26.5 V (10) Min Time to VBUSMOD = 3.7 V, 6.0 V VBATT 26.5 V (10) Max Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (10) Min Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (10) High Speed Rising Output Delay s t DLYHSRO 75 RL 135 , 0.0 s Load Time Constants 1.5 s, 8.0 V VBATT 16 V Measured from TXD = VIL to VBUS as follows: Max Time to VBUS = 3.7 V (11) Min Time to VBUS = 1.0 V (11) High Speed Falling Output Delay 75 RL 135 , 0.0 s Load Time Constants 1.5 s, 8.0 V VBATT 16 V s t DLYHSFO Measured from TXD = VIH to VBUS as follows: Max Time to VBUS = 1.0 V (11) Min Time to VBUS = 3.7 V (11) Notes 10. VBUSMOD is the voltage at the BUSMOD node in Figure 6, page 13. 11. VBUS is the voltage at the BUS pin in Figure 7, page 14. 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions of -40 C TA 125 C, unless otherwise stated. Voltages are relative to GND unless otherwise noted. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit BUS (CONTINUED) High Voltage Rising Output Delay s t DLYHVRO 200 RL 3332 , 1.0 s Load Time Constants 4.0 s Measured from TXD=VIL to VBUS as follows: Max Time to VBUSMOD = 3.7 V, 6.0 V VBATT 26.5 V (12) 2.0 - 6.3 Min Time to VBUSMOD = 1.0 V, 6.0 V VBATT 26.5 V (12) 2.0 - 6.3 2.0 - 18 Max Time to VBUSMOD = 9.4 V, 12.0 V VBATT 26.5 V (12) High Voltage Falling Output Delay s t DLYHVFO 200 RL 3332 , 1.0 s Load Time Constants 4.0 s, 12.0 V VBATT 26.5 V Measured from TXD=VIH to VBUS as follows: Max Time to VBUSMOD = 1.0 V (12) Min Time to VBUSMOD = 3.7 V (12) 1.8 - 14 1.8 - 14 0.2 - 1.0 10 - 70 300 - 1000 RECEIVER RXD Receive Delay Time (5.0 V VBATT 26.5 V) Receive Delay Time (BUS Rising to RXD Falling, 5.0 V VBATT 26.5 V) s t RDLY Awake s t RDLYSL Sleep CNTL CNTL Falling Delay Time (5.0 V VBATT 26.5 V) t CNTLFDLY ms Notes 12. VBUSMOD is the voltage at the BUSMOD node in Figure 6, page 13. 33897 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS tDLYNORMFO tDLYNORMRO V IH V IL TXD V NOHF Bus V BIA V BUSMOD * V BIA V BUSMOD * V IH RXD V IL tRDLY tRDLY * VBUSMOD is the voltage at the BUSMOD node in Figure 7. Figure 4. TXD, Bus and RXD Waveforms in Normal Mode TDLYHSRO tDLYHSFO VIH TXD VIL VNOHF VBUS * Bus VBIA VBIA VBUS * VIH RXD VIL tRDLY tRDLY * VBUS is the voltage at the BUS pin in Figure 8. Figure 5. TXD, Bus and RXD Waveforms in High Speed Mode 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33897 Series is intended for use as a physical layer device in a Single Wire CAN communications bus. Communications takes place from a single pin over a single wire using a common ground for a current return path. Two data rates are available, with the high rate used for factory or assembly line communications and the lower for actual system communications where the radiated EMI of the higher rate could be an issue. Two pins control the mode of operation (sleep, low speed, high speed, and high voltage wake-up). FUNCTIONAL PIN DESCRIPTION The 33897 Series is intended to be used with an MCU to control its operation and to process and generate the data for the bus. MCU comes out of reset, before the driving signals have been configured as outputs. RXD DATA GROUND PINS The four ground pins are not only for electrical conduction, their number and locations at each of the four corners serve also to remove heat from the IC. The biggest benefit of this is obtained by putting a lot of copper on the PCB in this area and, if ground is an internal layer, by adding numerous plated-through connections to it with the largest diameter holes the layout can use. TXD DATA The data driven onto the SWCAN bus is inverted from the TXD pin. A "1" driven on TXD will result in an undriven (recessive) state (bus at near zero volts). When the TXD pin is low, the output goes to a driven state. The voltage and waveshaping in the driven state is determined by the levels on the MODE0 and MODE1 Pins (refer to Table 6). Table 6. Mode Control Logic Levels Logic Level Operation MODE0 MODE1 0 0 Sleep mode 0 1 High voltage wake-up mode 1 0 High speed mode 1 1 Normal mode MODE CONTROL The MODE pins control the transmitter filtering and BUS voltage and the IC Sleep mode operation. Table 6 shows the mode versus the logic levels on MODE0 and MODE1. The MODE0 and MODE1 pins have a weak pull-down in the IC so that in case the pins are not driven, the device will enter the Sleep mode. This is usually the situation as the The data received on the bus is translated to logic levels on this pin. This pin is a logic high when the bus is in the recessive state (near zero volts) and is logic low when the bus is in either the normal or high voltage dominant state. This is an open-drain type of output that requires an external resistor to pull it up. When the device is in sleep mode, the output will be off unless a high voltage wake-up level is detected on the bus. If the wake-up level is detected, the output will be driven by the data on the bus. If the level of the data returns to normal level, the output will return to off after a short delay unless a non-sleep mode condition is set by the MCU. LOAD SWITCH This switch is ON in all operating modes unless a loss of ground is detected. If this happens, the switch is opened and the resistor normally attached to its pin will no longer pass current to or from the bus. CNTL OUTPUT This logic level signal is used to control a VCC regulator. When the output is low, the VCC regulator is expected to shutdown. This is normally used to shut down the MCU and all the devices powered by VCC when the IC is in Sleep mode. This is done to save power. When the part is taken out of the Sleep mode by the higher than normal bus voltage, this pin is asserted high and the VCC regulator brings its output up to the regulated level. This starts the MCU, which controls the mode of the IC. The MCU must change the mode signals to nonSleep mode levels in order to keep this pin from going low. There is a delay to allow the MCU to fully wake-up and take control after the high voltage signaling is removed before the level on this output returns low. After a delay time, even if the bus is at high voltage, the IC will return to Sleep mode if both MODE pins are low. 33897 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM COMPONENTS VBATT INPUT BUS I /O This power input is not reverse battery protected and should use an external diode to protect it from damage due to reverse battery if this protection is desired. The voltage drop of the diode must be taken into consideration when the operating range of the system is being determined. This diode is generally used to protect the entire module from reverse battery and should be selected accordingly. This input / output may require electrostatic discharge (ESD) and /or EMI external circuitry. A set of components is shown in the simplified application diagrams on page 15. The value of the capacitor should be adjusted downward in direct proportion to the added capacitance of the ESD or EMI circuits. The series resistance of the inductor should be kept below 3.5 to prevent its voltage drop from significantly degrading system noise margins. FUNCTIONAL BLOCK DIAGRAM COMPONENTS TIMER OSC TXD BUS DRVR This circuit generates a 500 kHz signal to be used for internal logic. It is the reference for some of the required delays. This circuit drives the BUS. It can drive it with the higher voltage wake-up signals when enabled by the Mode Control circuit. It can also provide waveshaping for reduced EMI or not provide it for the higher data rate mode. The actual data is received on TXD at CMOS logic levels, then translated by this circuit to the necessary operating voltages. TIMERS This circuit contains the timing logic used to hold the CNTL active for the required time after the conditions for sleep mode have been met. It is also used to keep the TXD driver active for a period of time after it has generated a passive level on the bus. MODE CONTROL This circuit contains the control logic for the various operating modes and conditions required for the IC. BUS RCVR This circuit translates the levels on the BUS pin to a CMOS level indicating the presence of a logic [0] or a logic [1]. It also determines the presence of a high voltage wake-up (HVWU) signal that is passed to Mode Control and Timers circuits. An analog filter is used to "de-glitch" the high voltage wake-up signal and prevent false exits from the Sleep mode. UNDER-VOLTAGE DETECT This circuit monitors internal operating voltage to assure proper operation of the part. If a low-voltage condition is detected, it sends a signal to disable the BUS RCVR and TXD BUS DRVR circuits. This prevents incorrect data from being put on the bus or sent to the MCU. LOAD SWITCH The LOAD switch provides a path for an external resistor connected to the BUS to be connected to ground. When a loss of ground is detected, this switch is opened to prevent the current that would normally be flowing to the ground from the module from going back through the load resistor and raising the bus level. The circuit is opened when the voltage between GND and VBATT becomes too low as would be the case if module ground were lost. BUS LOADING PARAMETERS VBATT 100 pF 33897 1.0 k 47 H BUSMOD BUS 6.49 k CNOM = 100 pF + (n -1) 220 pF R= 6.49 k (n -1) LOAD GND Note: The letter 'n' represents the number of nodes in the system. Figure 6. Transmitter Delays in Normal and Transmit High Voltage Wake-up Modes 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM COMPONENTS 33897 BUS 6.49 k 130 CNOM = (n) 220 pF R= 6.49 k (n -1) LOAD GND Note: The letter 'n' represents the number of nodes in the system. Figure 7. Transmitter Delays in Transmit High Speed Mode 33897 14 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS bus. This wake-up voltage will activate the CNTL line, which enables the regulator and turns the module back ON. This feature allows the module to be more energy efficient since the current consumption is significantly lowered when it goes into sleep mode. The 33897 can be used in applications where the module includes a regulator that has the capability of going into Sleep mode by having an Enable pin. See Figure 8. When the module's regulator is in Sleep mode, the module is turned off. The module waits for a defined wake-up voltage level on the VCC Voltage Regulator Power Battery Source 100 nF EN 100 pF VBATT 1.0 k CNTL VCC 10 k 2.7 k 47 H BUS TXD SWC BUS 47 pF RXD MCU 4.7 F MODE0 LOAD 6.49 k MODE1 GND 4 33897 Figure 8. 33897 Typical Application Schematic 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 15 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current Package revision, visit www.freescale.com and perform a Keyword Search on the 98ASB42565B drawing number below. Dimensions shown are provided for reference ONLY. EF (Pb-FREE) SUFFIX 14-pin SOICN 98ASB42565B ISSUE J 33897 16 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EF (Pb-FREE) SUFFIX 14-pin SOICN 98ASB42565B ISSUE J 33897 Analog Integrated Circuit Device Data Freescale Semiconductor 17 REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 9.0 5/2005 * * * * Converted to Freescale format Added A & B Versions Updated Device Variation Table, and Note "* Recommended device for all new designs" Added EF (Pb-Free) Devices, and higher soldering temperature 10.0 8/2005 * * * Implemented Revision History page Updated Simplified Application Diagrams Updated Typical Application Schematic 11.0 12/2005 * Added 33897C and D versions and Timing Diagrams 12.0 1/2006 * * Updated Table 4, Static Electrical Characteristics - LOAD and BUS parameters Updated Ordering Information. 13.0 6/2006 * Removed "Unless otherwise noted" from Static Electrical Characteristics & Dynamic Electrical Characteristics table introductions 14.0 8/2006 * * Added Part Numbers MC33897TD and MC33897TEF to Ordering Information on Page 1. Added 33897T to Table 1, Device Variations on Page 3, Referencing Electrical Changes per Errata MC33897TER, Revision 3 and specifying ESD variations 15.0 10/2006 * Removed Part Numbers MC33897TD/R2, MC33897TEF/R2, MC33897CLEF/R2, PC33897CLEF/ R2, MC33897DLEF/R2, and PC33897DLEF/R2 Added Part Numbers MCZ33897EF/R2, MCZ33897TEF/R2, MCZ33897AEF/R2, MCZ33897CEF/ R2, MCZ33897BEF/R2, and MCZ33897DEF/R2 to the Ordering Information block on Page 1. Updated Device Variations on page 2 for "T" suffix products Split out Human Body Model on page 5 to differentiate between T and non-T versions Added Under-voltage Hysteresis on page 6 Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 5. Added note with instructions to obtain this information from www.freescale.com. * * * * * 16.0 6/2007 * Removed watermark, "Advance Information" from page 1. 17.0 1/2011 * * * * Improved HBM ESD All Pins Except BUS to 2.0 kV on MC33897CT Added MC33897CTEKF/R2 to the ordering information Removed all 8-Pin SOICN device information Changed Short-circuit BUS Output Current to -100 mA (Approved by GM) 18.0 4/2012 * Updated Quiescent Current IQSLP to 60 A max. 33897 18 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits on the Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, Qorivva, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, Processor expert, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) 2012 Freescale Semiconductor, Inc. Document Number: MC33897 Rev. 18.0 4/2012