Integrated Silicon Solution, Inc. 1
Rev. C
05/27/2010
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61VPS102436A IS61LPS102436A
IS61VPS204818A IS61LPS204818A
FEATURES
• Internalself-timedwritecycle
• IndividualByteWriteControlandGlobalWrite
• Clockcontrolled,registeredaddress,dataand
control
• BurstsequencecontrolusingMODEinput
• Threechipenableoptionforsimpledepthex-
pansion and address pipelining
• Commondatainputsanddataoutputs
• AutoPower-downduringdeselect
• Singlecycledeselect
• SnoozeMODEforreduced-powerstandby
• PowerSupply
LPS: Vd d 3.3V + 5%, Vd d q 3.3V/2.5V + 5%
VPS: Vd d 2.5V + 5%, Vd d q 2.5V + 5%
• JEDEC100-PinTQFPand165-ballPBGA
packages
• Lead-freeavailable
DESCRIPTION
The ISSI IS61LPS/VPS102436A and IS61LPS/VPS
204818Aarehigh-speed,low-powersynchronousstatic
RAMs
designed to provide burstable,
high-performance
memory for communication and networking applications.
TheIS61LPS/VPS102436Aisorganizedas1,048,476
wordsby36bits.TheIS61LPS/VPS204818A is organized
as2M-wordby18bits.FabricatedwithISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter,high-speedSRAMcore,andhigh-drivecapability
outputs into a single monolithic circuit. All synchronous
inputspassthroughregisterscontrolledbyapositive-
edge-triggeredsingleclockinput.
Writecyclesareinternallyself-timedandareinitiatedby
therisingedgeoftheclockinput.Writecyclescanbe
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
Thebytewriteoperationisperformedbyusingthebyte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). Inaddition,Global
Write(GW) is available for writing all bytes at one time,
regardless of the byte write controls.
BurstscanbeinitiatedwitheitherADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the ADV (burst address
advance) input pin.
Themodepinisusedtoselecttheburstsequenceor-
der,LinearburstisachievedwhenthispinistiedLOW.
InterleaveburstisachievedwhenthispinistiedHIGH
or left floating.
1Mb x 36, 2Mb x 18
36Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
JUNE 2010
FAST ACCESS TIME
Symbol Parameter 200 166 Units
tk q ClockAccessTime 3.1 3.5 ns
tk c CycleTime 5 6 ns
Frequency 200 166 MHz
2 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
BLOCK DIAGRAM
20/21
BINARY
COUNTER
GW
CLR
CE
CLK Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
18/19 20/21
ADDRESS
REGISTER
CE
D
CLK
Q
DQ(a-h)
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW(a-h)
x18: a,b
x36: a-d
CE
CE2
CE2
1Mx36;
2Mx18
MEMORY ARRAY
36,
or 18
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
2/4/8
OE
DQa - DQd
36,
or 18
36,
or 18
A
POWER
DOWN
ZZ
Integrated Silicon Solution, Inc.3
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
BOTTOMVIEW
165-PIN BGA
165-Ball,13x15mmBGA
1mmBallPitch,11x15BallArray
4 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
PIN DESCRIPTIONS
165 PBGA PACKAGE PIN CONFIGURATION
1M x 36 (TOP VIEW)
Note: * A0 and A1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
1 2 3 4 5 6 7 8 9 10 11
ANC A CE BWc BWb CE2 BWE ADSC ADV A NC
BNC A CE2 BWd BWa CLK GW OE ADSP A NC
CDQPc NC Vd d q Vss Vss Vss Vss Vss Vd d q Nc DQPb
DDQc DQc Vd d q Vd d Vss Vss Vss Vd d Vd d q DQb DQb
EDQc DQc Vd d q Vd d Vss Vss Vss Vd d Vd d q DQb DQb
FDQc DQc Vd d q Vd d Vss Vss Vss Vd d Vd d q DQb DQb
GDQc DQc Vd d q Vd d Vss Vss Vss Vd d Vd d q DQb DQb
HNC NC NC Vd d Vss Vss Vss Vd d Nc Nc ZZ
JDQd DQd Vd d q Vd d Vss Vss Vss Vd d Vd d q dqadqa
KDQd DQd Vd d q Vd d Vss Vss Vss Vd d Vd d q dqadqa
LDQd DQd Vd d q Vd d Vss Vss Vss Vd d Vd d q dqadqa
MDQd DQd Vd d q Vd d Vss Vss Vss Vd d Vd d q dqadqa
NDQPd NC Vd d q Vss NC A NC Vss Vd d q NC DQPa
PNC NC A A NC A1* NC A A A A
RMODE A A A NC A0* NC A A A A
Symbol Pin Name
A Address Inputs
A0, A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP Address Status Processor
ADSC Address Status Controller
GW GlobalWriteEnable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx(x=a,b,c,d) SynchronousByteWrite
Controls
Symbol Pin Name
BWE ByteWriteEnable
OE OutputEnable
ZZ PowerSleepMode
MODE BurstSequenceSelection
NC No Connect
DQx DataInputs/Outputs
DQPx DataInputs/Outputs
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputPowerSupply
3.3V/2.5V
Vss Ground
Integrated Silicon Solution, Inc. 5
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
Note: * A0 and A1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
165 PBGA PACKAGE PIN CONFIGURATION
2M x 18 (TOP VIEW)
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP Address Status Processor
ADSC Address Status Controller
GW GlobalWriteEnable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx(x=a,b) SynchronousByteWrite
Controls
Symbol Pin Name
BWE ByteWriteEnable
OE OutputEnable
ZZ PowerSleepMode
MODE BurstSequenceSelection
NC No Connect
DQx DataInputs/Outputs
DQPx DataInputs/Outputs
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputPowerSupply
3.3V/2.5V
Vss Ground
1 2 3 4 5 6 7 8 9 10 11
ANC A CE BWb NC CE2 BWE ADSC ADV A A
BNC A CE2 NC BWa CLK GW OE ADSP A NC
CNC NC Vd d q Vss Vss Vss Vss Vss Vd d q Nc DQPa
DNC DQb Vd d q Vd d Vss Vss Vss Vd d Vd d q NC DQa
ENC DQb Vd d q Vd d Vss Vss Vss Vd d Vd d q NC DQa
FNC DQb Vd d q Vd d Vss Vss Vss Vd d Vd d q NC DQa
GNC DQb Vd d q Vd d Vss Vss Vss Vd d Vd d q NC DQa
HNC NC NC Vd d Vss Vss Vss Vd d Nc Nc ZZ
JDQb NC Vd d q Vd d Vss Vss Vss Vd d Vd d q dqaNc
KDQb NC Vd d q Vd d Vss Vss Vss Vd d Vd d q dqaNc
LDQb NC Vd d q Vd d Vss Vss Vss Vd d Vd d q dqaNc
MDQb NC Vd d q Vd d Vss Vss Vss Vd d Vd d q dqaNc
NDQPb NC Vd d q Vss NC A NC Vss Vd d q NC NC
PNC NC A A NC A1* NC A A A A
RMODE A A A NC A0* NC A A A A
6 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
A
VSS
VDD
A
A
A
A
A
A
A
A
A
46 47 48 49 50
PIN DESCRIPTIONS
A0, A1 SynchronousAddressInputs.These
pinsmusttiedtothetwoLSBsofthe
address bus.
A Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
SynchronousBurstAddressAdvance
BWa-BWd SynchronousByteWriteEnable
BWE SynchronousByteWriteEnable
CE, CE2, CE2 SynchronousChipEnable
CLK Synchronous Clock
DQa-DQd SynchronousDataInput/Output
DQPa-DQPd ParityDataInput/Output
GW SynchronousGlobalWriteEnable
MODE BurstSequenceModeSelection
OE OutputEnable
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputBufferSupply:
3.3V/2.5V
Vss Ground
ZZ SnoozeEnable
PIN CONFIGURATION
1M x 36
100-PIN TQFP
Integrated Silicon Solution, Inc. 7
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
PIN CONFIGURATION
2M x 18
PIN DESCRIPTIONS
A0,A1 SynchronousAddressInputs.These
pinsmusttiedtothetwoLSBsofthe
address bus.
A Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
SynchronousBurstAddressAdvance
BWa-BWb SynchronousByteWriteEnable
BWE SynchronousByteWriteEnable
CE,CE2,CE2 SynchronousChipEnable
CLK Synchronous Clock
DQa-DQb SynchronousDataInput/Output
DQPa-DQPb ParityDataI/O;DQPaisparityfor
DQa1-8;DQPbisparityforDQb1-8
GW SynchronousGlobalWriteEnable
MODE BurstSequenceModeSelection
OE OutputEnable
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputBufferSupply:
3.3V/2.5V
Vss Ground
ZZ SnoozeEnable
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
A
VSS
VDD
A
A
A
A
A
A
A
A
A
46 47 48 49 50
100-PIN TQFP
8 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
TRUTH TABLE(1-8) (3CEoption)
OPERATION ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ
DeselectCycle,Power-Down None H X X L X L X X X L-H High-Z
DeselectCycle,Power-Down None L X L L L X X X X L-H High-Z
DeselectCycle,Power-Down None L H X L L X X X X L-H High-Z
DeselectCycle,Power-Down None L X L L H L X X X L-H High-Z
DeselectCycle,Power-Down None L H X L H L X X X L-H High-Z
SnoozeMode,Power-Down None X X X H X X X X X X High-Z
ReadCycle,BeginBurst External L L H L L X X X L L-H Q
ReadCycle,BeginBurst External L L H L L X X X H L-H High-Z
WriteCycle,BeginBurst External L L H L H L X L X L-H D
ReadCycle,BeginBurst External L L H L H L X H L L-H Q
ReadCycle,BeginBurst External L L H L H L X H H L-H High-Z
ReadCycle,ContinueBurst Next X X X L H H L H L L-H Q
ReadCycle,ContinueBurst Next X X X L H H L H H L-H High-Z
ReadCycle,ContinueBurst Next H X X L X H L H L L-H Q
ReadCycle,ContinueBurst Next H X X L X H L H H L-H High-Z
WriteCycle,ContinueBurst Next X X X L H H L L X L-H D
WriteCycle,ContinueBurst Next H X X L X H L L X L-H D
ReadCycle,SuspendBurst Current X X X L H H H H L L-H Q
ReadCycle,SuspendBurst Current X X X L H H H H H L-H High-Z
ReadCycle,SuspendBurst Current H X X L X H H H L L-H Q
ReadCycle,SuspendBurst Current H X X L X H H H H L-H High-Z
WriteCycle,SuspendBurst Current X X X L H H H L X L-H D
WriteCycle,SuspendBurst Current H X X L X H H L X L-H D
NOTE:
1. Xmeans“Don’tCare.”HmeanslogicHIGH.LmeanslogicLOW.
2. ForWRITE, L means one or more byte write enable signals (BWa-h) and BWEareLOWorGWisLOW.WRITE = H for all
BWx, BWE, GWHIGH.
3. BWaenablesWRITEstoDQa’sandDQPa.BWbenablesWRITEstoDQb’sandDQPb.BWcenablesWRITEstoDQc’s and
DQPc.BWdenablesWRITEstoDQd’sandDQPd.DQPa-DQPdareavailableonthex36version.
4. AllinputsexceptOEandZZmustmeetsetupandholdtimesaroundtherisingedge(LOWtoHIGH)ofCLK.
5. Waitstatesareinsertedbysuspendingburst.
6. ForaWRITEoperationfollowingaREADoperation,OEmustbeHIGHbeforetheinputdatasetuptimeandheldHIGHduring
the input data hold time.
7. ThisdevicecontainscircuitrythatwillensuretheoutputswillbeinHigh-Zduringpower-up.
8. ADSPLOWalwaysinitiatesaninternalREADattheL-HedgeofCLK.AWRITEisperformedbysettingoneormorebytewrite
enable signals and BWELOWorGWLOWforthesubsequentL-HedgeofCLK.SeeWRITEtimingdiagramforclarication.
Integrated Silicon Solution, Inc. 9
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
PARTIAL TRUTH TABLE
Function GW BWE BWa BWb BWc BWd
Read H H X X X X
Read H L H H H H
WriteByte1 H L L H H H
WriteAllBytes H L L L L L
WriteAllBytes L X X X X X
TRUTH TABLE(1-8) (1CEoption)
NEXT CYCLE ADDRESS CE ADSP ADSC ADV
WRITE
OE DQ
Deselected None H X L X X X High-Z
Read,BeginBurst External L L X X X L Q
Read,BeginBurst External L L X X X H High-Z
Write,BeginBurst External L H L X L X D
Read,BeginBurst External L H L X H L Q
Read,BeginBurst External L H L X H H High-Z
Read,ContinueBurst Next X H H L H L Q
Read,ContinueBurst Next X H H L H H High-Z
Read,ContinueBurst Next H X H L H L Q
Read,ContinueBurst Next H X H L H H High-Z
Write,ContinueBurst Next X H H L L X D
Write,ContinueBurst Next H X H L L X D
Read,SuspendBurst Current X H H H H L Q
Read,SuspendBurst Current X H H H H H High-Z
Read,SuspendBurst Current H X H H H L Q
Read,SuspendBurst Current H X H H H H High-Z
Write,SuspendBurst Current X H H H L X D
Write,SuspendBurst Current H X H H L X D
NOTE:
1. Xmeans“Don’tCare.”HmeanslogicHIGH.LmeanslogicLOW.
2. ForWRITE, L means one or more byte write enable signals (BWa-h) and BWEareLOWorGWisLOW.WRITE = H for all
BWx, BWE, GWHIGH.
3. BWaenablesWRITEstoDQa’sandDQPa.BWbenablesWRITEstoDQb’sandDQPb.BWcenablesWRITEstoDQc’s and
DQPc.BWdenablesWRITEstoDQd’sandDQPd.DQPa-DQPdareavailableonthex36version.
4. AllinputsexceptOEandZZmustmeetsetupandholdtimesaroundtherisingedge(LOWtoHIGH)ofCLK.
5. Waitstatesareinsertedbysuspendingburst.
6. ForaWRITEoperationfollowingaREADoperation,OEmustbeHIGHbeforetheinputdatasetuptimeandheldHIGHduring
the input data hold time.
7. ThisdevicecontainscircuitrythatwillensuretheoutputswillbeinHigh-Zduringpower-up.
8. ADSPLOWalwaysinitiatesaninternalREADattheL-HedgeofCLK.AWRITEisperformedbysettingoneormorebytewrite
enable signals and BWELOWorGWLOWforthesubsequentL-HedgeofCLK.SeeWRITEtimingdiagramforclarication.
10 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
INTERLEAVED BURST ADDRESS TABLE (MODE = VD D or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
1,0
0,1A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Ts T g StorageTemperature –55to+150 °C
Pd PowerDissipation 1.6 W
IO u T OutputCurrent(perI/O) 100 mA
VI N , VO u T VoltageRelativetoVssforI/OPins –0.5toVd d q + 0.5 V
VI N VoltageRelativetoVssfor –0.5toVd d + 0.5 V
for Address and Control Inputs
Vd d Voltage on Vd d SupplyRelativetoVss –0.5to4.6 V
Notes:
1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycauseperma-
nentdamagetothedevice.Thisisastressratingonlyandfunctionaloperationofthedevice
at these or any other conditions above those indicated in the operational sections of this
specicationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2.Thisdevicecontainscircuitytoprotecttheinputsagainstdamageduetohighstaticvoltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higherthanmaximumratedvoltagestothishigh-impedancecircuit.
3.ThisdevicecontainscircuitrythatwillensuretheoutputdevicesareinHigh-Zatpowerup.
Integrated Silicon Solution, Inc. 11
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
OPERATING RANGE (IS61LPSXXXXX)
Range Ambient Temperature VD D VD D q
Commercial 0°Cto+70°C 3.3V+ 5% 3.3V/2.5V+ 5%
Industrial –40°Cto+85°C 3.3V+ 5% 3.3V/2.5V+ 5%
OPERATING RANGE (IS61VPSXXXXX)
Range Ambient Temperature VD D VD D q
Commercial 0°Cto+70°C 2.5V+ 5% 2.5V + 5%
Industrial –40°Cto+85°C 2.5V+ 5% 2.5V + 5%
DC ELECTRICAL CHARACTERISTICS (OverOperatingRange)
3.3V 2.5V
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
VO h OutputHIGHVoltage IO h = –4.0mA(3.3V) 2.4 — 2.0 — V
IO h = –1.0mA(2.5V)
VO l OutputLOWVoltage IO l = 8.0mA(3.3V) — 0.4 — 0.4 V
IO l = 1.0 mA (2.5V)
VI h InputHIGHVoltage 2.0 Vd d +0.3 1.7 Vd d + 0.3 V
VI l InputLOWVoltage -0.3 0.8 -0.3 0.7 V
Il I Input Leakage Current Vss ≤ VI N ≤ Vd d (1) -5 5 -5 5 µA
Il O OutputLeakageCurrent Vss ≤ VO u T ≤ Vd d q , -5 5 -5 5 µA
OE = VI h
POWER SUPPLY CHARACTERISTICS(1) (OverOperatingRange)
-200 -166
MAX MAX
Symbol Parameter Test Conditions
Temp. range x18 x36 x18 x36 Uni
t
Ic c ACOperating DeviceSelected, Com. 450 450 400 400 mA
Supply Current OE = VI h , ZZ ≤ VI l , Ind. 475 475 450 450
All Inputs ≤ 0.2V or ≥ Vd d – 0.2V, typ.(2) 390 340
CycleTime≥ tk c min.
Is b StandbyCurrent DeviceDeselected, Com. 150 150 140 140 mA
TTLInput Vd d = Max., Ind. 160 160 150 150
All Inputs ≤ VI l or ≥ VI h ,
ZZ ≤ VI l , f=Max.
Is b I StandbyCurrent DeviceDeselected, Com. 110 110 110 110 mA
cMOs Input Vd d = Max., Ind. 140 140 140 140
VI N
≤
Vs s +0.2Vor≥Vd d – 0.2V typ.(2) 75 75
f = 0
Note:
1. MODEpinhasaninternalpullupandshouldbetiedtoVd d or Vs s .Itexhibits±100µAmaximumleakagecurrentwhentiedto≤
Vs s +0.2Vor≥ Vd d –0.2V.
2.TypicalvaluesaremeasuredatVcc=3.3V,T
A = 25oC and not 100% tested.
12 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
cI N Input Capacitance VI N = 0V 6 pF
cO u T Input/OutputCapacitance VO u T = 0V 8 pF
Notes:
1.Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.
2. Testconditions:T
A = 25°c, f=1MHz,Vd d =3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Unit
InputPulseLevel 0Vto3.0V
InputRiseandFallTimes 1.5ns
InputandOutputTiming 1.5V
and Reference Level
OutputLoad SeeFigures1and2
AC TEST LOADS
Figure 2
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Figure 1
Output
Z
O
= 50Ω
1.5V
50Ω
Integrated Silicon Solution, Inc. 13
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
2.5V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 2.5V
InputRiseandFallTimes 1.5ns
InputandOutputTiming 1.25V
and Reference Level
OutputLoad SeeFigures3and4
2.5 I/O OUTPUT LOAD EQUIVALENT
Figure 4
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
2.5V
Figure 3
Output
Z
O
= 50Ω
1.25V
50Ω
14 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (OverOperatingRange)
-200 -166
Symbol Parameter Min. Max. Min. Max. Unit
fM A x ClockFrequency — 200 — 166 MHz
tk c CycleTime 5 — 6 — ns
tk h ClockHighTime 2 — 2.4 — ns
tk l ClockLowTime 2 — 2.4 — ns
tk q ClockAccessTime — 3.1 — 3.5 ns
tk q x (2) ClockHightoOutputInvalid 1.5 — 1.5 — ns
tk q l Z (2,3) ClockHightoOutputLow-Z 1 — 1 — ns
tk q h Z (2,3) ClockHightoOutputHigh-Z — 3.0 — 3.4 ns
tO E q OutputEnabletoOutputValid — 3.1 — 3.5 ns
tO E q x (2) OutputDisabletoOutputInvalid 0 — 0 — ns
tO E l Z (2,3) OutputEnabletoOutputLow-Z 0 — 0 — ns
tO E h Z (2,3) OutputDisabletoOutputHigh-Z — 3.0 — 3.4 ns
tA s AddressSetupTime 1.4 — 1.5 — ns
ts s AddressStatusSetupTime 1.4 — 1.5 — ns
tW s Read/WriteSetupTime 1.4 — 1.5 — ns
tc E s ChipEnableSetupTime 1.4 — 1.5 — ns
tA V s AddressAdvanceSetupTime 1.4 — 1.5 — ns
td s DataSetupTime 1.4 — 1.5 — ns
tA h AddressHoldTime 0.4 — 0.5 — ns
ts h AddressStatusHoldTime 0.4 — 0.3 — ns
tW h WriteHoldTime 0.4 — 0.5 — ns
tc E h ChipEnableHoldTime 0.4 — 0.5 — ns
tA V h AddressAdvanceHoldTime 0.4 — 0.5 — ns
td h DataHoldTime 0.4 — 0.5 — ns
tP d s ZZHightoPowerDown — 2 — 2 cyc
tP u s ZZLowtoPowerDown — 2 — 2 cyc
Note:
1.CongurationsignalMODEisstaticandmustnotchangeduringnormaloperation.
2.Guaranteedbutnot100%tested.Thisparameterisperiodicallysampled.
3. TestedwithloadinFigure2.
Integrated Silicon Solution, Inc. 15
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
READ/WRITE CYCLE TIMING
Single Read
High-Z
High-Z
DATAOUT
DATAIN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
RD1 RD2
1a 2c 2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQHZ
ADSC initiate read
ADSP is blocked by CE inactive
t
AVH
t
AVS
Suspend Burst
Pipelined Read
2a 2b
16 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
WRITE CYCLE TIMING
Single Write
DATAOUT
DATAIN
OE
CE2
CE2
CE
BWx
BWE
GW
Address
ADV
ADSC
ADSP
CLK
WR1WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z 1a 3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2a 2b
Integrated Silicon Solution, Inc. 17
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
SNOOZE MODE TIMING
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Temperature Conditions Min. Max. Unit
Is b 2 CurrentduringSNOOZEMODE Com. ZZ≥Vih — 60 mA
Ind. — 90
tP d s ZZactivetoinputignored — 2 cycle
tP u s ZZinactivetoinputsampled 2 — cycle
tZ Z I ZZactivetoSNOOZEcurrent — 2 cycle
tr Z Z I ZZinactivetoexitSNOOZEcurrent 0 — ns
18 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O)
Commercial Range: 0°C to +70°C
Configuration Frequency Order Part Number Package
1Mx36
166 IS61LPS102436A-166TQ 100TQFP
IS61LPS102436A-166TQL 100TQFP,Lead-free
IS61LPS102436A-166B3 165PBGA
2Mx18
166 IS61LPS204818A-166TQ 100TQFP
IS61LPS204818A-166TQL 100TQFP,Lead-free
IS61LPS204818A-166B3 165PBGA
Industrial Range: -40°C to +85°C
Configuration Frequency Order Part Number Package
1Mx36
166 IS61LPS102436A-166TQI 100TQFP
IS61LPS102436A-166TQLI 100TQFP,Lead-free
IS61LPS102436A-166B3I 165PBGA
IS61LPS102436A-166B3LI 165PBGA,Lead-free
2Mx18
166 IS61LPS204818A-166TQI 100TQFP
IS61LPS204818A-166B3I 165PBGA
Integrated Silicon Solution, Inc. 19
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
ORDERING INFORMATION (2.5V core/2.5V I/O)
Commercial Range: 0°C to +70°C
Configuration Frequency Order Part Number Package
1Mx36
166 IS61VPS102436A-166TQ 100TQFP
IS61VPS102436A-166TQL 100TQFP,Lead-free
IS61VPS102436A-166B3 165PBGA
2Mx18
166 IS61VPS204818A-166TQ 100TQFP
IS61VPS204818A-166TQL 100TQFP,Lead-free
IS61VPS204818A-166B3 165PBGA
Industrial Range: -40°C to +85°C
Configuration Frequency Order Part Number Package
2Mx18
166 IS61VPS204818A-166TQI 100TQFP
IS61VPS204818A-166B3I 165PBGA
20 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
Integrated Silicon Solution, Inc. 21
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
1. CONTROLLING DIMENSION : MM .
NOTE :
Package Outline 08/28/2008