Integrated Silicon Solution, Inc. 1
Rev. C
05/27/2010
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61VPS102436A IS61LPS102436A
IS61VPS204818A IS61LPS204818A
FEATURES
• Internalself-timedwritecycle
• IndividualByteWriteControlandGlobalWrite
• Clockcontrolled,registeredaddress,dataand
control
• BurstsequencecontrolusingMODEinput
• Threechipenableoptionforsimpledepthex-
pansion and address pipelining
• Commondatainputsanddataoutputs
• AutoPower-downduringdeselect
• Singlecycledeselect
• SnoozeMODEforreduced-powerstandby
• PowerSupply
LPS: Vd d 3.3V + 5%, Vd d q 3.3V/2.5V + 5%
VPS: Vd d 2.5V + 5%, Vd d q 2.5V + 5%
• JEDEC100-PinTQFPand165-ballPBGA
packages
• Lead-freeavailable
DESCRIPTION
The ISSI IS61LPS/VPS102436A and IS61LPS/VPS
204818Aarehigh-speed,low-powersynchronousstatic
RAMs
designed to provide burstable,
high-performance
memory for communication and networking applications.
TheIS61LPS/VPS102436Aisorganizedas1,048,476
wordsby36bits.TheIS61LPS/VPS204818A is organized
as2M-wordby18bits.FabricatedwithISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter,high-speedSRAMcore,andhigh-drivecapability
outputs into a single monolithic circuit. All synchronous
inputspassthroughregisterscontrolledbyapositive-
edge-triggeredsingleclockinput.
Writecyclesareinternallyself-timedandareinitiatedby
therisingedgeoftheclockinput.Writecyclescanbe
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
Thebytewriteoperationisperformedbyusingthebyte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). Inaddition,Global
Write(GW) is available for writing all bytes at one time,
regardless of the byte write controls.
BurstscanbeinitiatedwitheitherADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the ADV (burst address
advance) input pin.
Themodepinisusedtoselecttheburstsequenceor-
der,LinearburstisachievedwhenthispinistiedLOW.
InterleaveburstisachievedwhenthispinistiedHIGH
or left floating.
1Mb x 36, 2Mb x 18
36Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
JUNE 2010
FAST ACCESS TIME
Symbol Parameter 200 166 Units
tk q ClockAccessTime 3.1 3.5 ns
tk c CycleTime 5 6 ns
Frequency 200 166 MHz