IDT49FCT806APYG8 - Integrated Device Technology

IDT49FCT806/A

FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE

MAY 2010

2006 Integrated Device Technology, Inc. DSC-5837/3c

IDT49FCT806/A

COMMERCIAL TEMPERATURE RANGE

FAST CMOS

BUFFER/CLOCK DRIVER

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

• 0.5 MICRON CMOS Technology

• Guaranteed low skew < 700ps (max.)

• Low duty cycle distortion < 1ns (max.)

• Low CMOS power levels

• TTL compatible inputs and outputs

• Rail-to-rail output voltage swing

• High drive: -24mA IOH, +64mA IOL

• Two independent output banks with 3-state control

• 1:5 fanout per bank

• "Heartbeat" monitor output

• Available in SSOP and SOIC packages

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

DESCRIPTION:

The FCT806 is an inverting buffer/clock driver built using advanced dual

metal CMOS technology. Each bank consists of two banks of drivers. Each

bank drives five output buffers from a standard TTL compatible input. These

devices feature a “heart-beat” monitor for diagnostics and PLL driving. The

MON output is identical to all other outputs and complies with the output

specifications in this document.

The FCT806 offers low capacitance inputs and hysteresis. Rail-to-rail

output swing improves noise margin and allows easy interface with CMOS

inputs.

INA

INB

OEB

OEA

OA1-OA5

OB1-OB5

MON

COMMERCIAL TEMPERATURE RANGE

IDT49FCT806/A

FAST CMOS BUFFER/CLOCK DRIVER

VCCA

OA1

OA2

GNDA

(1)

INA

10 11

201

OA3

OA4

OA5

OEA

VCC

OB1

GNDB

MON

INB

OB2

OB3

OB4

OB5

OEB

NOTE:

1. Pin 8 is not internally connected on devices with a "K" prefix in the date code. On older

devices, pin 8 is internally connected to GND. To insure compatibility with all products,

pin 8 should be connected to GND at the board level.

PIN DESCRIPTION

Pin Names Description

OEA, OEB3-State Output Enable Inputs (Active LOW)

INA, INBClock Inputs

OAn, OBn Clock Outputs

MON Monitor Output

FUNCTION TABLE (1)

Inputs Outputs

OEA, OEBINA, INBOAn, OBnMON

LLHH

LHLL

HLZH

HHZL

NOTE:

1. H = HIGH

L = LOW

Z = High-Impedance

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Description Max Unit

VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V

VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V

TSTG Storage Temperature –65 to +150 °C

IOUT DC Output Current –60 to +120 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Input and VCC terminals.

3. Output and I/O terminals.

CAPACITANCE (TA = +25OC, f = 1.0MHz)

Symbol Parameter(1) Conditions Typ. Max. Unit

CIN Input Capacitance VIN = 0V 4.5 6 pF

COUT Output Capacitance VOUT = 0V 5.5 8 pF

NOTE:

1. This parameter is measured at characterization but not tested.

PIN CONFIGURATION

SOIC/ SSOP

TOP VIEW

IDT49FCT806/A

FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V

Commercial: TA = 0°C to +70°C, VCC = 5V ± 5%

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V

VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

IIH Input HIGH Current VCC = Max. VI = VCC ——±1µA

IIL Input LOW Current VCC = Max. VI = GND — — ±1µA

IOZH Off State (Hi-Z) Output Current VCC = Max. VO = VCC ——±1µA

IOZL VO = GND — — ±1

VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V

IOS Short Circuit Current VCC = Max., VO = GND(3) –60 –120 — mA

VCC = 3V, VIN = VLC or VHC IOH = –32µAVHC VCC —

VOH Output HIGH Voltage VCC = Min. IOH = –300µAVHC VCC —V

VIN = VIH or VIL IOH = –15mA 3 . 6 4 . 3 —

IOH = –24mA 2. 4 3 . 8 —

VCC = 3V, VIN = VLC or VHC IOL = 300µA — GND VLC

VOL Output LOW Voltage VCC = Min. I OL = 300mA — GND VLC V

VIN = VIH or VIL IOL = 64mA — 0.3 0.55

VHInput Hysteresis for all inputs — — 200 — mV

ICC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

COMMERCIAL TEMPERATURE RANGE

IDT49FCT806/A

FAST CMOS BUFFER/CLOCK DRIVER

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 5V, +25°C ambient.

3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fONO)

ICC = Quiescent Current (ICCL, ICCH and ICCZ)

∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

fO = Output Frequency

NO = Number of Outputs at fO

All currents are in milliamps and all frequencies are in megahertz.

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

∆ICC Quiescent Power Supply Current VCC = Max. — 1 2.5 mA

TTL Inputs HIGH VIN = 3.4V(3)

ICCD Dynamic Power Supply Current(4) VCC = Max. VIN = VCC — 0.15 0.2 mA/MHz

Outputs Open VIN = GND

OEA = OEB = GND

50% Duty Cycle

ICTotal Power Supply Current(6) VCC = Max. VIN = VCC — 1.5 2.5

Outputs Open VIN = GND

fO = 10MHz

50% Duty Cycle VIN = 3.4V — 2 3.8

OEA = OEB = VCC VIN = GND

Mon. Output Toggling

VCC = Max. VIN = VCC — 4.1 6(5) mA

Outputs Open VIN = GND

fO = 2.5MHz

50% Duty Cycle VIN = 3.4V — 5.1 8.5(5)

OEA = OEB = GND VIN = GND

Eleven Outputs Toggling

IDT49FCT806/A

FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE

NOTES:

1. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.

2. See test circuits and waveforms.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1)

FCT806 FCT806A

Symbol Parameter Conditions(2) Min.Max.Min.Max.Unit

tPLH Propagation Delay CL = 50pF 1.5 5.6 1.5 5.3 ns

tPHL INA to OAn, INB to OBnRL = 500Ω

tROutput Rise Time — 1.5 — 1.5 ns

tFOutput Fall Time — 1.5 — 1.5 ns

tSK(O) Output skew: skew between outputs of all banks of — 0.7 — 0.7 ns

same package (inputs tied together)

tSK(P) Pulse skew: skew between opposite transitions — 1 — 1 ns

of same output (|tPHL -– tPLH|)

tSK(PP) Part-to-part skew: skew between outputs of different — 1.5 — 1.5 ns

packages at same power supply voltage,

temperature, package type and speed grade

tPZL Output Enable Time 1.5 8 1.5 8 ns

tPZH OEA to OAn, OEB to OBn

tPLZ Output Disable Time 1.5 7 1.5 7 ns

tPHZ OEA to OAn, OEB to OBn

COMMERCIAL TEMPERATURE RANGE

IDT49FCT806/A

FAST CMOS BUFFER/CLOCK DRIVER

VCC

Pulse

Generator D.U.T.

500

VIN VOUT

50pF

VOH

tPLH tPHL

VOL

1.5V

2.0V

0.8V

1.5V

OUTPUT

INPUT

CONTROL

INPUT

tPLZ 0V

OUTPUT

NORMALLY

LOW

tPZH

SWITCH

CLOSED

OUTPUT

NORMALLY

HIGH

ENABLE DISABLE

SWITCH

OPEN

tPHZ

VOL

VOH

0.3V

1.5V

tPZL

3.5V 3.5V

1.5V

VOH

tPLH tPHL

VOL

1.5V

OUTPUT

INPU T

tSK(p) = tPHL - tPLH

VOH

tPLH1

VOL

1.5V

OUTPUT 1

1.5V

INPUT

VOH

tSK(o)

VOL

1.5V

tSK(o) = tPLH2 - tPLH1 or tPHL2 - tPHL1

OUTPUT 2

tPLH1

tSK(o)

tPLH2 tPHL2

VOH

tPLH1

VOL

1.5VPACKAGE 1

OUTPUT

1.5V

INPU T

VOH

tSK(pp)

VOL

1.5V

tSK(pp) = tPLH2 - tPLH1 or tPHL2 - tPHL1

tPHL1

tSK(pp)

tPLH2 tPHL2

PACKAGE 2

OUTPUT

Package Delay

TEST CIRCUITS AND WAVEFORMS

Pulse Skew - tSK(P)

Test Circuits for All Outputs

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Test Switch

Disable LOW Closed

Enable LOW

Disable HIGH G ND

Enable HIGH

SWITCH POSITION

Enable and Disable Times

Output Skew

Part-to-Part Skew - tSK(PP)

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

NOTE:

1. Package 1 and Package 2 are same device type and speed grade.

IDT49FCT806/A

FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE

IDT49FCT X

Package

PYG

Small Outline IC

Shrink Small Outline Package

SSOP - Green

806

806A

Fast CMOS Buffer/Clock Driver

XXXX

Device Type

ORDERING INFORMATION

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com

San Jose, CA 95138 fax: 408-284-2775