0 Spartan-II 2.5V FPGA Family: Pinout Tables R DS001-4 (v2.4) April 30, 2001 0 0 Preliminary Product Specification Pin Definitions Pin Name Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 No Input Clock input pins that connect to Global Clock Buffers. These pins become user inputs when not needed for clocks. M0, M1, M2 Yes Input Mode pins are used to specify the configuration mode. CCLK Yes Input or Output The configuration Clock I/O pin. It is an input for slave-parallel and slave-serial modes, and output in master-serial mode. PROGRAM Yes Input Initiates a configuration sequence when asserted Low. DONE Yes Bidirectional Indicates that configuration loading is complete, and that the start-up sequence is in progress. The output may be open drain. INIT No Bidirectional (Open-drain) When Low, indicates that the configuration memory is being cleared. This pin becomes a user I/O after configuration. BUSY/DOUT No Output In Slave Parallel mode, BUSY controls the rate at which configuration data is loaded. This pin becomes a user I/O after configuration unless the Slave Parallel port is retained. In serial modes, DOUT provides configuration data to downstream devices in a daisy-chain. This pin becomes a user I/O after configuration. D0/DIN, D1, D2, D3, D4, D5, D6, D7 No Input or Output In Slave Parallel mode, D0-D7 are configuration data input pins. During readback, D0-D7 are output pins. These pins become user I/Os after configuration unless the Slave Parallel port is retained. In serial modes, DIN is the single data input. This pin becomes a user I/O after configuration. WRITE No Input In Slave Parallel mode, the active-low Write Enable signal. This pin becomes a user I/O after configuration unless the Slave Parallel port is retained. CS No Input In Slave Parallel mode, the active-low Chip Select signal. This pin becomes a user I/O after configuration unless the Slave Parallel port is retained. TDI, TDO, TMS, TCK Yes Mixed Boundary Scan Test Access Port pins (IEEE 1149.1). VCCINT Yes Input Power supply pins for the internal core logic. VCCO Yes Input Power supply pins for output drivers (subject to banking rules) VREF No Input Input threshold voltage pins. Become user I/Os when an external threshold voltage is not needed (subject to banking rules). GND Yes Input Ground. IRDY, TRDY No See PCI core documentation These signals can only be accessed when using Xilinx PCI cores. If the cores are not used, these pins are available as user I/Os. (c) 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 1 R Spartan-II 2.5V FPGA Family: Pinout Tables Pinout Tables The following device-specific pinout tables include all packages available for each Spartan-II device. They follow the pad locations around the die, and include Boundary Scan register locations. XC2S15 Device Pinouts (Continued) XC2S15 Device Pinouts XC2S15 Pad Name VQ100 TQ144 CS144 Bndry Scan I/O, VREF 5 P30 P102 L4 158 - I/O 5 P31 P100 N4 161 C2 77 I/O 5 P32 P99 K5 164 P140 C1 80 GND - - P98 L5 - P139 D4 83 VCCINT - P33 P97 M5 - 5 - P96 N5 167 VQ100 TQ144 CS144 GND - P1 P143 A1 - TMS - P2 P142 B1 I/O 7 P3 P141 I/O 7 - I/O, VREF 7 P4 Function XC2S15 Pad Name Bank Bank Bndry Scan Function I/O 7 P5 P137 D2 86 I/O I/O 7 P6 P136 D1 89 I/O 5 - P95 K6 170 GND - - P135 E4 - I/O, VREF 5 P34 P94 L6 173 I/O 7 P7 P134 E3 92 I/O 5 - P93 M6 176 I/O 7 - P133 E2 95 VCCINT - P35 P92 N6 - 5 P36 P91 M7 185 I/O, VREF 7 P8 P132 E1 98 I, GCK1 I/O 7 P9 P131 F4 101 VCCO 5 P37 P90 N7 - I/O 7 - P130 F3 104 VCCO 4 P37 P90 N7 - I/O, IRDY(1) 7 P10 P129 F2 107 GND - P38 P89 L7 - GND - P11 P128 F1 - I, GCK0 4 P39 P88 K7 186 4 P40 P87 N8 190 VCCO 7 P12 P127 G2 - I/O VCCO 6 P12 P127 G2 - I/O 4 - P86 M8 193 I/O, TRDY(1) 6 P13 P126 G1 110 I/O, VREF 4 P41 P85 L8 196 VCCINT - P14 P125 G3 - I/O 4 - P84 K8 199 I/O 6 - P124 G4 113 I/O 4 - P83 N9 202 - P42 P82 M9 - I/O 6 P15 P123 H1 116 VCCINT I/O, VREF 6 P16 P122 H2 119 GND - - P81 L9 - I/O 6 - P121 H3 122 I/O 4 P43 P80 K9 205 I/O 6 P17 P120 H4 125 I/O 4 P44 P79 N10 208 GND - - P119 J1 - I/O, VREF 4 P45 P77 L10 211 4 - P76 N11 214 I/O 6 P18 P118 J2 128 I/O I/O 6 P19 P117 J3 131 I/O 4 P46 P75 M11 217 I/O, VREF 6 P20 P115 K1 134 I/O 4 P47 P74 L11 220 I/O 6 - P114 K2 137 GND - P48 P73 N12 - I/O 6 P21 P113 K3 140 DONE 3 P49 P72 M12 223 4 P50 P71 N13 - I/O 6 P22 P112 L1 143 VCCO M1 - P23 P111 L2 146 VCCO 3 P50 P70 M13 - GND - P24 P110 L3 - PROGRAM - P51 P69 L12 226 M0 - P25 P109 M1 147 I/O (INIT) 3 P52 P68 L13 227 VCCO 6 P26 P108 M2 - I/O (D7) 3 P53 P67 K10 230 I/O 3 - P66 K11 233 VCCO 5 P26 P107 N1 - M2 - P27 P106 N2 148 I/O, VREF 3 P54 P65 K12 236 I/O 5 - P103 K4 155 I/O 3 P55 P63 J10 239 Module 4 of 4 2 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S15 Device Pinouts (Continued) XC2S15 Pad Name XC2S15 Device Pinouts (Continued) XC2S15 Pad Name Bank VQ100 TQ144 CS144 Bndry Scan I/O (D6) 3 P56 P62 J11 242 GND - - P61 J12 - I/O (D5) 3 P57 P60 J13 245 I/O I/O 3 P58 P59 H10 248 I/O I/O, VREF 3 P59 P58 H11 251 I, GCK2 I/O (D4) 3 P60 P57 H12 254 I/O 3 - P56 H13 257 Function Bank VQ100 TQ144 CS144 Bndry Scan I/O 1 - P22 C8 21 I/O, VREF 1 P86 P21 B8 24 1 - P20 A8 27 1 P87 P19 B7 30 1 P88 P18 A7 36 GND - P89 P17 C7 - VCCO 1 P90 P16 D7 - Function VCCINT - P61 P55 G12 - VCCO 0 P90 P16 D7 - I/O, TRDY(1) 3 P62 P54 G13 260 I, GCK3 0 P91 P15 A6 37 VCCO 3 P63 P53 G11 - VCCINT - P92 P14 B6 - VCCO 2 P63 P53 G11 - I/O 0 - P13 C6 44 GND - P64 P52 G10 - I/O, VREF 0 P93 P12 D6 47 2 P65 P51 F13 263 I/O 0 - P11 A5 50 I/O, IRDY(1) I/O 2 - P50 F12 266 I/O 0 - P10 B5 53 I/O (D3) 2 P66 P49 F11 269 VCCINT - P94 P9 C5 - I/O, VREF 2 P67 P48 F10 272 GND - - P8 D5 - I/O 2 P68 P47 E13 275 I/O 0 P95 P7 A4 56 I/O (D2) 2 P69 P46 E12 278 I/O 0 P96 P6 B4 59 GND - - P45 E11 - I/O, VREF 0 P97 P5 C4 62 I/O (D1) 2 P70 P44 E10 281 I/O 0 - P4 A3 65 I/O 2 P71 P43 D13 284 I/O 0 P98 P3 B3 68 I/O, VREF 2 P72 P41 D11 287 TCK - P99 P2 C3 - I/O 2 - P40 C13 290 VCCO 0 P100 P1 A2 - I/O (DIN, D0) 2 P73 P39 C12 293 VCCO 7 P100 P144 B2 - I/O (DOUT, BUSY) 2 P74 P38 C11 296 04/18/01 CCLK 2 P75 P37 B13 299 Notes: 1. IRDY and TRDY can only be accessed when using Xilinx PCI cores. VCCO 2 P76 P36 B12 - VCCO 1 P76 P35 A13 - TDO 2 P77 P34 A12 - GND - P78 P33 B11 - TDI - P79 P32 A11 - I/O (CS) 1 P80 P31 D10 0 11/02/00 I/O (WRITE) 1 P81 P30 C10 3 TQ144 I/O 1 - P29 B10 6 I/O, VREF 1 P82 P28 A10 9 I/O 1 P83 P27 D9 12 I/O 1 P84 P26 C9 15 GND - - P25 B9 - VCCINT - P85 P24 A9 - I/O 1 - P23 D8 18 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification Additional XC2S15 Package Pins VQ100 P28 P42 P116 P29 Not Connected Pins - - - P64 P138 Not Connected Pins P78 P101 - P104 - P105 - D12 N3 Not Connected Pins J4 K13 - M3 - M4 - 11/02/00 CS144 D3 M10 11/02/00 www.xilinx.com 1-800-255-7778 Module 4 of 4 3 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S30 Device Pinouts (Continued) XC2S30 Device Pinouts XC2S30 Pad Name Function Bndry Bank VQ100 TQ144 CS144 PQ208 Scan XC2S30 Pad Name Function Bank VQ100 TQ144 CS144 PQ208 Bndry Scan GND - P1 P143 A1 P1 - I/O, VREF 6 P20 P115 K1 P45 203 TMS - P2 P142 B1 P2 - I/O 6 - - - P46 206 I/O 7 P3 P141 C2 P3 113 I/O 6 - P114 K2 P47 209 6 P21 P113 K3 P48 212 I/O 7 - P140 C1 P4 116 I/O I/O 7 - - - P5 119 I/O 6 P22 P112 L1 P49 215 I/O, VREF 7 P4 P139 D4 P6 122 M1 - P23 P111 L2 P50 218 I/O 7 - P138 D3 P8 125 GND - P24 P110 L3 P51 - I/O 7 P5 P137 D2 P9 128 M0 - P25 P109 M1 P52 219 6 P26 P108 M2 P53 - I/O 7 P6 P136 D1 P10 131 VCCO GND - - P135 E4 P11 - VCCO 5 P26 P107 N1 P53 - VCCO 7 - - - P12 - M2 - P27 P106 N2 P54 220 I/O 7 P7 P134 E3 P14 134 I/O 5 - P103 K4 P57 227 I/O 7 - P133 E2 P15 137 I/O 5 - - - P58 230 I/O 7 - - - P16 140 I/O, VREF 5 P30 P102 L4 P59 233 5 - P101 M4 P61 236 I/O 7 - - - P17 143 I/O I/O 7 - - - P18 146 I/O 5 P31 P100 N4 P62 239 GND - - - - P19 - I/O 5 P32 P99 K5 P63 242 I/O, VREF 7 P8 P132 E1 P20 149 GND - - P98 L5 P64 - 5 - - - P65 - I/O 7 P9 P131 F4 P21 152 VCCO I/O 7 - P130 F3 P22 155 VCCINT - P33 P97 M5 P66 - I/O 7 - - - P23 158 I/O 5 - P96 N5 P67 245 I/O, IRDY(1) 7 P10 P129 F2 P24 161 I/O 5 - P95 K6 P68 248 GND - P11 P128 F1 P25 - I/O 5 - - - P69 251 5 - - - P70 254 VCCO 7 P12 P127 G2 P26 - I/O VCCO 6 P12 P127 G2 P26 - I/O 5 - - - P71 257 I/O, TRDY(1) 6 P13 P126 G1 P27 164 GND - - - - P72 - VCCINT - P14 P125 G3 P28 - I/O, VREF 5 P34 P94 L6 P73 260 I/O 6 - P124 G4 P29 170 I/O 5 - - - P74 263 I/O 6 P15 P123 H1 P30 173 I/O 5 - P93 M6 P75 266 - P35 P92 N6 P76 - I/O, VREF 6 P16 P122 H2 P31 176 VCCINT GND - - - - P32 - I, GCK1 5 P36 P91 M7 P77 275 I/O 6 - - - P33 179 VCCO 5 P37 P90 N7 P78 - I/O 6 - - - P34 182 VCCO 4 P37 P90 N7 P78 - - P38 P89 L7 P79 - I/O 6 - - - P35 185 GND I/O 6 - P121 H3 P36 188 I, GCK0 4 P39 P88 K7 P80 276 I/O 6 P17 P120 H4 P37 191 I/O 4 P40 P87 N8 P81 280 VCCO 6 - - - P39 - I/O 4 - P86 M8 P82 283 GND - - P119 J1 P40 - I/O 4 - - - P83 286 4 P41 P85 L8 P84 289 I/O 6 P18 P118 J2 P41 194 I/O, VREF I/O 6 P19 P117 J3 P42 197 GND - - - - P85 - I/O 6 - P116 J4 P43 200 I/O 4 - - - P86 292 Module 4 of 4 4 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S30 Device Pinouts (Continued) XC2S30 Device Pinouts (Continued) XC2S30 Pad Name Function Bndry Bank VQ100 TQ144 CS144 PQ208 Scan XC2S30 Pad Name Function Bank VQ100 TQ144 CS144 PQ208 Bndry Scan I/O 4 - - - P87 295 VCCO 3 P63 P53 G11 P130 - I/O 4 - - - P88 298 VCCO 2 P63 P53 G11 P130 - I/O 4 - P84 K8 P89 301 GND - P64 P52 G10 P131 - I/O 4 - P83 N9 P90 304 I/O, IRDY(1) 2 P65 P51 F13 P132 389 VCCINT - P42 P82 M9 P91 - I/O 2 - - - P133 392 VCCO 4 - - - P92 - I/O 2 - P50 F12 P134 395 GND - - P81 L9 P93 - I/O (D3) 2 P66 P49 F11 P135 398 I/O 4 P43 P80 K9 P94 307 I/O, VREF 2 P67 P48 F10 P136 401 I/O 4 P44 P79 N10 P95 310 GND - - - - P137 - I/O 4 - P78 M10 P96 313 I/O 2 - - - P138 404 I/O, VREF 4 P45 P77 L10 P98 316 I/O 2 - - - P139 407 I/O 4 - - - P99 319 I/O 2 - - - P140 410 I/O 4 - P76 N11 P100 322 I/O 2 P68 P47 E13 P141 413 I/O 4 P46 P75 M11 P101 325 I/O (D2) 2 P69 P46 E12 P142 416 I/O 4 P47 P74 L11 P102 328 VCCO 2 - - - P144 - GND - P48 P73 N12 P103 - GND - - P45 E11 P145 - DONE 3 P49 P72 M12 P104 331 I/O (D1) 2 P70 P44 E10 P146 419 VCCO 4 P50 P71 N13 P105 - I/O 2 P71 P43 D13 P147 422 VCCO 3 P50 P70 M13 P105 - I/O 2 - P42 D12 P148 425 PROGRAM - P51 P69 L12 P106 334 I/O, VREF 2 P72 P41 D11 P150 428 I/O (INIT) 3 P52 P68 L13 P107 335 I/O 2 - - - P151 431 I/O (D7) 3 P53 P67 K10 P108 338 I/O 2 - P40 C13 P152 434 I/O 3 - P66 K11 P109 341 I/O (DIN, D0) 2 P73 P39 C12 P153 437 I/O 3 - - - P110 344 2 P74 P38 C11 P154 440 I/O, VREF 3 P54 P65 K12 P111 347 I/O (DOUT, BUSY) I/O 3 - P64 K13 P113 350 CCLK 2 P75 P37 B13 P155 443 I/O 3 P55 P63 J10 P114 353 VCCO 2 P76 P36 B12 P156 - I/O (D6) 3 P56 P62 J11 P115 356 VCCO 1 P76 P35 A13 P156 - 2 P77 P34 A12 P157 - GND - - P61 J12 P116 - TDO VCCO 3 - - - P117 - GND - P78 P33 B11 P158 - I/O (D5) 3 P57 P60 J13 P119 359 TDI - P79 P32 A11 P159 - I/O 3 P58 P59 H10 P120 362 I/O (CS) 1 P80 P31 D10 P160 0 I/O 3 - - - P121 365 I/O (WRITE) 1 P81 P30 C10 P161 3 1 - P29 B10 P162 6 I/O 3 - - - P122 368 I/O I/O 3 - - - P123 371 I/O 1 - - - P163 9 GND - - - - P124 - I/O, VREF 1 P82 P28 A10 P164 12 I/O, VREF 3 P59 P58 H11 P125 374 I/O 1 - - - P166 15 I/O (D4) 3 P60 P57 H12 P126 377 I/O 1 P83 P27 D9 P167 18 I/O 1 P84 P26 C9 P168 21 I/O 3 - P56 H13 P127 380 VCCINT - P61 P55 G12 P128 - GND - - P25 B9 P169 - I/O, TRDY(1) 3 P62 P54 G13 P129 386 VCCO 1 - - - P170 - DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 5 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S30 Device Pinouts (Continued) XC2S30 Device Pinouts (Continued) XC2S30 Pad Name Function Bndry Bank VQ100 TQ144 CS144 PQ208 Scan XC2S30 Pad Name Function Bank VQ100 TQ144 CS144 PQ208 Bndry Scan VCCINT - P85 P24 A9 P171 - I/O 0 P96 P6 B4 P200 89 I/O 1 - P23 D8 P172 24 I/O 0 - - - P201 92 I/O 1 - P22 C8 P173 27 I/O, VREF 0 P97 P5 C4 P203 95 I/O 1 - - - P174 30 I/O 0 - - - P204 98 I/O 1 - - - P175 33 I/O 0 - P4 A3 P205 101 I/O 1 - - - P176 36 I/O 0 P98 P3 B3 P206 104 GND - - - - P177 - TCK - P99 P2 C3 P207 - I/O, VREF 1 P86 P21 B8 P178 39 VCCO 0 P100 P1 A2 P208 - I/O 1 - - - P179 42 VCCO 7 P100 P144 B2 P208 - I/O 1 - P20 A8 P180 45 04/18/01 I/O 1 P87 P19 B7 P181 48 I, GCK2 1 P88 P18 A7 P182 54 Notes: 1. IRDY and TRDY can only be accessed when using Xilinx PCI cores. GND - P89 P17 C7 P183 - VCCO 1 P90 P16 D7 P184 - VCCO 0 P90 P16 D7 P184 - I, GCK3 0 P91 P15 A6 P185 55 VCCINT - P92 P14 B6 P186 - I/O 0 - P13 C6 P187 62 I/O 0 - - - P188 65 I/O, VREF 0 P93 P12 D6 P189 68 GND - - - - P190 - I/O 0 - - - P191 71 I/O 0 - - - P192 74 I/O 0 - - - P193 77 I/O 0 - P11 A5 P194 80 I/O 0 - P10 B5 P195 83 VCCINT - P94 P9 C5 P196 - VCCO 0 - - - P197 - GND - - P8 D5 P198 - I/O 0 P95 P7 A4 P199 86 Additional XC2S30 Package Pins VQ100 P28 P29 Not Connected Pins - - - P105 Not Connected Pins - - - N3 Not Connected Pins - - - P13 P97 P202 Not Connected Pins P38 P44 P112 P118 - P55 P143 - P56 P149 - 11/02/00 TQ144 P104 11/02/00 CS144 M3 11/02/00 PQ208 P7 P60 P165 11/02/00 XC2S50 Device Pinouts (Continued) XC2S50 Device Pinouts XC2S50 Pad Name XC2S50 Pad Name Function Bank TQ144 PQ208 FG256 Bndry Scan Bank TQ144 PQ208 FG256 Bndry Scan I/O 7 - - A2 152 GND - P143 P1 GND* - I/O 7 P140 P4 B1 155 TMS - P142 P2 D3 - I/O 7 - - E3 158 I/O 7 P141 P3 C2 149 I/O 7 - P5 D2 161 Function Module 4 of 4 6 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S50 Device Pinouts (Continued) XC2S50 Pad Name XC2S50 Device Pinouts (Continued) Bank TQ144 PQ208 FG256 Bndry Scan GND - - - GND* - I/O, VREF 7 P139 P6 C1 164 I/O 7 - P7 F3 167 I/O 7 - - E2 I/O 7 P138 P8 I/O 7 P137 I/O 7 GND - Function VCCO 7 XC2S50 Pad Name Bank TQ144 PQ208 FG256 Bndry Scan VCCINT - - P38 VCCINT* - VCCO 6 - P39 VCCO Bank 6* - 170 GND - P119 P40 GND* - E4 173 I/O 6 P118 P41 K4 254 P9 D1 176 I/O 6 P117 P42 M1 257 P136 P10 E1 179 I/O 6 P116 P43 L4 260 P135 P11 GND* - I/O 6 - - M2 263 VCCO Bank 7* - I/O 6 - P44 L3 266 I/O, VREF 6 P115 P45 N1 269 GND - - - GND* - - P46 P1 272 - P12 Function VCCINT - - P13 VCCINT* - I/O 7 P134 P14 F2 182 I/O 6 I/O 7 P133 P15 G3 185 I/O 6 - - L5 275 I/O 7 - - F1 188 I/O 6 P114 P47 N2 278 I/O 7 - P16 F4 191 I/O 6 - - M4 281 I/O 7 - P17 F5 194 I/O 6 P113 P48 R1 284 I/O 7 - P18 G2 197 I/O 6 P112 P49 M3 287 GND - - P19 GND* - M1 - P111 P50 P2 290 I/O, VREF 7 P132 P20 H3 200 GND - P110 P51 GND* - I/O 7 P131 P21 G4 203 M0 - P109 P52 N3 291 I/O 7 - - H2 206 VCCO 6 P108 P53 - I/O 7 P130 P22 G5 209 VCCO Bank 6* I/O 7 - P23 H4 212 VCCO 5 P107 P53 - I/O, IRDY(1) VCCO Bank 5* 7 P129 P24 G1 215 M2 - P106 P54 R3 292 GND - P128 P25 GND* - I/O 5 - - N5 299 VCCO 7 P127 P26 VCCO Bank 7* - I/O 5 P103 P57 T2 302 VCCO 6 P127 P26 VCCO Bank 6* - I/O 5 - - P5 305 I/O 5 - P58 T3 308 GND - - - GND* - I/O, VREF 5 P102 P59 T4 311 5 - P60 M6 314 I/O, TRDY(1) 6 P126 P27 J2 218 VCCINT - P125 P28 VCCINT* - I/O 6 P124 P29 H1 224 I/O I/O 6 - - J4 227 I/O 5 - - T5 317 I/O 6 P123 P30 J1 230 I/O 5 P101 P61 N6 320 I/O, VREF 6 P122 P31 J3 233 I/O 5 P100 P62 R5 323 GND - - P32 GND* - I/O 5 P99 P63 P6 326 I/O 6 - P33 K5 236 GND - P98 P64 GND* - I/O 6 - P34 K2 239 VCCO 5 - P65 6 - P35 K1 242 VCCO Bank 5* - I/O I/O 6 - - K3 245 VCCINT - P97 P66 VCCINT* - I/O 6 P121 P36 L1 248 I/O 5 P96 P67 R6 329 I/O 6 P120 P37 L2 251 I/O 5 P95 P68 M7 332 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 7 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S50 Device Pinouts (Continued) XC2S50 Pad Name XC2S50 Device Pinouts (Continued) Bank TQ144 PQ208 FG256 Bndry Scan I/O 5 - P69 N7 338 I/O 5 - P70 T6 I/O 5 - P71 GND - - P72 I/O, VREF 5 P94 P73 I/O 5 - I/O 5 - I/O 5 P93 VCCINT - P92 I, GCK1 5 P91 VCCO 5 VCCO 4 Function XC2S50 Pad Name Bank TQ144 PQ208 FG256 Bndry Scan I/O 4 P75 P101 P13 433 341 I/O 4 P74 P102 T14 436 P7 344 GND - P73 P103 GND* - GND* - DONE 3 P72 P104 R14 439 P8 347 VCCO 4 P71 P105 - P74 R7 350 VCCO Bank 4* - T7 353 VCCO 3 P70 P105 VCCO Bank 3* - P75 T8 356 PROGRAM - P69 P106 P15 442 P76 VCCINT* - I/O (INIT) 3 P68 P107 N15 443 P77 R8 365 I/O (D7) 3 P67 P108 N14 446 P90 P78 VCCO Bank 5* - I/O 3 - - T15 449 P90 P78 VCCO Bank 4* - I/O 3 P66 P109 M13 452 I/O 3 - - R16 455 I/O 3 - P110 M14 458 Function GND - P89 P79 GND* - I, GCK0 4 P88 P80 N8 366 GND - - - GND* - I/O 4 P87 P81 N9 370 I/O, VREF 3 P65 P111 L14 461 I/O 4 P86 P82 R9 373 I/O 3 - P112 M15 464 I/O 4 - - N10 376 I/O 3 - - L12 467 I/O 4 - P83 T9 379 I/O 3 P64 P113 P16 470 I/O, VREF 4 P85 P84 P9 382 I/O 3 P63 P114 L13 473 GND - - P85 GND* - I/O (D6) 3 P62 P115 N16 476 I/O 4 - P86 M10 385 GND - P61 P116 GND* - I/O 4 - P87 R10 388 VCCO 3 - P117 - I/O 4 - P88 P10 391 VCCO Bank 3* I/O 4 P84 P89 T10 397 VCCINT - - P118 VCCINT* - I/O 4 P83 P90 R11 400 I/O (D5) 3 P60 P119 M16 479 VCCINT - P82 P91 VCCINT* - I/O 3 P59 P120 K14 482 VCCO Bank 4* - I/O 3 - - L16 485 I/O 3 - P121 K13 488 VCCO 4 - P92 GND - P81 P93 GND* - I/O 3 - P122 L15 491 I/O 4 P80 P94 M11 403 I/O 3 - P123 K12 494 I/O 4 P79 P95 T11 406 GND - - P124 GND* - I/O 4 P78 P96 N11 409 I/O, VREF 3 P58 P125 K16 497 I/O 4 - - R12 412 I/O (D4) 3 P57 P126 J16 500 I/O 4 - P97 P11 415 I/O 3 - - J14 503 I/O, VREF 4 P77 P98 T12 418 I/O 3 P56 P127 K15 506 GND - - - GND* - VCCINT - P55 P128 VCCINT* - I/O 4 - P99 T13 421 I/O, TRDY(1) 3 P54 P129 J15 512 I/O 4 - - N12 424 VCCO 3 P53 P130 - I/O 4 P76 P100 R13 427 VCCO Bank 3* I/O 4 - - P12 430 VCCO 2 P53 P130 VCCO Bank 2* - Module 4 of 4 8 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Function GND I/O, IRDY(1) XC2S50 Device Pinouts (Continued) Bank TQ144 PQ208 FG256 Bndry Scan - P52 P131 GND* - 2 P51 P132 H16 XC2S50 Pad Name Bank TQ144 PQ208 FG256 Bndry Scan I/O 1 - - C12 6 515 I/O 1 P29 P162 A14 9 Function I/O 2 - P133 H14 518 I/O 1 - - D12 12 I/O 2 P50 P134 H15 521 I/O 1 - P163 B12 15 I/O 2 - - J13 524 GND - - - GND* - I/O (D3) 2 P49 P135 G16 527 I/O, VREF 1 P28 P164 C11 18 I/O, VREF 2 P48 P136 H13 530 I/O 1 - P165 A13 21 GND - - P137 GND* - I/O 1 - - D11 24 I/O 2 - P138 G14 533 I/O 1 - P166 A12 27 I/O 2 - P139 G15 536 I/O 1 P27 P167 E11 30 I/O 2 - P140 G12 539 I/O 1 P26 P168 B11 33 I/O 2 - - F16 542 GND - P25 P169 GND* - I/O 2 P47 P141 G13 545 VCCO 1 - P170 - I/O (D2) 2 P46 P142 F15 548 VCCO Bank 1* VCCINT - - P143 VCCINT* - VCCINT - P24 P171 VCCINT* - VCCO 2 - P144 VCCO Bank 2* - I/O 1 P23 P172 A11 36 I/O 1 P22 P173 C10 39 GND - P45 P145 GND* - I/O 1 - P174 B10 45 I/O (D1) 2 P44 P146 E16 551 I/O 1 - P175 D10 48 I/O 2 P43 P147 F14 554 I/O 1 - P176 A10 51 I/O 2 P42 P148 D16 557 GND - - P177 GND* - I/O 2 - - F12 560 I/O, VREF 1 P21 P178 B9 54 I/O 2 - P149 E15 563 I/O 1 - P179 E10 57 I/O, VREF 2 P41 P150 F13 566 I/O 1 - - A9 60 GND - - - GND* - I/O 1 P20 P180 D9 63 I/O 2 - P151 E14 569 I/O 1 P19 P181 A8 66 I/O 2 - - C16 572 I, GCK2 1 P18 P182 C9 72 I/O 2 P40 P152 E13 575 GND - P17 P183 GND* - I/O 2 - - B16 578 VCCO 1 P16 P184 - I/O (DIN, D0) 2 P39 P153 D14 581 VCCO Bank 1* I/O (DOUT, BUSY) 2 P38 P154 C15 584 VCCO 0 P16 P184 VCCO Bank 0* - CCLK 2 P37 P155 D15 587 I, GCK3 0 P15 P185 B8 73 VCCO Bank 2* - VCCINT - P14 P186 VCCINT* - I/O 0 P13 P187 A7 80 I/O 0 - - D8 83 A6 86 VCCO 2 P36 P156 VCCO 1 P35 P156 VCCO Bank 1* - I/O 0 - P188 TDO 2 P34 P157 B14 - I/O, VREF 0 P12 P189 B7 89 GND - P33 P158 GND* - GND - - P190 GND* - TDI - P32 P159 A15 - I/O 0 - P191 C8 92 I/O (CS) 1 P31 P160 B13 0 I/O 0 - P192 D7 95 I/O (WRITE) 1 P30 P161 C13 3 I/O 0 - P193 E7 98 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 9 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Function I/O Additional XC2S50 Package Pins Bank TQ144 PQ208 FG256 Bndry Scan 0 P11 P194 C7 104 P104 11/02/00 I/O 0 P10 P195 B6 107 VCCINT - P9 P196 VCCINT* - VCCO 0 - P197 VCCO Bank 0* - TQ144 P105 Not Connected Pins - - - P56 Not Connected Pins - - - E5 P3 E12 P14 - - - - - - - - - - - - - - - - F6 G8 H9 K6 L6 T1 F7 G9 H10 K7 L7 T16 - - PQ208 P55 11/02/00 GND - P8 P198 GND* - I/O 0 P7 P199 A5 110 I/O 0 P6 P200 C6 113 I/O 0 - P201 B5 116 I/O 0 - - D6 119 I/O 0 - P202 A4 122 I/O, VREF 0 P5 P203 B4 125 GND - - - GND* - I/O 0 - P204 E6 128 I/O 0 - - D5 131 I/O 0 P4 P205 A3 134 I/O 0 - - C5 137 I/O 0 P3 P206 B3 140 TCK - P2 P207 C4 - VCCO 0 P1 P208 VCCO Bank 0* - VCCO 7 P144 P208 VCCO Bank 7* - 04/18/01 Notes: 1. IRDY and TRDY can only be accessed when using Xilinx PCI cores. 2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*, VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*, VCCO Bank 6*, VCCO Bank 7* are internally bonded to independent ground or power planes within the package. FG256 C3 M5 C14 M12 E8 F8 E9 F9 H11 H12 J11 J12 L9 M9 L8 M8 J5 J6 H5 H6 A1 F10 G10 J7 K8 L10 A16 F11 G11 J8 K9 L11 P4 R4 VCCINT Pins D4 D13 N4 N13 VCCO Bank 0 Pins VCCO Bank 1 Pins VCCO Bank 2 Pins VCCO Bank 3 Pins VCCO Bank 4 Pins VCCO Bank 5 Pins VCCO Bank 6 Pins VCCO Bank 7 Pins GND Pins B2 B15 G6 G7 H7 H8 J9 J10 K10 K11 R2 R15 Not Connected Pins - 11/02/00 Module 4 of 4 10 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S100 Device Pinouts (Continued) XC2S100 Device Pinouts XC2S100 Pad Name Function Bank TQ144 PQ208 FG256 FG456 Bndry Scan XC2S100 Pad Name Function GND - P143 P1 GND* GND* - VCCINT TMS - P142 P2 D3 D3 - Bank TQ144 PQ208 FG256 FG456 VCCINT* VCCINT* Bndry Scan - P125 P28 - I/O 6 P124 P29 H1 M3 281 6 - - J4 M4 284 I/O 7 P141 P3 C2 B1 185 I/O I/O 7 - - A2 F5 191 I/O 6 P123 P30 J1 M5 287 I/O 7 P140 P4 B1 D2 194 I/O, VREF 6 P122 P31 J3 N2 290 I/O 7 - - - E3 197 GND - - P32 GND* GND* - I/O 7 - - E3 G5 200 I/O 6 - P33 K5 N3 293 6 - P34 K2 N4 296 I/O 7 - P5 D2 F3 203 I/O GND - - - GND* GND* - I/O 6 - P35 K1 P2 302 VCCO 7 - - - I/O 6 - - K3 P4 305 I/O 6 P121 P36 L1 P3 308 I/O, VREF 7 P139 P6 C1 E2 206 I/O 6 P120 P37 L2 R2 311 I/O 7 - P7 F3 E1 209 VCCINT - - P38 I/O 7 - - E2 H5 215 VCCO 6 - P39 I/O 7 P138 P8 E4 F2 218 I/O 7 - - - F1 221 GND - P119 P40 I/O, VREF 7 P137 P9 D1 H4 224 I/O 6 P118 P41 I/O, VREF 6 P117 P42 VCCO VCCO Bank 7* Bank 7* VCCINT* VCCINT* VCCO VCCO Bank 6* Bank 6* GND* - GND* - K4 T1 314 M1 R4 317 I/O 7 P136 P10 E1 G1 227 GND - P135 P11 GND* GND* - I/O 6 - - - T2 320 VCCO 7 - P12 VCCO VCCO Bank 7* Bank 7* - I/O 6 P116 P43 L4 U1 323 I/O 6 - - M2 R5 326 VCCINT - - P13 - I/O 7 P134 P14 VCCINT* VCCINT* F2 H3 I/O 7 P133 P15 G3 I/O 7 - - F1 I/O 7 - P16 I/O 7 - P17 I/O 6 - P44 L3 U2 332 230 I/O, VREF 6 P115 P45 N1 T3 335 H2 233 VCCO 6 - - J5 236 F4 J2 239 GND - - - GND* F5 K5 245 I/O 6 - P46 P1 T4 338 6 - - L5 W1 341 VCCO VCCO Bank 6* Bank 6* GND* - I/O 7 - P18 G2 K1 248 I/O GND - - P19 GND* GND* - I/O 6 - - - U4 344 I/O, VREF 7 P132 P20 H3 K3 251 I/O 6 P114 P47 N2 Y1 347 I/O 7 P131 P21 G4 K4 254 I/O 6 - - M4 W2 350 I/O 7 - - H2 L6 257 I/O 6 P113 P48 R1 Y2 356 6 P112 P49 M3 W3 359 I/O 7 P130 P22 G5 L1 260 I/O I/O 7 - P23 H4 L4 266 M1 - P111 P50 P2 U5 362 I/O, IRDY(1) 7 P129 P24 G1 L3 269 GND - P110 P51 GND* GND* - GND - P128 P25 GND* GND* - M0 - P109 P52 N3 AB2 363 VCCO 7 P127 P26 VCCO VCCO Bank 7* Bank 7* - VCCO 6 P108 P53 VCCO VCCO Bank 6* Bank 6* - VCCO 6 P127 P26 VCCO VCCO Bank 6* Bank 6* - VCCO 5 P107 P53 VCCO VCCO Bank 5* Bank 5* - I/O, TRDY(1) 6 P126 P27 M2 - P106 P54 R3 Y4 364 I/O 5 - - N5 V7 374 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification J2 M1 272 www.xilinx.com 1-800-255-7778 Module 4 of 4 11 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Function XC2S100 Device Pinouts (Continued) XC2S100 Pad Name FG456 Bndry Scan T2 Y6 377 GND - - P85 Bank TQ144 PQ208 FG256 Function FG456 Bndry Scan GND* GND* - Bank TQ144 PQ208 FG256 I/O 5 P103 P57 I/O 5 - - - AA4 380 I/O 4 - P86 M10 Y13 478 I/O 5 - - P5 W6 383 I/O 4 - P87 R10 V13 481 I/O 5 - P58 T3 Y7 386 I/O 4 - P88 P10 AA14 487 GND - - - GND* GND* - I/O 4 - - - V14 490 VCCO 5 - - - I/O 4 P84 P89 T10 AB15 493 I/O 4 P83 P90 R11 AA15 496 I/O, VREF 5 P102 P59 T4 AA5 389 VCCINT - P82 P91 I/O 5 - P60 M6 AB5 392 VCCO 4 - P92 I/O 5 - - T5 AB6 398 I/O 5 P101 P61 N6 AA7 401 GND - P81 P93 GND* VCCO VCCO Bank 5* Bank 5* VCCINT* VCCINT* VCCO VCCO Bank 4* Bank 4* - GND* - I/O 5 - - - W7 404 I/O 4 P80 P94 M11 Y15 499 I/O, VREF 5 P100 P62 R5 W8 407 I/O, VREF 4 P79 P95 T11 AB16 502 I/O 5 P99 P63 P6 Y8 410 I/O 4 - - - AB17 505 GND - P98 P64 GND* GND* - I/O 4 P78 P96 N11 V15 508 VCCO 5 - P65 VCCO VCCO Bank 5* Bank 5* - I/O 4 - - R12 Y16 511 I/O 4 - P97 P11 AB18 517 VCCINT - P97 P66 - I/O, VREF 4 P77 P98 T12 AB19 520 I/O 5 P96 P67 VCCINT* VCCINT* R6 AA8 VCCO 4 - - I/O 5 P95 P68 M7 V9 416 I/O 5 - - - AB9 419 GND - - - I/O 5 - P69 N7 Y9 422 I/O 4 - I/O 5 - P70 T6 W10 428 I/O 4 - I/O 5 - P71 P7 AB10 431 I/O 4 GND - - P72 GND* GND* - I/O I/O, VREF 5 P94 P73 P8 Y10 434 I/O 5 - P74 R7 V11 I/O 5 - - T7 W11 I/O 5 P93 P75 T8 AB11 443 VCCINT - P92 P76 I, GCK1 5 P91 P77 VCCO 5 P90 P78 VCCO 4 P90 P78 VCCINT* VCCINT* R8 Y11 413 VCCO VCCO Bank 4* Bank 4* - GND* GND* - P99 T13 Y17 523 - N12 V16 526 - - - W17 529 4 P76 P100 R13 AB20 532 I/O 4 - - P12 AA19 535 437 I/O 4 P75 P101 P13 AA20 541 440 I/O 4 P74 P102 T14 W18 544 GND - P73 P103 GND* GND* - - DONE 3 P72 P104 R14 Y19 547 455 VCCO 4 P71 P105 VCCO VCCO Bank 4* Bank 4* - VCCO 3 P70 P105 VCCO VCCO Bank 3* Bank 3* - PROGRAM - P69 P106 VCCO VCCO Bank 5* Bank 5* - VCCO VCCO Bank 4* Bank 4* - P15 W20 550 GND - P89 P79 GND* GND* - I/O (INIT) 3 P68 P107 N15 V19 551 I, GCK0 4 P88 P80 N8 W12 456 I/O (D7) 3 P67 P108 N14 Y21 554 I/O 4 P87 P81 N9 U12 460 I/O 3 - - T15 W21 560 I/O 4 P86 P82 R9 Y12 466 I/O 3 P66 P109 M13 U20 563 I/O 4 - - N10 AA12 469 I/O 3 - - - U19 566 I/O 4 - P83 T9 AB13 472 I/O 3 - - R16 T18 569 I/O, VREF 4 P85 P84 P9 AA13 475 I/O 3 - P110 M14 W22 572 Module 4 of 4 12 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Function Bank TQ144 PQ208 FG256 GND - - - VCCO 3 - - GND* XC2S100 Device Pinouts (Continued) XC2S100 Pad Name FG456 Bndry Scan GND* - I/O - I/O 2 I/O (D2) 2 VCCO VCCO Bank 3* Bank 3* Function Bank TQ144 PQ208 FG256 2 - FG456 Bndry Scan 674 - F16 J22 P47 P141 G13 H19 677 P46 P142 F15 H20 680 I/O, VREF 3 P65 P111 L14 U21 575 VCCINT - - P143 I/O 3 - P112 M15 T20 578 VCCO 2 - P144 I/O 3 - - L12 T21 584 I/O 3 P64 P113 P16 R18 587 GND - P45 P145 GND* GND* - I/O 3 - - - U22 590 I/O (D1) 2 P44 P146 E16 H22 683 I/O, VREF 3 P63 P114 L13 R19 593 I/O, VREF 2 P43 P147 F14 H18 686 I/O (D6) 3 P62 P115 N16 T22 596 I/O 2 - - - G21 689 GND - P61 P116 GND* GND* - I/O 2 P42 P148 D16 G18 692 VCCO 3 - P117 VCCO VCCO Bank 3* Bank 3* - I/O 2 - - F12 G20 695 I/O 2 - P149 E15 F19 701 VCCINT* VCCINT* M16 R21 - I/O, VREF 2 P41 P150 F13 F21 704 VCCO 2 - - VCCINT - - P118 I/O (D5) 3 P60 P119 I/O 3 P59 P120 I/O 3 - I/O 3 - I/O 3 - I/O 3 GND - 599 VCCINT* VCCINT* VCCO VCCO Bank 2* Bank 2* VCCO VCCO Bank 2* Bank 2* - - K14 P18 602 - L16 P20 605 GND - - - GND* GND* - P121 K13 P21 608 I/O 2 - P151 E14 F20 707 P122 L15 N18 614 I/O 2 - - C16 F18 710 - P123 K12 N20 617 I/O 2 - - - E21 713 - P124 GND* GND* - I/O 2 P40 P152 E13 D22 716 I/O, VREF 3 P58 P125 K16 N21 620 I/O 2 - - B16 E20 719 I/O (D4) 3 P57 P126 J16 N22 623 2 P39 P153 D14 D20 725 I/O 3 - - J14 M19 626 I/O (DIN, D0) I/O 3 P56 P127 K15 M20 629 I/O (DOUT, BUSY) 2 P38 P154 C15 C21 728 - P55 P128 E5 VCCINT* - CCLK 2 P37 P155 D15 B22 731 3 P54 P129 J15 M22 638 P36 P156 P53 P130 VCCO VCCO Bank 3* Bank 3* - VCCO VCCO Bank 2* Bank 2* - 3 VCCO 2 VCCO P35 P156 P53 P130 VCCO VCCO Bank 2* Bank 2* - VCCO VCCO Bank 1* Bank 1* - 2 VCCO 1 VCCO TDO 2 P34 P157 B14 A21 - GND - P52 P131 GND* GND* - I/O, IRDY(1) GND - P33 P158 GND* GND* - 2 P51 P132 H16 L20 641 TDI - P32 P159 A15 B20 - I/O 2 - P133 H14 L17 644 I/O (CS) B13 C19 0 I/O 2 P50 P134 H15 L21 650 I/O 2 - - J13 L22 653 I/O (D3) 2 P49 P135 G16 K20 656 I/O, VREF 2 P48 P136 H13 K21 659 GND - - P137 GND* GND* - I/O 2 - P138 G14 K22 662 I/O 2 - P139 G15 J21 665 I/O 2 - P140 G12 J18 671 VCCINT I/O, TRDY(1) DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification 1 P31 P160 I/O (WRITE) 1 P30 P161 C13 A20 3 I/O 1 - - C12 D17 9 I/O 1 P29 P162 A14 A19 12 I/O 1 - - - B18 15 I/O 1 - - D12 C17 18 I/O 1 - P163 B12 D16 21 GND - - - GND* GND* - www.xilinx.com 1-800-255-7778 Module 4 of 4 13 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Function Bank TQ144 PQ208 FG256 FG456 VCCO VCCO Bank 1* Bank 1* XC2S100 Device Pinouts (Continued) Bndry Scan VCCO 1 - - - I/O, VREF 1 P28 P164 C11 A18 24 I/O 1 - P165 A13 B17 27 I/O 1 - - D11 D15 33 I/O 1 - P166 A12 C16 36 I/O 1 - - - D14 39 I/O, VREF 1 P27 P167 E11 E14 42 I/O 1 P26 P168 B11 A16 45 GND - P25 P169 GND* GND* - VCCO 1 - P170 VCCO VCCO Bank 1* Bank 1* - VCCINT - P24 P171 - I/O 1 P23 P172 VCCINT* VCCINT* A11 C15 I/O 1 P22 P173 C10 I/O 1 - - I/O 1 - I/O 1 I/O XC2S100 Pad Name Function Bank TQ144 PQ208 FG256 A6 FG456 Bndry Scan C10 107 I/O 0 - P188 I/O, VREF 0 P12 P189 B7 A9 110 GND - - P190 GND* GND* - I/O 0 - P191 C8 B9 113 I/O 0 - P192 D7 E10 116 I/O 0 - P193 E7 A8 122 I/O 0 - - - D9 125 I/O 0 P11 P194 C7 E9 128 I/O 0 P10 P195 B6 A7 131 VCCINT - P9 P196 VCCO 0 - P197 VCCINT* VCCINT* VCCO VCCO Bank 0* Bank 0* - GND - P8 P198 GND* GND* - 48 I/O 0 P7 P199 A5 B7 134 B15 51 I/O, VREF 0 P6 P200 C6 E8 137 - F12 54 I/O 0 - - - D8 140 P174 B10 C14 57 I/O 0 - P201 B5 C7 143 - P175 D10 D13 63 I/O 0 - - D6 D7 146 1 - P176 A10 C13 66 I/O 0 - P202 A4 D6 152 GND - - P177 GND* GND* - I/O, VREF 0 P5 P203 B4 C6 155 I/O, VREF 1 P21 P178 B9 B13 69 VCCO 0 - - I/O 1 - P179 E10 E12 72 I/O 1 - - A9 B12 75 GND - - - GND* GND* - I/O 1 P20 P180 D9 D12 78 I/O 0 - P204 E6 B5 158 I/O 1 P19 P181 A8 D11 84 I/O 0 - - D5 E7 161 I, GCK2 1 P18 P182 C9 A11 90 I/O 0 - - - E6 164 GND* GND* VCCO VCCO Bank 0* Bank 0* - GND - P17 P183 - I/O 0 P4 P205 A3 B4 167 VCCO 1 P16 P184 VCCO VCCO Bank 1* Bank 1* - I/O 0 - - C5 A3 170 I/O 0 P3 P206 B3 C5 176 VCCO 0 P16 P184 VCCO VCCO Bank 0* Bank 0* - TCK - P2 P207 C4 C4 - I, GCK3 0 P15 P185 VCCO 0 P1 P208 VCCO VCCO Bank 0* Bank 0* - VCCINT - P14 P186 VCCO 7 P144 P208 0 P13 P187 VCCO VCCO Bank 7* Bank 7* - I/O I/O 0 - - B8 C11 VCCINT* VCCINT* A7 A10 D8 B10 91 101 104 04/18/01 Notes: 1. IRDY and TRDY can only be accessed when using Xilinx PCI cores. 2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*, VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*, VCCO Bank 6*, VCCO Bank 7* are internally bonded to independent ground or power planes within the package. Module 4 of 4 14 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables Additional XC2S100 Package Pins (Continued) Additional XC2S100 Package Pins VCCO Bank 1 Pins TQ144 F13 Not Connected Pins P104 P105 - - - F15 F16 G12 G13 K17 L16 R17 T17 U15 U16 U8 U9 R6 T6 K7 L7 VCCO Bank 2 Pins G17 11/02/00 H17 J17 K16 VCCO Bank 3 Pins PQ208 M16 Not Connected Pins P55 F14 P56 - - - - 11/02/00 N16 N17 P17 VCCO Bank 4 Pins T12 T13 U13 U14 VCCO Bank 5 Pins FG256 T10 T11 VCCINT Pins C3 C14 D4 D13 E5 E12 M5 M12 N4 N13 P3 P14 - - - - - - VCCO Bank 0 Pins E8 F8 - - E9 F9 - - VCCO Bank 2 Pins H11 H12 - - VCCO Bank 3 Pins J11 J12 - - - - - - - - VCCO Bank 4 Pins L9 M9 L8 M8 - - VCCO Bank 5 Pins - - VCCO Bank 6 Pins J5 J6 - - - - VCCO Bank 7 Pins H5 H6 - - - - GND Pins A1 F10 A16 F11 B2 G6 B15 G7 F6 G8 F7 G9 G10 G11 H7 H8 H9 H10 J7 J8 J9 J10 K6 K7 K8 K9 K10 K11 L6 L7 L10 L11 R2 R15 T1 T16 Not Connected Pins P4 R4 - - M7 - - 11/02/00 FG456 VCCINT Pins E5 E18 F6 F17 G7 G8 G9 G14 G15 G16 H7 H16 J7 J16 P7 P16 R7 R16 T7 T8 T9 T14 T15 T16 U6 U17 V5 V18 - - G10 G11 U7 N6 N7 P6 VCCO Bank 7 Pins G6 VCCO Bank 1 Pins U10 VCCO Bank 6 Pins H6 J6 K6 GND Pins A1 A22 B2 B21 C3 C20 J9 J10 J11 J12 J13 J14 K9 K10 K11 K12 K13 K14 L9 L10 L11 L12 L13 L14 M9 M10 M11 M12 M13 M14 N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 Y3 Y20 AA2 AA21 AB1 AB22 A2 A4 A5 A6 A12 A13 A14 A15 A17 B3 B6 B8 B11 B14 B16 B19 C1 C2 C8 C9 C12 C18 C22 D1 D4 D5 D10 D18 D19 D21 E17 Not Connected Pins E4 E11 E13 E15 E16 E19 E22 F4 F11 F22 G2 G3 G4 G19 G22 H1 H21 J1 J3 J4 J19 J20 K2 K18 K19 L2 L5 L18 L19 M2 M6 M17 M18 M21 N1 N5 N19 P1 P5 P19 P22 R1 R3 R20 R22 T5 T19 U3 U11 U18 V1 V2 V10 V12 V17 V3 V4 V6 V8 V20 V21 V22 W4 W5 W9 W13 W14 W15 W16 W19 Y5 Y14 Y18 Y22 AA1 AA3 AA6 AA9 AA10 AA11 AA16 AA17 AA18 AA22 AB3 AB4 AB7 AB8 AB12 AB14 AB21 - - - - 11/02/00 VCCO Bank 0 Pins F10 F7 F8 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification F9 www.xilinx.com 1-800-255-7778 Module 4 of 4 15 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S150 Device Pinouts (Continued) XC2S150 Device Pinouts XC2S150 Pad Name XC2S150 Pad Name Bank PQ208 FG256 FG456 Bndry Scan Bank PQ208 FG256 FG456 Bndry Scan GND - P1 GND* GND* - I/O 7 P22 G5 L1 314 TMS - P2 D3 D3 - I/O 7 - - L5 317 I/O 7 P3 C2 B1 221 I/O 7 P23 H4 L4 320 7 P24 G1 L3 323 Function Function I/O 7 - - E4 224 I/O, IRDY(1) I/O 7 - - C1 227 GND - P25 GND* GND* - I/O 7 - A2 F5 230 VCCO 7 P26 - - GND* GND* - VCCO Bank 7* - GND VCCO Bank 7* I/O 7 P4 B1 D2 233 VCCO 6 P26 VCCO Bank 6* VCCO Bank 6* - I/O 7 - - E3 236 I/O, TRDY(1) 6 P27 J2 M1 326 I/O 7 - - F4 239 VCCINT - P28 VCCINT* VCCINT* - I/O 7 - E3 G5 242 I/O 6 - - M6 332 I/O 7 P5 D2 F3 245 I/O 6 P29 H1 M3 335 GND - - GND* GND* - I/O 6 - J4 M4 338 VCCO 7 - VCCO Bank 7* VCCO Bank 7* - I/O 6 P30 J1 M5 341 I/O, VREF 7 P6 C1 E2 248 I/O, VREF 6 P31 J3 N2 344 I/O 7 P7 F3 E1 251 VCCO 6 - VCCO Bank 6* VCCO Bank 6* - I/O 7 - - G4 254 GND - P32 GND* GND* - I/O 7 - - G3 257 I/O 6 P33 K5 N3 347 I/O 7 - E2 H5 260 I/O 6 P34 K2 N4 350 I/O 7 P8 E4 F2 263 I/O 6 - - N5 356 I/O 7 - - F1 266 I/O 6 P35 K1 P2 359 I/O, VREF 7 P9 D1 H4 269 I/O 6 - K3 P4 362 I/O 7 P10 E1 G1 272 I/O 6 - - R1 365 GND - P11 GND* GND* - I/O 6 P36 L1 P3 371 VCCO 7 P12 VCCO Bank 7* VCCO Bank 7* - I/O 6 P37 L2 R2 374 VCCINT - P13 VCCINT* VCCINT* - VCCINT - P38 VCCINT* VCCINT* - I/O 7 P14 F2 H3 275 VCCO 6 P39 VCCO Bank 6* VCCO Bank 6* - I/O 7 P15 G3 H2 278 GND - P40 GND* GND* - I/O 7 - - H1 284 I/O 7 - F1 J5 287 I/O 7 P16 F4 J2 290 I/O 7 - - J3 293 I/O 7 P17 F5 K5 299 I/O 7 P18 G2 K1 302 GND - P19 GND* GND* - VCCO 7 - VCCO Bank 7* VCCO Bank 7* - I/O, VREF 7 P20 H3 K3 I/O 7 P21 G4 I/O 7 - H2 Module 4 of 4 16 I/O 6 P41 K4 T1 377 I/O, VREF 6 P42 M1 R4 380 I/O 6 - - T2 383 I/O 6 P43 L4 U1 386 I/O 6 - M2 R5 389 I/O 6 - - V1 392 I/O 6 - - T5 395 I/O 6 P44 L3 U2 398 305 I/O, VREF 6 P45 N1 T3 401 K4 308 VCCO 6 - VCCO Bank 6* VCCO Bank 6* - L6 311 GND - - GND* GND* - www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S150 Device Pinouts (Continued) XC2S150 Pad Name XC2S150 Device Pinouts (Continued) Bank PQ208 FG256 FG456 Bndry Scan I/O 6 P46 P1 T4 404 I/O 6 - L5 W1 407 I/O 6 - - V2 410 Function XC2S150 Pad Name Function Bndry Scan Bank PQ208 FG256 FG456 5 P65 VCCO Bank 5* VCCO Bank 5* VCCINT - P66 VCCINT* VCCINT* - 5 P67 R6 AA8 494 VCCO - I/O 6 - - U4 413 I/O I/O 6 P47 N2 Y1 416 I/O 5 P68 M7 V9 497 GND - - GND* GND* - I/O 5 - - W9 503 I/O 6 - M4 W2 419 I/O 5 - - AB9 506 I/O 6 - - V3 422 I/O 5 P69 N7 Y9 509 5 - - V10 512 I/O 6 - - V4 425 I/O I/O 6 P48 R1 Y2 428 I/O 5 P70 T6 W10 518 I/O 6 P49 M3 W3 431 I/O 5 P71 P7 AB10 521 M1 - P50 P2 U5 434 GND - P72 GND* GND* - GND - P51 GND* GND* - VCCO 5 - VCCO Bank 5* VCCO Bank 5* - M0 - P52 N3 AB2 435 P73 P8 Y10 524 6 P53 VCCO Bank 6* VCCO Bank 6* - I/O, VREF 5 VCCO I/O 5 P74 R7 V11 527 VCCO 5 P53 VCCO Bank 5* VCCO Bank 5* - I/O 5 - T7 W11 530 I/O 5 P75 T8 AB11 533 M2 - P54 R3 Y4 436 I/O 5 - - U11 536 I/O 5 - - W5 443 VCCINT - P76 VCCINT* VCCINT* - I/O 5 - - AB3 446 I, GCK1 5 P77 R8 Y11 545 I/O 5 - N5 V7 449 VCCO 5 P78 VCCO Bank 5* VCCO Bank 5* - VCCO 4 P78 VCCO Bank 4* VCCO Bank 4* - GND - P79 GND* GND* - I, GCK0 4 P80 N8 W12 546 I/O 4 P81 N9 U12 550 I/O 4 - - V12 553 I/O 4 P82 R9 Y12 556 I/O 4 - N10 AA12 559 GND - - GND* GND* - I/O 5 P57 T2 Y6 452 I/O 5 - - AA4 455 I/O 5 - - AB4 458 I/O 5 - P5 W6 461 I/O 5 P58 T3 Y7 464 GND - - GND* GND* - VCCO 5 - VCCO Bank 5* VCCO Bank 5* - I/O, VREF 5 P59 T4 AA5 467 I/O 4 P83 T9 AB13 562 4 P84 P9 AA13 565 I/O 5 P60 M6 AB5 470 I/O, VREF I/O 5 - - V8 473 VCCO 4 - VCCO Bank 4* VCCO Bank 4* - I/O 5 - - AA6 476 GND - P85 GND* GND* - I/O 5 - T5 AB6 479 I/O 4 P86 M10 Y13 568 I/O 5 P61 N6 AA7 482 I/O 4 P87 R10 V13 571 I/O 5 - - W7 485 I/O 4 - - W14 577 I/O, VREF 5 P62 R5 W8 488 I/O 4 P88 P10 AA14 580 I/O 5 P63 P6 Y8 491 I/O 4 - - V14 583 GND - P64 GND* GND* - DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification I/O 4 - - Y14 586 I/O 4 P89 T10 AB15 592 www.xilinx.com 1-800-255-7778 Module 4 of 4 17 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S150 Device Pinouts (Continued) XC2S150 Pad Name XC2S150 Device Pinouts (Continued) Bank PQ208 FG256 FG456 Bndry Scan I/O 4 P90 R11 AA15 595 VCCINT - P91 VCCINT* VCCINT* VCCO 4 P92 VCCO Bank 4* Function XC2S150 Pad Name Bank PQ208 FG256 FG456 Bndry Scan I/O 3 - - U19 677 - I/O 3 - - V21 680 VCCO Bank 4* - I/O 3 - R16 T18 683 I/O 3 P110 M14 W22 686 Function GND - P93 GND* GND* - GND - - GND* GND* - I/O 4 P94 M11 Y15 598 VCCO 3 - 4 P95 T11 AB16 601 VCCO Bank 3* VCCO Bank 3* - I/O, VREF I/O 4 - - AB17 604 I/O, VREF 3 P111 L14 U21 689 I/O 4 P96 N11 V15 607 I/O 3 P112 M15 T20 692 I/O 4 - R12 Y16 610 I/O 3 - - T19 695 I/O 4 - - AA17 613 I/O 3 - - V22 698 I/O 4 - - W16 616 I/O 3 - L12 T21 701 I/O 4 P97 P11 AB18 619 I/O 3 P113 P16 R18 704 I/O, VREF 4 P98 T12 AB19 622 I/O 3 - - U22 707 VCCO 4 - VCCO Bank 4* VCCO Bank 4* - I/O, VREF 3 P114 L13 R19 710 I/O (D6) 3 P115 N16 T22 713 GND - - GND* GND* - GND - P116 GND* GND* - I/O 4 P99 T13 Y17 625 VCCO 3 P117 4 - N12 V16 628 VCCO Bank 3* VCCO Bank 3* - I/O I/O 4 - - AA18 631 VCCINT - P118 VCCINT* VCCINT* - I/O 4 - - W17 634 I/O (D5) 3 P119 M16 R21 716 I/O 4 P100 R13 AB20 637 I/O 3 P120 K14 P18 719 GND - - GND* GND* - I/O 3 - - P19 725 I/O 4 - P12 AA19 640 I/O 3 - L16 P20 728 I/O 4 - - V17 643 I/O 3 P121 K13 P21 731 I/O 4 - - Y18 646 I/O 3 - - N19 734 I/O 4 P101 P13 AA20 649 I/O 3 P122 L15 N18 740 I/O 4 P102 T14 W18 652 I/O 3 P123 K12 N20 743 GND - P103 GND* GND* - GND - P124 GND* GND* - DONE 3 P104 R14 Y19 655 VCCO 3 - 4 P105 VCCO Bank 4* VCCO Bank 4* - VCCO Bank 3* - VCCO VCCO Bank 3* I/O, VREF 3 P125 K16 N21 746 VCCO Bank 3* VCCO Bank 3* - I/O (D4) 3 P126 J16 N22 749 I/O 3 - J14 M19 752 VCCO 3 P105 PROGRAM - P106 P15 W20 658 I/O 3 P127 K15 M20 755 I/O (INIT) 3 P107 N15 V19 659 I/O 3 - - M18 758 I/O (D7) 3 P108 N14 Y21 662 VCCINT - P128 VCCINT* VCCINT* - I/O 3 - - V20 665 I/O, 3 P129 J15 M22 764 I/O 3 - - AA22 668 VCCO 3 P130 3 - T15 W21 671 VCCO Bank 3* - I/O VCCO Bank 3* GND - - GND* GND* - VCCO 2 P130 3 P109 M13 U20 674 VCCO Bank 2* - I/O VCCO Bank 2* GND - P131 GND* GND* - Module 4 of 4 18 TRDY(1) www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S150 Device Pinouts (Continued) XC2S150 Pad Name XC2S150 Device Pinouts (Continued) Bank PQ208 FG256 FG456 Bndry Scan I/O, IRDY(1) 2 P132 H16 L20 767 I/O 2 P133 H14 L17 Function XC2S150 Pad Name Bank PQ208 FG256 FG456 Bndry Scan I/O 2 - - C22 866 770 I/O (DIN, D0) 2 P153 D14 D20 869 Function I/O 2 - - L18 773 P154 C15 C21 872 2 P134 H15 L21 776 I/O (DOUT, BUSY) 2 I/O I/O 2 - J13 L22 779 CCLK 2 P155 D15 B22 875 I/O (D3) 2 P135 G16 K20 782 VCCO 2 P156 VCCO Bank 2* VCCO Bank 2* - I/O, VREF 2 P136 H13 K21 785 P156 - VCCO Bank 2* VCCO Bank 2* - VCCO Bank 1* VCCO Bank 1* - 2 VCCO 1 VCCO TDO 2 P157 B14 A21 - GND - P137 GND* GND* - GND - P158 GND* GND* - I/O 2 P138 G14 K22 788 TDI - P159 A15 B20 - I/O 2 P139 G15 J21 791 I/O 2 - - J20 797 I/O 2 P140 G12 J18 800 I/O 2 - F16 J22 803 I/O 2 - - J19 806 I/O 2 P141 G13 H19 812 I/O (D2) 2 P142 F15 H20 815 VCCINT - P143 VCCINT* VCCINT* - VCCO 2 P144 VCCO Bank 2* VCCO Bank 2* - GND - P145 GND* GND* I/O (D1) 2 P146 E16 H22 I/O (CS) 1 P160 B13 C19 0 I/O (WRITE) 1 P161 C13 A20 3 I/O 1 - - B19 6 I/O 1 - - C18 9 I/O 1 - C12 D17 12 GND - - GND* GND* - I/O 1 P162 A14 A19 15 I/O 1 - - B18 18 I/O 1 - - E16 21 - I/O 1 - D12 C17 24 818 I/O 1 P163 B12 D16 27 - - GND* GND* - I/O, VREF 2 P147 F14 H18 821 GND I/O 2 - - G21 824 VCCO 1 - VCCO Bank 1* VCCO Bank 1* - I/O 2 P148 D16 G18 827 I/O 2 - F12 G20 830 I/O 2 - - G19 833 I/O 2 - - F22 836 I/O 2 P149 E15 F19 839 I/O, VREF 2 P150 F13 F21 842 VCCO 2 - VCCO Bank 2* VCCO Bank 2* - GND - - GND* GND* - I/O 2 P151 E14 F20 I/O 2 - C16 I/O 2 - - I/O 2 - I/O 2 P152 GND - - I/O 2 I/O 2 I/O, VREF 1 P164 C11 A18 30 I/O 1 P165 A13 B17 33 I/O 1 - - E15 36 I/O 1 - - A17 39 I/O 1 - D11 D15 42 I/O 1 P166 A12 C16 45 I/O 1 - - D14 48 I/O, VREF 1 P167 E11 E14 51 845 I/O 1 P168 B11 A16 54 F18 848 GND - P169 GND* GND* - E22 851 VCCO 1 P170 VCCO Bank 1* VCCO Bank 1* - - E21 854 P171 857 VCCINT* VCCINT* - D22 VCCINT - E13 I/O 1 P172 A11 C15 57 GND* GND* - I/O 1 P173 C10 B15 60 - B16 E20 860 I/O 1 - - A15 66 - - D21 863 I/O 1 - - F12 69 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 19 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S150 Device Pinouts (Continued) XC2S150 Pad Name XC2S150 Device Pinouts (Continued) Bank PQ208 FG256 FG456 Bndry Scan I/O 1 P174 B10 C14 72 I/O 1 - - B14 75 I/O 1 P175 D10 D13 81 I/O 1 P176 A10 C13 84 GND - P177 GND* GND* VCCO 1 - VCCO Bank 1* Function XC2S150 Pad Name Bank PQ208 FG256 FG456 Bndry Scan VCCINT - P196 VCCINT* VCCINT* - VCCO 0 P197 VCCO Bank 0* VCCO Bank 0* - GND - P198 GND* GND* - - I/O 0 P199 A5 B7 161 VCCO Bank 1* - I/O, VREF 0 P200 C6 E8 164 I/O 0 - - D8 167 Function I/O, VREF 1 P178 B9 B13 87 I/O 0 P201 B5 C7 170 I/O 1 P179 E10 E12 90 I/O 0 - D6 D7 173 I/O 1 - A9 B12 93 I/O 0 - - B6 176 I/O 1 P180 D9 D12 96 I/O 0 - - A5 179 I/O 1 - - C12 99 I/O 0 P202 A4 D6 182 I/O 1 P181 A8 D11 102 I/O, VREF 0 P203 B4 C6 185 I, GCK2 1 P182 C9 A11 108 VCCO 0 - - P183 GND* GND* - VCCO Bank 0* - GND VCCO Bank 0* VCCO 1 P184 VCCO Bank 1* VCCO Bank 1* - GND - - GND* GND* - I/O 0 P204 E6 B5 188 VCCO Bank 0* VCCO Bank 0* - I/O 0 - D5 E7 191 I/O 0 - - A4 194 VCCO 0 P184 I, GCK3 0 P185 B8 C11 109 I/O 0 - - E6 197 VCCINT - P186 VCCINT* VCCINT* - I/O 0 P205 A3 B4 200 I/O 0 - - E11 116 GND - - GND* GND* - I/O 0 P187 A7 A10 119 I/O 0 - C5 A3 203 I/O 0 - D8 B10 122 I/O 0 - - B3 206 I/O 0 P188 A6 C10 125 I/O 0 - - D5 209 I/O, VREF 0 P189 B7 A9 128 I/O 0 P206 B3 C5 212 VCCO 0 - VCCO Bank 0* VCCO Bank 0* - TCK - P207 C4 C4 - GND - P190 GND* GND* - VCCO 0 P208 VCCO Bank 0* VCCO Bank 0* - I/O 0 P191 C8 B9 131 VCCO 7 P208 0 P192 D7 E10 134 VCCO Bank 7* VCCO Bank 7* - I/O I/O 0 - - D10 140 04/18/01 I/O 0 P193 E7 A8 143 I/O 0 - - D9 146 I/O 0 - - B8 149 I/O 0 P194 C7 E9 155 I/O 0 P195 B6 A7 158 Notes: 1. IRDY and TRDY can only be accessed when using Xilinx PCI cores. 2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*, VCCO Bank 2*, VCCO Bank 3*, V CCO Bank 4*, V CCO Bank 5*, VCCO Bank 6*, VCCO Bank 7* are internally bonded to independent ground or power planes within the package. Module 4 of 4 20 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables Additional XC2S150 Package Pins (Continued) Additional XC2S150 Package Pins FG456 PQ208 VCCINT Pins Not Connected Pins P55 P56 - - - - 11/02/00 FG256 VCCINT Pins C3 C14 D4 D13 E5 E12 M5 M12 N4 N13 P3 P14 VCCO Bank 0 Pins E8 F8 - - - F9 - - - H12 - - - J12 - - - M9 - - - M8 - - - J6 - - - H6 - - - A16 B2 B15 F6 F7 F11 G6 G7 G8 G9 G10 G11 H7 H8 H9 H10 J7 J8 J9 J10 K6 K7 K8 K9 K10 K11 L6 L7 L10 L11 R2 R15 T1 T16 Not Connected Pins P4 R4 - - G16 H7 H16 P7 P16 R7 R16 T7 T8 T9 T14 T15 T16 U6 U17 V5 V18 - - F7 F8 G10 G11 F13 F14 G12 G13 K17 L16 R17 T17 U15 U16 U9 U10 R6 T6 K7 L7 C3 C20 VCCO BANK 0 Pins - F9 F10 VCCO Bank 1 Pins F15 F16 VCCO Bank 2 Pins G17 H17 M16 N16 T12 T13 J17 K16 VCCO Bank 3 Pins N17 P17 VCCO Bank 4 Pins U13 U14 VCCO Bank 5 Pins T10 T11 M7 N6 G6 H6 U7 U8 VCCO Bank 6 Pins N7 P6 VCCO Bank 7 Pins J6 K6 GND Pins A1 F10 11/02/00 G15 J16 - GND Pins A1 G14 J7 - VCCO Bank 7 Pins H5 G9 - VCCO Bank 6 Pins J5 G8 - VCCO Bank 5 Pins L8 G7 - VCCO Bank 4 Pins L9 F17 - VCCO Bank 3 Pins J11 F6 - VCCO Bank 2 Pins H11 E18 - VCCO Bank 1 Pins E9 E5 A22 B2 B21 J9 J10 J11 J12 J13 J14 K9 K10 K11 K12 K13 K14 L9 L10 L11 L12 L13 L14 M9 M10 M11 M12 M13 M14 N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 Y3 Y20 AA2 AA21 AB1 AB22 B11 Not Connected Pins A2 A6 A12 A13 A14 B16 C2 C8 C9 D1 D4 D18 D19 E13 E17 E19 F11 G2 G22 H21 J1 J4 K2 K18 K19 L2 L19 M2 M17 M21 N1 P1 P5 P22 R3 R20 R22 U3 U18 V6 W4 W13 W15 W19 Y5 Y22 AA1 AA3 AA9 AA10 AA11 AA16 AB7 AB8 AB12 AB14 AB21 - - 11/02/00 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 21 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S200 Device Pinouts (Continued) XC2S200 Device Pinouts XC2S200 Pad Name Bank PQ208 FG256 FG456 Bndry Scan GND - P1 GND* GND* - TMS - P2 D3 D3 - I/O 7 P3 C2 B1 257 Function I/O 7 - - E4 263 I/O 7 - - C1 266 I/O 7 - A2 F5 269 GND - - GND* GND* - I/O, VREF 7 P4 B1 D2 272 I/O 7 - - E3 275 I/O 7 - - F4 281 GND - - GND* GND* - I/O 7 - E3 G5 284 I/O 7 P5 D2 F3 287 GND - - GND* GND* - VCCO 7 - VCCO Bank 7* VCCO Bank 7* - I/O, VREF 7 P6 C1 E2 290 I/O 7 P7 F3 E1 293 I/O 7 - - G4 296 I/O 7 - - G3 299 I/O 7 - E2 H5 302 GND - - GND* GND* - I/O 7 P8 E4 F2 305 I/O 7 - - F1 308 I/O, VREF 7 P9 D1 H4 I/O 7 P10 E1 GND - P11 GND* VCCO 7 P12 VCCO Bank 7* VCCINT - P13 I/O 7 I/O XC2S200 Pad Name Function Bank PQ208 FG256 FG456 VCCO 7 - VCCO Bank 7* VCCO Bank 7* Bndry Scan - I/O, VREF 7 P20 H3 K3 350 I/O 7 P21 G4 K4 353 I/O 7 - - K2 359 I/O 7 - H2 L6 362 I/O 7 P22 G5 L1 365 I/O 7 - - L5 368 I/O 7 P23 H4 L4 374 I/O, IRDY(1) 7 P24 G1 L3 377 GND - P25 GND* GND* - VCCO 7 P26 VCCO Bank 7* VCCO Bank 7* - VCCO 6 P26 VCCO Bank 6* VCCO Bank 6* - I/O, TRDY(1) 6 P27 J2 M1 380 VCCINT - P28 VCCINT* VCCINT* - I/O 6 - - M6 389 I/O 6 P29 H1 M3 392 I/O 6 - J4 M4 395 I/O 6 - - N1 398 I/O 6 P30 J1 M5 404 I/O, VREF 6 P31 J3 N2 407 VCCO 6 - VCCO Bank 6* VCCO Bank 6* - 314 GND - P32 GND* GND* - G1 317 I/O 6 P33 K5 N3 410 GND* - I/O 6 P34 K2 N4 413 VCCO Bank 7* - I/O 6 - - P1 416 I/O 6 - - N5 419 VCCINT* VCCINT* - I/O 6 P35 K1 P2 422 P14 F2 H3 320 7 P15 G3 H2 323 I/O 7 - - J4 326 I/O 7 - - H1 329 I/O 7 - F1 J5 332 GND - - GND* GND* - I/O 7 P16 F4 J2 335 I/O 7 - - J3 338 I/O 7 - - J1 341 I/O 7 P17 F5 K5 I/O 7 P18 G2 K1 GND - P19 GND* GND* - Module 4 of 4 22 GND - - GND* GND* - I/O 6 - K3 P4 425 I/O 6 - - R1 428 I/O 6 - - P5 431 I/O 6 P36 L1 P3 434 I/O 6 P37 L2 R2 437 VCCINT - P38 VCCINT* VCCINT* - VCCO 6 P39 VCCO Bank 6* VCCO Bank 6* - 344 GND - P40 GND* GND* - 347 I/O 6 P41 K4 T1 440 I/O, VREF 6 P42 M1 R4 443 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S200 Device Pinouts (Continued) XC2S200 Pad Name XC2S200 Device Pinouts (Continued) Bank PQ208 FG256 FG456 Bndry Scan I/O 6 - - T2 449 I/O 6 P43 L4 U1 452 GND - - GND* GND* - Function XC2S200 Pad Name Function Bndry Scan Bank PQ208 FG256 FG456 VCCO 5 - VCCO Bank 5* VCCO Bank 5* - I/O, VREF 5 P59 T4 AA5 545 5 P60 M6 AB5 548 I/O 6 - M2 R5 455 I/O I/O 6 - - V1 458 I/O 5 - - V8 551 I/O 6 - - T5 461 I/O 5 - - AA6 554 I/O 6 P44 L3 U2 464 I/O 5 - T5 AB6 557 I/O, VREF 6 P45 N1 T3 467 GND - - GND* GND* - I/O 5 P61 N6 AA7 560 I/O 5 - - W7 563 I/O, VREF 5 P62 R5 W8 569 5 P63 P6 Y8 572 VCCO 6 - VCCO Bank 6* VCCO Bank 6* - GND - - GND* GND* - I/O 6 P46 P1 T4 470 I/O I/O 6 - L5 W1 473 GND - P64 GND* GND* - GND - - GND* GND* - VCCO 5 P65 6 - - V2 476 VCCO Bank 5* - I/O VCCO Bank 5* I/O 6 - - U4 482 VCCINT - P66 VCCINT* VCCINT* - I/O, VREF 6 P47 N2 Y1 485 I/O 5 P67 R6 AA8 575 GND - - GND* GND* - I/O 5 P68 M7 V9 578 5 - - AB8 581 I/O 6 - M4 W2 488 I/O I/O 6 - - V3 491 I/O 5 - - W9 584 I/O 6 - - V4 494 I/O 5 - - AB9 587 I/O 6 P48 R1 Y2 500 GND - - GND* GND* - I/O 6 P49 M3 W3 503 I/O 5 P69 N7 Y9 590 5 - - V10 593 M1 - P50 P2 U5 506 I/O GND - P51 GND* GND* - I/O 5 - - AA9 596 M0 - P52 N3 AB2 507 I/O 5 P70 T6 W10 599 VCCO 6 P53 VCCO Bank 6* VCCO Bank 6* - I/O 5 P71 P7 AB10 602 GND - P72 GND* GND* - VCCO 5 P53 VCCO Bank 5* VCCO Bank 5* - VCCO 5 - VCCO Bank 5* VCCO Bank 5* - M2 - P54 R3 Y4 508 I/O, VREF 5 P73 P8 Y10 605 I/O 5 - - W5 518 I/O 5 P74 R7 V11 608 I/O 5 - - AB3 521 I/O 5 - - AA10 614 I/O 5 - N5 V7 524 I/O 5 - T7 W11 617 GND - - GND* GND* - I/O 5 P75 T8 AB11 620 I/O, VREF 5 P57 T2 Y6 527 I/O 5 - - U11 623 I/O 5 - - AA4 530 VCCINT - P76 VCCINT* VCCINT* - I/O 5 - - AB4 536 I, GCK1 5 P77 R8 Y11 635 I/O 5 - P5 W6 539 VCCO 5 P78 5 P58 T3 Y7 542 VCCO Bank 5* - I/O VCCO Bank 5* GND - - GND* GND* - VCCO 4 P78 VCCO Bank 4* VCCO Bank 4* - GND - P79 GND* GND* - DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 4 of 4 23 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S200 Device Pinouts (Continued) XC2S200 Pad Name XC2S200 Device Pinouts (Continued) Bank PQ208 FG256 FG456 Bndry Scan I, GCK0 4 P80 N8 W12 636 I/O 4 P81 N9 U12 Function XC2S200 Pad Name Bank PQ208 FG256 FG456 Bndry Scan I/O 4 - - W17 739 640 I/O, VREF 4 P100 R13 AB20 742 Function I/O 4 - - V12 646 GND - - GND* GND* - I/O 4 P82 R9 Y12 649 I/O 4 - P12 AA19 745 I/O 4 - N10 AA12 652 I/O 4 - - V17 748 I/O 4 - - W13 655 I/O 4 - - Y18 751 I/O 4 P83 T9 AB13 661 I/O 4 P101 P13 AA20 757 I/O 4 P102 T14 W18 760 GND - P103 GND* GND* - DONE 3 P104 R14 Y19 763 VCCO 4 P105 VCCO Bank 4* VCCO Bank 4* - VCCO 3 P105 VCCO Bank 3* VCCO Bank 3* - I/O, VREF 4 P84 P9 AA13 664 VCCO 4 - VCCO Bank 4* VCCO Bank 4* - GND - P85 GND* GND* - I/O 4 P86 M10 Y13 667 I/O 4 P87 R10 V13 670 I/O 4 - - AB14 673 I/O 4 - - W14 676 PROGRAM - P106 P15 W20 766 I/O 4 P88 P10 AA14 679 I/O (INIT) 3 P107 N15 V19 767 GND - - GND* GND* - I/O (D7) 3 P108 N14 Y21 770 I/O 4 - - V14 682 I/O 3 - - V20 776 3 - - AA22 779 I/O 4 - - Y14 685 I/O I/O 4 - - W15 688 I/O 3 - T15 W21 782 I/O 4 P89 T10 AB15 691 GND - - GND* GND* - I/O 4 P90 R11 AA15 694 I/O, VREF 3 P109 M13 U20 785 VCCINT - P91 VCCINT* VCCINT* - I/O 3 - - U19 788 I/O 3 - - V21 794 GND - - GND* GND* - VCCO 4 P92 VCCO Bank 4* VCCO Bank 4* - GND - P93 GND* GND* - I/O 3 - R16 T18 797 I/O 4 P94 M11 Y15 697 I/O 3 P110 M14 W22 800 I/O, VREF 4 P95 T11 AB16 700 GND - - GND* GND* - I/O 4 - - AB17 706 VCCO 3 - 4 P96 N11 V15 709 VCCO Bank 3* - I/O VCCO Bank 3* GND - - GND* GND* - I/O, VREF 3 P111 L14 U21 803 I/O 4 - R12 Y16 712 I/O 3 P112 M15 T20 806 I/O 4 - - AA17 715 I/O 3 - - T19 809 3 - - V22 812 I/O 4 - - W16 718 I/O I/O 4 P97 P11 AB18 721 I/O 3 - L12 T21 815 I/O, VREF 4 P98 T12 AB19 724 GND - - GND* GND* - VCCO 4 - VCCO Bank 4* VCCO Bank 4* - I/O 3 P113 P16 R18 818 I/O 3 - - U22 821 GND - - GND* GND* - I/O, VREF 3 P114 L13 R19 827 I/O 4 P99 T13 Y17 727 I/O (D6) 3 P115 N16 T22 830 I/O 4 - N12 V16 730 GND - P116 GND* GND* - I/O 4 - - AA18 733 Module 4 of 4 24 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S200 Device Pinouts (Continued) XC2S200 Pad Name XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Bank PQ208 FG256 FG456 Bndry Scan I/O 2 - - K18 929 I/O 2 - - J20 932 I/O 2 P140 G12 J18 935 GND - - GND* GND* - 836 I/O 2 - F16 J22 938 R22 839 I/O 2 - - J19 941 - P19 842 I/O 2 - - H21 944 - L16 P20 845 I/O 2 P141 G13 H19 947 - - GND* GND* - I/O (D2) 2 P142 F15 H20 950 I/O 3 P121 K13 P21 848 VCCINT - P143 VCCINT* VCCINT* - I/O 3 - - N19 851 VCCO 2 P144 3 - - P22 854 VCCO Bank 2* VCCO Bank 2* - I/O I/O 3 P122 L15 N18 857 GND - P145 GND* GND* - I/O 3 P123 K12 N20 860 I/O (D1) 2 P146 E16 H22 953 GND - P124 GND* GND* - I/O, VREF 2 P147 F14 H18 956 VCCO 3 - VCCO Bank 3* VCCO Bank 3* - I/O 2 - - G21 962 I/O 2 P148 D16 G18 965 I/O, VREF 3 P125 K16 N21 863 GND - - GND* GND* - I/O (D4) 3 P126 J16 N22 866 I/O 2 - F12 G20 968 I/O 3 - - M17 872 I/O 2 - - G19 971 I/O 3 - J14 M19 875 I/O 2 - - F22 974 I/O 3 P127 K15 M20 878 I/O 2 P149 E15 F19 977 I/O 3 - - M18 881 I/O, VREF 2 P150 F13 F21 980 VCCINT - P128 VCCINT* VCCINT* - 2 - 3 P129 J15 M22 890 VCCO Bank 2* VCCO Bank 2* - I/O, TRDY(1) VCCO VCCO 3 P130 VCCO Bank 3* VCCO Bank 3* - GND - - GND* GND* - I/O 2 P151 E14 F20 983 VCCO 2 P130 VCCO Bank 2* VCCO Bank 2* - I/O 2 - C16 F18 986 GND - - GND* GND* - I/O 2 - - E22 989 I/O 2 - - E21 995 I/O, VREF 2 P152 E13 D22 998 Function Bndry Scan Bank PQ208 FG256 FG456 VCCO 3 P117 VCCO Bank 3* VCCO Bank 3* - VCCINT - P118 VCCINT* VCCINT* - I/O (D5) 3 P119 M16 R21 833 I/O 3 P120 K14 P18 I/O 3 - - I/O 3 - I/O 3 GND GND - P131 GND* GND* - I/O, IRDY(1) 2 P132 H16 L20 893 I/O 2 P133 H14 L17 896 I/O 2 - - L18 902 I/O 2 P134 H15 L21 905 I/O 2 - J13 L22 908 I/O 2 - - K19 911 I/O (D3) 2 P135 G16 K20 917 I/O, VREF 2 P136 H13 K21 920 VCCO 2 - VCCO Bank 2* VCCO Bank 2* - GND - P137 GND* GND* - I/O 2 P138 G14 K22 923 I/O 2 P139 G15 J21 926 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification Function GND - - GND* GND* - I/O 2 - B16 E20 1001 I/O 2 - - D21 1004 I/O 2 - - C22 1007 I/O (DIN, D0) 2 P153 D14 D20 1013 I/O (DOUT, BUSY) 2 P154 C15 C21 1016 CCLK 2 P155 D15 B22 1019 VCCO 2 P156 VCCO Bank 2* VCCO Bank 2* - www.xilinx.com 1-800-255-7778 Module 4 of 4 25 R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S200 Device Pinouts (Continued) XC2S200 Pad Name XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Bank PQ208 FG256 FG456 Bndry Scan I/O 1 P175 D10 D13 90 I/O 1 P176 A10 C13 93 GND - P177 GND* GND* - VCCO 1 - VCCO Bank 1* VCCO Bank 1* - 0 I/O, VREF 1 P178 B9 B13 96 3 I/O 1 P179 E10 E12 99 B19 9 I/O 1 - - A13 105 C18 12 I/O 1 - A9 B12 108 D17 15 I/O 1 P180 D9 D12 111 GND* GND* - I/O 1 - - C12 114 P162 A14 A19 18 I/O 1 P181 A8 D11 120 1 - - B18 21 I, GCK2 1 P182 C9 A11 126 1 - - E16 27 GND - P183 GND* GND* - I/O 1 - D12 C17 30 VCCO 1 P184 1 P163 B12 D16 33 VCCO Bank 1* - I/O VCCO Bank 1* GND - - GND* GND* - VCCO 0 P184 VCCO Bank 0* VCCO Bank 0* - VCCO 1 - VCCO Bank 1* VCCO Bank 1* - I, GCK3 0 P185 B8 C11 127 I/O, VREF 1 P164 C11 A18 36 VCCINT - P186 VCCINT* VCCINT* - I/O 1 P165 A13 B17 39 I/O 0 - - E11 137 I/O 1 - - E15 42 I/O 0 P187 A7 A10 140 I/O 1 - - A17 45 I/O 0 - D8 B10 143 0 - - F11 146 Function Bndry Scan Bank PQ208 FG256 FG456 VCCO 1 P156 VCCO Bank 1* VCCO Bank 1* - TDO 2 P157 B14 A21 - GND - P158 GND* GND* - TDI - P159 A15 B20 - I/O (CS) 1 P160 B13 C19 I/O (WRITE) 1 P161 C13 A20 I/O 1 - - I/O 1 - - I/O 1 - C12 GND - - I/O, VREF 1 I/O I/O Function I/O 1 - D11 D15 48 I/O GND - - GND* GND* - I/O 0 P188 A6 C10 152 I/O 1 P166 A12 C16 51 I/O, VREF 0 P189 B7 A9 155 I/O 1 - - D14 54 VCCO 0 - VCCO Bank 0* VCCO Bank 0* - I/O, VREF 1 P167 E11 E14 60 GND - P190 GND* GND* - I/O 1 P168 B11 A16 63 I/O 0 P191 C8 B9 158 GND - P169 GND* GND* - I/O 0 P192 D7 E10 161 VCCO 1 P170 VCCO Bank 1* VCCO Bank 1* - I/O 0 - - C9 164 0 - - D10 167 VCCINT - P171 VCCINT* VCCINT* - I/O I/O 1 P172 A11 C15 66 I/O 0 P193 E7 A8 170 I/O 1 P173 C10 B15 69 GND - - GND* GND* - I/O 1 - - E13 72 I/O 0 - - D9 173 I/O 1 - - A15 75 I/O 0 - - B8 176 I/O 1 - - F12 78 I/O 0 - - C8 179 0 P194 C7 E9 182 GND - - GND* GND* - I/O I/O 1 P174 B10 C14 81 I/O 0 P195 B6 A7 185 I/O 1 - - B14 84 VCCINT - P196 VCCINT* VCCINT* - I/O 1 - - A14 87 VCCO 0 P197 VCCO Bank 0* VCCO Bank 0* - Module 4 of 4 26 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: Pinout Tables XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function GND Additional XC2S200 Package Pins Bank PQ208 FG256 FG456 Bndry Scan - P198 GND* GND* - I/O 0 P199 A5 PQ208 Not Connected Pins P55 B7 188 11/02/00 FG256 P56 - - - - I/O, VREF 0 P200 C6 E8 191 I/O 0 - - D8 197 I/O 0 P201 B5 C7 200 C3 C14 D4 D13 E5 E12 GND - - GND* GND* - M5 M12 N4 N13 P3 P14 I/O 0 - D6 D7 203 I/O 0 - - B6 206 - - I/O 0 - - A5 209 I/O 0 P202 A4 D6 212 - - I/O, VREF 0 P203 B4 C6 215 VCCO 0 - VCCO Bank 0* VCCO Bank 0* - - - GND - - GND* GND* - - - I/O 0 P204 E6 B5 218 I/O 0 - D5 E7 221 - - I/O 0 - - A4 224 I/O 0 - - E6 230 - - I/O, VREF 0 P205 A3 B4 233 GND - - GND* GND* - - - I/O 0 - C5 A3 236 I/O 0 - - B3 239 - - I/O 0 - - D5 242 I/O 0 P206 B3 C5 248 F7 TCK - P207 C4 C4 - VCCO 0 P208 VCCO Bank 0* VCCO Bank 0* - VCCO 7 P208 VCCO Bank 7* VCCO Bank 7* - 04/18/01 Notes: 1. IRDY and TRDY can only be accessed when using Xilinx PCI cores. 2. Pads labelled GND*, VCCINT*, V CCO Bank 0*, VCCO Bank 1*, VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*, VCCO Bank 6*, VCCO Bank 7* are internally bonded to independent ground or power planes within the package. DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification VCCINT Pins VCCO Bank 0 Pins E8 F8 - - VCCO Bank 1 Pins E9 F9 - - VCCO Bank 2 Pins H11 H12 - - VCCO Bank 3 Pins J11 J12 L9 M9 - - VCCO Bank 4 Pins - - VCCO Bank 5 Pins L8 M8 - - VCCO Bank 6 Pins J5 J6 - - VCCO Bank 7 Pins H5 H6 - - GND Pins A1 A16 B2 B15 F6 F10 F11 G6 G7 G8 G9 G10 G11 H7 H8 H9 H10 J7 J8 J9 J10 K6 K7 K8 K9 K10 K11 L6 L7 L10 L11 R2 R15 T1 T16 P4 R4 - - Not Connected Pins - - 11/02/00 www.xilinx.com 1-800-255-7778 Module 4 of 4 27 R Spartan-II 2.5V FPGA Family: Pinout Tables Additional XC2S200 Package Pins (Continued) Additional XC2S200 Package Pins (Continued) GND Pins FG456 VCCINT Pins A1 A22 B2 B21 C3 C20 E5 E18 F6 F17 G7 G8 J9 J10 J11 J12 J13 J14 G9 G14 G15 G16 H7 H16 K9 K10 K11 K12 K13 K14 J7 J16 P7 P16 R7 R16 L9 L10 L11 L12 L13 L14 M10 M11 M12 M13 M14 T7 T8 T9 T14 T15 T16 M9 U6 U17 V5 V18 - - N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 G11 Y3 Y20 AA2 AA21 AB1 AB22 G13 A2 A6 A12 B11 B16 C2 D1 D4 D18 D19 E17 E19 G2 G22 L2 L19 M2 M21 R3 R20 U3 U18 V6 W4 VCCO BANK 0 Pins F7 F8 F9 F10 G10 Not Connected Pins VCCO Bank 1 Pins F13 F14 F15 F16 G12 VCCO Bank 2 Pins G17 H17 J17 K16 K17 L16 VCCO Bank 3 Pins M16 N16 N17 P17 R17 T17 VCCO Bank 4 Pins T12 T13 U13 U14 U15 U16 U9 U10 R6 T6 K7 L7 W19 Y5 Y22 AA1 AA3 AA11 AA16 AB7 AB12 AB21 - - 11/02/00 VCCO Bank 5 Pins T10 T11 U7 U8 VCCO Bank 6 Pins M7 N6 N7 P6 VCCO Bank 7 Pins G6 H6 J6 K6 Revision History Version No. Date Description 2.0 09/18/00 Sectioned the Spartan-II Family data sheet into four modules. Corrected all known errors in the pinout tables. 2.1 10/04/00 2.2 11/02/00 Added notes requiring PWDN to be tied to V CCINT when unused. Removed the Power Down feature. 2.3 03/05/01 Added notes on pinout tables for IRDY and TRDY. 2.4 04/30/01 Reinstated XC2S50 V CCO Bank 7, GND, and "not connected" pins missing in version 2.3. The Spartan-II Family Data Sheet DS001-1, Spartan-II 2.5V FPGA Family: Introduction and Ordering Information (Module 1) DS001-2, Spartan-II 2.5V FPGA Family: Functional Description (Module 2) DS001-3, Spartan-II 2.5V FPGA Family: DC and Switching Characteristics (Module 3) DS001-4, Spartan-II 2.5V FPGA Family: Pinout Tables (Module 4) Module 4 of 4 28 www.xilinx.com 1-800-255-7778 DS001-4 (v2.4) April 30, 2001 Preliminary Product Specification