1. General description
The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General
Purpose parallel Inpu t/O ut pu t (GPIO) expansion for I2C-bus/SMBus applications and
were developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders.
The improvements include higher drive cap ability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O
expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push buttons, LEDs, fans, etc.
The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output
selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity
Inversion register (active HIGH or active LOW operation). The system master can enable
the I/Os as either inpu ts or outputs by writing to the I/O con fig ur at ion bits. The data for
each input or output is kept in the corresponding Inp ut Port or Output Port register. The
polarity of the read register can be inverted with the Polarity Inversion register. All
registers can be read by the system master. Although pin-to-pin and I2C-bus address
compatible with the PCF8574 series, software changes are required due to the
enhancem en ts and are dis cus se d in A pplication Note AN469.
The PCA9554/PCA9554A open-drain interrupt output is activated when any input state
differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address an d allo w up to eigh t
devices to share the same I2C-bus/SMBus. The PCA9554A is identical to the PCA9554
except that the fixed I2C-bus address is different allowing up to sixteen of these devices
(eight of each) on the same I2C-bus/SMBus.
2. Features and benefits
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power- on res et
8 I/O pins which default to 8 inputs
0 Hz to 400 kHz clock frequency
PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Rev. 8 — 26 July 2011 Product data sheet
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 2 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
AEC-Q100 compliance available
Packages offered: DIP16, SO16, SSOP16, SSOP20, TSSOP16,
HVQFN16 (2 versions: 4 40.85 mm and 3 30.85 mm), and bare die
3. Ordering information
[1] PCA9554PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.
Table 1. Ordering information
Tamb =
40
Cto+85
C.
Type number Topside mark Package
Name Description Version
PCA9554N PCA9554N DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
PCA9554AN PCA9554AN
PCA9554D PCA9554D SO16 plastic small outline package; 16 leads;
body width 7.5 mm SOT162-1
PCA9554AD PCA9554AD
PCA9554DB 9554DB SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
PCA9554ADB 9554A
PCA9554TS PCA9554 SSOP20 plastic shrink small outline package; 20 leads;
body width 4.4 mm SOT266-1
PCA9554ATS PA9554A
PCA9554PW 9554DH TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
PCA9554PW/Q900[1] 9554DH
PCA9554APW 9554ADH
PCA9554BS 9554 HVQFN16 plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4 40.85 mm SOT629-1
PCA9554ABS 554A
PCA9554BS3 P54 HVQFN16 plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3 30.85 mm SOT758-1
PCA9554ABS3 54A
PCA9554U - bare die - -
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 3 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
4. Block diagram
All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9554/PCA9554A
PCA9554/PCA9554A
POWER-ON
RESET
002aac492
I2C-BUS/SMBus
CONTROL
INPUT
FILTER
SCL
SDA
VDD
INPUT/
OUTPUT
PORTS
IO0
VSS
8-bit
write pulse
read pulse
IO2
IO4
IO6
IO1
IO3
IO5
IO7
LP
FILTER
VDD
INT
A0
A1
A2
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 4 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
5. Pinning information
5.1 Pinning
Fig 2. Pin configuration for DIP16 Fig 3. Pin configuration for SO16
Fig 4. Pin configuration for SSOP16 Fig 5. Pin configuration for TSSOP16
PCA9554N
PCA9554AN
A0 VDD
A1 SDA
A2 SCL
IO0 INT
IO1 IO7
IO2 IO6
IO3 IO5
VSS IO4
002aac485
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
VDD
SDA
SCL
INT
IO7
IO6
IO5
IO4
A0
A1
A2
IO0
IO1
IO2
IO3
VSS
PCA9554D
PCA9554AD
002aac486
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
PCA9554DB
PCA9554ADB
002aac487
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15 VDD
SDA
SCL
INT
IO7
IO6
IO5
IO4
A0
A1
A2
IO0
IO1
IO2
IO3
VSS
V
DD
SDA
SCL
INT
IO7
IO6
IO5
IO4
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
PCA9554PW
PCA9554PW/Q900
PCA9554APW
002aac488
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 5 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Fig 6. Pin confi gura tio n for SSOP2 0
Fig 7. Pin configura tio n for HVQFN16
(SOT629-1) Fig 8. Pin configuration for HVQFN16
(SOT758-1)
PCA9554TS
PCA9554ATS
INT IO7
SCL IO6
n.c. n.c.
SDA IO5
VDD IO4
A0 VSS
A1 IO3
n.c. n.c.
A2 IO2
IO0 IO1
002aac489
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
002aac490
PCA9554BS
PCA9554ABS
Transparent top view
IO2 IO6
IO1 IO7
IO0 INT
A2 SCL
IO3
V
SS
IO4
IO5
A1
A0
V
DD
SDA
4 9
3 10
2 11
1 12
5
6
7
8
16
15
14
13
terminal 1
index area
002aac491
PCA9554BS3
PCA9554ABS3
Transparent top view
IO2 IO6
IO1 IO7
IO0
A2 SCL
IO3
VSS
IO4
IO5
A1
A0
VDD
SDA
4 9
3 10
2 11
1 12
5
6
7
8
16
15
14
13
terminal 1
index area
INT
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 6 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
5.2 Pin description
[1] HVQFN16 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
6. Functional description
Refer to Figure 1 “Block dia gram of PCA9554/PCA9554A.
6.1 Registers
6.1.1 Command byte
The command byte is the first byte to follow the address byte during a write tra nsmission.
It is used as a pointer to determine which of the following registers will be written or read.
Ta ble 2. Pin description
Symbol Pin Description
DIP16, SO16,
SSOP16, TSSOP16 HVQFN16 SSOP20
A0 1 15 6 address input 0
A1 2 16 7 address input 1
A2 3 1 9 address input 2
IO0 4 2 10 input/output 0
IO1 5 3 11 input/output 1
IO2 6 4 12 input/output 2
IO3 7 5 14 input/output 3
VSS 86
[1] 15 supply ground
IO4 9 7 16 input/output 4
IO5 10 8 17 input/output 5
IO6 11 9 19 input/output 6
IO7 12 10 20 input/output 7
INT 13 11 1 interrupt output (open-drain)
SCL 14 12 2 serial clock line
SDA 15 13 4 serial data line
VDD 16 14 5 supply voltage
n.c. - - 3, 8, 13, 18 not connected
Ta ble 3. Command by te
Command Protocol Function
0 read byte Input Port register
1 read/write byte Output Port register
2 read/write byte Polarity Inversion register
3 read/write byte Configuration register
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 7 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.1.2 Register 0 - Input Port register
This register is a read-only port. It refle cts the incomin g logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no
external signal externally applied because of the internal pull-up resistors.
6.1.3 Register 1 - Output Port register
This register reflect s the outgoi ng logic levels of the pins d efined as output s by Re gister 3.
Bit values in this register have no ef fect on pins defined as inp uts. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
Ta ble 4. Regist er 0 - Inpu t Port register bit description
Bit Symbol Access Value Description
7 I7 read only X determined by externally appli ed logic level
6 I6 read only X
5 I5 read only X
4 I4 read only X
3 I3 read only X
2 I2 read only X
1 I1 read only X
0 I0 read only X
Ta ble 5. Register 1 - Output Por t register bit description
Legend: * default value.
Bit Symbol Access Value Description
7 O7 R 1* reflects outgoing logic levels of pins defined as
outputs by Register 3
6O6 R 1*
5O5 R 1*
4O4 R 1*
3O3 R 1*
2O2 R 1*
1O1 R 1*
0O0 R 1*
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 8 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.1.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port dat a is inverted . If a bit in
this register is cleared (written with a ‘0’) , the Input Port data polarity is retained.
6.1.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver . If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, th e
I/Os are configured as inputs with a weak pull-up to VDD.
6.2 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the
PCA9554/PCA9554A in a reset condition until VDD has reached VPOR. At that point, the
reset condition is released and the PCA9554/PCA9554A registers and state machine will
initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the
device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
Ta ble 6. Regist er 2 - Pola rity Inversion register bit descrip tion
Legend: * default value.
Bit Symbol Access Value Description
7 N7 R/W 0* inverts polarity of Input Port register data
0 = Input Port register data retained (default value)
1 = Input Port register data inverted
6N6 R/W 0*
5N5 R/W 0*
4N4 R/W 0*
3N3 R/W 0*
2N2 R/W 0*
1N1 R/W 0*
0N0 R/W 0*
Table 7. Register 3 - Configura t ion register bit description
Legend: * default value.
Bit Symbol Access Value Description
7 C7 R/W 1* configures the directio ns of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
6C6 R/W 1*
5C5 R/W 1*
4C4 R/W 1*
3C3 R/W 1*
2C2 R/W 1*
1C1 R/W 1*
0C0 R/W 1*
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 9 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins change state and
the pin is configured as an input. The interrup t is deactivated when the input retu rns to its
previous state or the Input Port register is read.
Note that changing an I/O from and output to an inp ut may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 k typ.) to VDD. The input voltage may be
raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of th e Output Port register. Care should be exercised if an ex ternal volta ge is applied
to an I/O configured as an outp ut because of the low-impedance paths that exist between
the pin and either VDD or VSS.
Remark: At power-on reset, all registers return to default values.
Fig 9. Simplified schematic of IO0 to IO7
VDD
IO0 to IO7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity inversion
register data
002aac493
FF
data from
shift register
FF
FF
FF
Q1
Q2
VSS
to INT
100 kΩ
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 10 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.5 Device address
6.6 Bus transactions
Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown
in Figure 12 and Figure 13. Data is r ead from the PCA9554/PCA9554A registers using the
Read mode as shown in Figure 14 and Figure 15. These devices do not implement an
auto-increment function, so once a command byte has been sent, the register which was
addressed will continue to be accessed by reads until a new command byte has been
sent.
Fig 10. PCA9554 device address Fig 11. PCA9554A device address
002aac494
0 1 0 0 A2 A1 A0 R/W
fixed
slave address
hardware
selectable
002aac495
0 1 1 1 A2 A1 A0 R/W
fixed
slave address
programmable
Fig 12. Write to Outp ut Port re g is t er
Fig 13. Write to Configuration register or Polarity Inversion register
1 0 0 A2 A1 A0 0 AS0
START condition R/W
acknowledge
from slave
002aac473
A
acknowledge
from slave
SCL
SDA A
data to
register
P
987654321
command byte
acknowledge
from slave
data to register
DATA
slave address
0000011/00
STOP
condition
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 11 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Fig 14. Read from register
1 0 0 A2 A1 A0 0 AS0
START condition R/W
acknowledge
from slave
002aac474
A
acknowledge
from slave
SDA
A P
command byte
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.) 1 0 0 A2 A1 A0 1 A0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
Fig 15. Read Input Port register
1 0 0 A2 A1 A0 1 AS0
START condition R/W
acknowledge
from slave
002aac475
A
acknowledge
from master
SCL
SDA NA
read from
port
data into
port
P
th(D)
987654321
data from port
no acknowledge
from master
data from port
DATA 4
slave address
DATA 1
STOP
condition
DATA 2 DATA 3 DATA 4
tsu(D)
INT
tv(INT_N) trst(INT_N)
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 12 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
7. Application design-in information
8. Limiting values
Device address configured as 0100 100X for this example.
IO0, IO1, IO2 configured as outputs.
IO3, IO4, IO5 configured as inputs.
IO6 and IO7 are not used and must be configured as outputs.
Fig 16. Typical application
PCA9554
IO0
IO1
SCL
SDA
VDD
002aac496
SCL
SDA IO2
IO3
VDD
VSS
MASTER
CONTROLLER
VSS
VDD (5 V)
2 kΩ
SUBSYSTEM 1
(e.g., temp. sensor)
INT
SUBSYSTEM 2
(e.g., counter)
RESET
controlled switch
(e.g., CBT device)
A
B
enable
INTINT
10 kΩ10 kΩ
SUBSYSTEM 3
(e.g., alarm system)
ALARM
IO4
IO5
VDD
A2
A1
A0
IO6
IO7
10 kΩ10 kΩ
Ta ble 8. Limiting valu es
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +6.0 V
IIinput current - 20 mA
VI/O voltage on an input/output pin VSS 0.5 5.5 V
IO(IOn) output current on pin IOn - 50 mA
IDD supply current - 85 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature 65 +150 C
Tamb ambient temperature operating 40 +85 C
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 13 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
9. Static characteristics
Table 9. Static characteristics
VDD = 2.3 V to 5.5 V; VSS =0V; T
amb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD =5.5V;
no load; fSCL = 100 kHz - 104 175 A
Istb standby current Standby mode; VDD = 5.5 V; no load;
VI=V
SS; fSCL = 0 kHz; I/O = inputs - 550 700 A
Standby mode; VDD = 5.5 V; no load;
VI=V
DD; fSCL = 0 kHz; I/O = inputs -0.251 A
VPOR power-on reset voltage no load; VI=V
DD or VSS [1] - 1.5 1.65 V
Input SCL; input/outpu t S DA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -5.5V
IOL LOW-level output current VOL =0.4V 3 6 - mA
ILleakage current VI=V
DD =V
SS 1- +1 A
Ciinput capacitance VI=V
SS - 6 10 pF
I/Os
VIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL =0.5V; V
DD =2.3V [2] 810- mA
VOL =0.7V; V
DD =2.3V [2] 10 13 - mA
VOL =0.5V; V
DD =3.0V [2] 814- mA
VOL =0.7V; V
DD =3.0V [2] 10 19 - mA
VOL =0.5V; V
DD =4.5V [2] 817- mA
VOL =0.7V; V
DD =4.5V [2] 10 24 - mA
VOH HIGH-level output voltage IOH =8mA; V
DD =2.3V [3] 1.8 - - V
IOH =10 mA; VDD =2.3V [3] 1.7 - - V
IOH =8mA; V
DD =3.0V [3] 2.6 - - V
IOH =10 mA; VDD =3.0V [3] 2.5 - - V
IOH =8mA; V
DD =4.75V [3] 4.1 - - V
IOH =10 mA; VDD =4.75V [3] 4.0 - - V
ILI input leakage current VDD =3.6V; V
I=V
DD 1- +1 A
ILleakage current VDD =5.5V; V
I=V
SS --100 A
Ciinput capacitance - 3.7 5 pF
Cooutput capacitance - 3.7 5 pF
Interrupt INT
IOL LOW-level output current VOL =0.4V 3 - - mA
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 14 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
[1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
10. Dynamic characteristics
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.
[3] Cb= total capacitance of one bus line in pF.
Select inputs A0, A1, A2
VIL LOW-level input voltage 0.5 - 0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current 1- 1 A
Table 9. Static characteristics …continued
VDD = 2.3 V to 5.5 V; VSS =0V; T
amb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 10. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode I2C-bus Unit
Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition 4.7 - 1.3 - s
tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s
tSU;STA set-up time for a repeated START
condition 4.7 - 0.6 - s
tSU;STO set-up time for STOP condition 4.0 - 0.6 - s
tHD;DAT data hold time 0 - 0 - s
tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 s
tVD;DAT data valid time [2] 300 - 50 - ns
tSU;DAT data set-up time 250 - 100 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - s
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s
trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns
tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns
tSP pulse width of spikes that must be
suppressed by the input filter - 50 - 50 ns
Port timing
tv(Q) data output valid time - 200 - 200 ns
tsu(D) data input set-up time 100 - 100 - ns
th(D) data input hold time 1 - 1 - s
Interrupt timing
tv(INT_N) valid time on pin INT -4 - 4s
trst(INT_N) reset time on pin INT -4 - 4s
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 15 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Fig 17. Definition of timing
tSP
tBUF
tHD;STA PP S
tLOW
tr
tHD;DAT
tf
tHIGH tSU;DAT tSU;STA
Sr
tHD;STA
tSU;STO
SDA
SCL
002aaa986
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 16 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
11. Package outline
Fig 18. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 17 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Fig 19. Package outline SOT162-1 (SO16)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 10.5
10.1 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT162-1
8
16
wM
bp
D
detail X
Z
e
9
1
y
0.25
075E03 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.41
0.40 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
0 5 10 mm
scale
SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
99-12-27
03-02-19
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 18 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Fig 20. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 19 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Fig 21. Package outline SOT266-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
01.4
1.2 0.32
0.20 0.20
0.13 6.6
6.4 4.5
4.3 0.65 1 0.2
6.6
6.2 0.65
0.45 0.48
0.18 10
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
0.75
0.45
SOT266-1 MO-152 99-12-27
03-02-19
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
X
(A )
3
A
y
0.25
110
20 11
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1
A
max.
1.5
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 20 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Fig 22. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index