
PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 26 July 2011 14 of 30
NXP Semiconductors PCA9554; PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
[1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
10. Dynamic characteristics
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.
[3] Cb= total capacitance of one bus line in pF.
Select inputs A0, A1, A2
VIL LOW-level input voltage 0.5 - 0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current 1- 1 A
Table 9. Static characteristics …continued
VDD = 2.3 V to 5.5 V; VSS =0V; T
amb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 10. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode I2C-bus Unit
Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition 4.7 - 1.3 - s
tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s
tSU;STA set-up time for a repeated START
condition 4.7 - 0.6 - s
tSU;STO set-up time for STOP condition 4.0 - 0.6 - s
tHD;DAT data hold time 0 - 0 - s
tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 s
tVD;DAT data valid time [2] 300 - 50 - ns
tSU;DAT data set-up time 250 - 100 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - s
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s
trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns
tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns
tSP pulse width of spikes that must be
suppressed by the input filter - 50 - 50 ns
Port timing
tv(Q) data output valid time - 200 - 200 ns
tsu(D) data input set-up time 100 - 100 - ns
th(D) data input hold time 1 - 1 - s
Interrupt timing
tv(INT_N) valid time on pin INT -4 - 4s
trst(INT_N) reset time on pin INT -4 - 4s