SLUS542F - OCTOBER 2003 - REVISED JULY 2009 FEATURES D Low Output Jitter D Soft-Stop Shutdown of MAIN and AUX D Ideal for Active Clamp/Reset Forward, D D D D D D D D D DESCRIPTION The UCC2891/2/3/4 family of PWM controllers is designed to simplify implementation of the various active clamp/reset switching power topologies. Flyback Converters Provides Complementary Auxiliary Driver with Programmable Deadtime (Turn-On Delay) between AUX and MAIN Switches Peak Current-Mode Control with Cycle-by-Cycle Current Limiting 110-V Input Startup Regulator on UCC2891/3 TrueDrivet 2-A Sink, 2-A Source Outputs Accurate Line UV and Line OV Threshold Programmable Slope Compensation 1.0-MHz Synchronizable Oscillator Precise Programmable Maximum Duty Cycle Programmable Soft Start The UCC289x is a peak current-mode, fixedfrequency, high-performance pulse width modulator. It includes the logic and the drive capability for the auxiliary switch with a simple method of programming the critical delays for proper active clamp operation. The UCC2891/3 includes a 110-V start-up regulator for initial start-up and to provide keep-alive power during stand-by. Additional features include an internal programmable slope compensation circuit, precise DMAX limit, and a single resistor programmable synchronizable oscillator. An accurate line monitoring function also programs the converter's ON and OFF transitions with regard to the bulk input voltage. Along with the UCC2897, this UCC289x family allows the power supply designer to eliminate many of the external components, reducing the size and complexity of the design. APPLICATIONS D 150-W to 700-W SMPS D High-Efficiency, Low EMI/RFI Off-Line or D D DC/DC Converters Server, 48-V Telecom, Datacom High Power Adapter, LCD-TV and PDP-TV R DEL 1 UCC2891 VIN RDEL BIAS WINDING 2 RTON 3 RTOFF LINE UV 15 VDD 14 R OFF 4 VREF OUT SYNC 6 GND 7 CS 8 RSLOPE AUX 12 PGND 11 SS/SD FB D3 10 C CLAMP C AUX Q2 Co LOAD D1 D2 Q3 SR DRIVE R CS C SS D AUX SECONDARY SIDE E/A 9 R SLOPE D4 Q1 R OUT 13 C VREF 5 C BIAS Lo Q4 C BULK R ON CF +VIN 16 RF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* Copyright 2003 - 2009, Texas Instruments Incorporated www.ti.com 1 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Line input voltage, VIN Supply voltage, VDD (IDD < 10 mA) Analog inputs FB, CS, SYNC, LINEOV, LINEUV Output source current (peak), IO_SOURCE Output sink current (peak), IO_SINK 120 V 16.5 V -0.3 to (VREF + 0.3) not to exceed 6 V 2.5 OUT, AUX Operating junction temperature range, TJ -55 to 150 Storage temperature, Tstg -65 to 150 ESD rating A -2.5 Human body model, (HBM) 2000 Change device model (CDM) 500 C V Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds 300 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of, the specified terminal. RECOMMENDED OPERATING CONDITIONS MIN Line input voltage, VIN 18 Supply voltage, VDD 8.5 Supply bypass capacitance NOM 12.0 MAX UNIT 110 V 16.0 V F 1 Timing resistance, RON = ROFF (for 250-kHz operation) 75 k Operating junction temperature, TJ -40 105 C Reference bypass capacitance, CREF 0.1 1 F ORDERING INFORMATION PART NUMBERS TA APPLICATION AUX OUTPUT POLARITY DC-DC DC-DC/Sec. Side -40C to 125C P-Channel DC-DC Off-Line N-Channel CS THRESHOLD (INCLUDES SLOPE COMPENSATION) 110-V START-UP CIRCUIT SOIC-16 (D) TSSOP-16 (PW) 0.75 V Yes UCC2891D UCC2891PW 1.27 V No UCC2892D UCC2892PW 0.75 V Yes UCC2893D UCC2893PW 1.27 V No UCC2894D UCC2894PW The D and PW packages are available taped and reeled. Add R suffix to device type (e.g. UCC2891DR) to order quantities of 2,500 devices per reel (for the D package) and 2,000 devices per reel (for the PW package). Bulk quantities are 40 units per tube (for the D package) and 90 units per tube (for the PW package). 2 www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 THERMAL RESISTANCE INFORMATION PACKAGE THERMAL RESISTANCE SOIC-16 (D) TSSOP-16 (PW) jc 36.9 to 38.4 ja (0 LFM) 73.1 to 111.6 jc 33.6 to 35.0 ja (0 LFM) 108.4 to 147.0 UNITS C/W C/W PIN ASSIGNMENTS UCC2892 AND UCC2894 D AND PW PACKAGE (TOP VIEW) UCC2891 AND UCC2893 D and PW PACKAGEs (TOP VIEW) RTDEL RTON RTOFF VREF SYNC GND CS RSLOPE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RTDEL RTON RTOFF VREF SYNC GND CS RSLOPE VIN LINEUV VDD OUT AUX PGND SS/SD FB 1 2 3 4 5 6 7 8 LINEOV LINEUV VDD OUT AUX PGND SS/SD FB 16 15 14 13 12 11 10 9 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-F capacitor from VDD to GND, 0.01-F capacitor from VREF to GND, RON = ROFF = 75 k, RDEL = 10 k, RSLOPE = 50 k, -40 C TA = TJ 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERALL ISTARTUP Start-up current IDD Operating supply current(1)(2) VDD < VUVLO VFB = 0 V, VCS = 0 V, Outputs not switching 300 500 A 2 3 mA HIGH-VOLTAGE BIAS SECTION (UCC2891, UCC2893) IDD-ST VDD startup current IVIN JFET leakage current UNDERVOLTAGE LOCKOUT Current available from VDD during Startup, VIN = 36 V, TA = -40C to 85C (3) 4 11 VIN = 120 V; VDD = 14 V Start threshold voltage(1) mA 75 A 12.2 12.7 13.2 Minimum operating voltage after start 7.6 8.0 8.4 Hysteresis 4.4 4.7 5.0 Line UV and Line OV voltage threshold 1.243 1.268 1.293 V Line UV and Line OV hysteresis current 11.8 12.5 14.5 A V LINE MONITOR VLINEUV ILINEHYS SOFT-START ISS ISS Charge current Discharge current RTON = 75 k RTON = 75 k -10.5 -18.5 10.5 18.5 A A VSS/SD Discharge/shutdown threshold voltage 0.4 0.5 0.6 V (1) Set VDD above the start threshold before setting at 12 V. (2) Does not include current of the external oscillator network. (3) The power supply starts with IDD-ST load on VDD, part will start up with no load up to 125C. For more detailed information, see pin descriptions for VIN and VDD. (4) ISSC and ISS/SD are directly proportional to IRON. See equation 7. www.ti.com 3 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-F capacitor from VDD to GND, 0.01-F capacitor from VREF to GND, RON = ROFF = 75 k, RDEL = 10 k, RSLOPE = 50 k, -40 C TA = TJ 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Reference VREF TJ = 25C 0 A < IREF < 5 mA, 4.85 5.00 5.15 4.75 5.00 5.25 -20 -11 -8 FB = High -10% R CS R SLOPE +10% Oscillator frequency TJ = 25C 237 250 263 Total variation -40 C < TJ 125C; 8.5 V < 14.5 V 225 Reference voltage ISC Short circuit current INTERNAL SLOPE COMPENSATION m REF = 0 V, Slope(3) over temperature TJ = 25C V mA OSCILLATOR fOSC VP_P Oscillator amplitude (peak-to-peak) SYNCHRONIZATION VSYNCH tDEL 270 2 SYNC theshold voltage 1.6 SYNC-to-output delay 2.3 kHz V 3.0 50 V ns PWM Maximum duty cycle 66% 70% 74% 0.43 0.50 0.61 0.40 0.50 0.60 4.8 5.0 5.2 Minimum duty cycle 0% PWM offset CS = 0 V V CURRENT SENSE VLVL VERR(max) Current sense level shift voltage VCS Current sense threshold UCC2891 UCC2893 0.71 0.75 0.79 VCS Current sense threshold UCC2892 UCC2894 1.23 1.27 1.31 Maximum voltage error (clamped) (1) Set VDD above the start threshold before setting at 12 V. (2) Does not include current of the external oscillator network. 4 www.ti.com V SLUS542F - OCTOBER 2003 - REVISED JULY 2009 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-F capacitor from VDD to GND, 0.01-F capacitor from VREF to GND, RON = ROFF = 75 k, RDEL = 10 k, RSLOPE = 50 k, -40 C TA = TJ 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT (OUT AND AUX) tR tF Rise time CLOAD = 2 nF 19 28 Fall time CLOAD = 2 nF 14 23 tDEL1 tDEL2 Delay time (AUX to OUT) CLOAD = 2 nF, RDEL = 10 k 110 Delay time (OUT to AUX) CLOAD = 2 nF, RDEL = 10 k 115 IOUT(src) IOUT(sink) Output source current VOUT(low) VOUT(high) Low-level output voltage -2 Output sink current IOUT = 150 mA IOUT = -150 mA 50% 0.4 50% t 50% 50% (N-channel) 50% 50% (P-channel) tDEL1 V 11.1 OUT AUX A 2 High-level output voltage AUX ns t t tDEL2 Figure 1. Output Timing Diagram www.ti.com 5 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 FUNCTIONAL BLOCK DIAGRAM TYP: VREF = 5.0 V VREF 0.05 * IRDEL 1/2 x VREF 0.05 * IRDEL IRDEL RDEL 92/94 VREF CLOCK UV 1-DMAX OUT VDD 13 OUT 12 AUX 11 PGND 10 SS/SD + PWM OFF IRTON CT VDD 4 14 VDD OK 1.27 V VDD 1/2 x VREF VREF LINEUV 91/93 13 V/ 8 V 3 15 1.27 V + 2 RTOFF VIN (UCC2891/3) LINEOV (UCC2892/4) + OV 1 1/2 x VREF RTON 16 VREF SYNC IRDEL VDD OUT REF GEN PWM Offset 0.5 V + SYNC 5 S Q R Q TURN-ON DELAY + VREF 75k VREF 91/92 P-Ch. IRDEL VDD 5 * ISLOPE GND 6 CS 7 TURN-ON DELAY + 93/94 N-Ch. OV OFF 1-DMAX VREF UV OFF ISS = 0.43 x IRTON UCC2892/4 1.27 V UCC2891/3 0.75 V CT 3*R + VDD 2*R UV ISLOPE VREF OV RSLOPE 8 ENABLE 9 + 6 UVLO AND SS www.ti.com FB SLUS542F - OCTOBER 2003 - REVISED JULY 2009 TERMINAL FUNCTIONS TERMINAL UCC2891 UCC2893 UCC2892 UCC2894 I/O AUX 12 12 O This output drives the auxiliary clamp MOSFET which is turned on when the main PWM switching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-A source turn-on current and 2-A sink turn-off current. CS 7 7 I This pin is used to sense the peak current utilized for current mode control and for current limiting functions. The peak signal which can be applied to this pin before pulse-by-pulse current limiting activates is approximately 0.75 V for the UCC2891 and UCC2893 and 1.27 V for the UCC2892 and UCC2894. FB 9 9 I This pin is used to bring the error signal from an external optocoupler or error amplifier into the PWM control circuitry. Often, there is a resistor tied from FB to VREF, and an optocoupler is used to pull the control pin closer to GND to reduce the pulse width of the OUT output driving the main power switch of the converter. GND 6 6 - This pin serves as the fundamental analog ground for the PWM control circuitry. This pin should be connected to PGND directly at the device. LINEOV - 16 I For the UCC2892/4, provides the LINE overvoltage function. NAME DESCRIPTION LINEUV 15 15 I This pin provides a means to accurately enable/disable the power converter stage by monitoring the bulk input voltage or another parameter. When the circuit initially starts (or restarts from a disabled condition), a rising input on LINEUV enables the outputs when the threshold of 1.27 V is crossed. After the circuit is enabled, then a falling LINEUV signal disables the outputs when the same threshold is reached. The hysteresis between the two levels is programmed using an internal current source. OUT 13 13 O This output pin drives the main PWM switching element MOSFET in an active clamp controller. It can directly drive an N-channel device with 2-A source turn-on current and 2-A sink turn-off current. A 10-k resistor is recommended to connect this pin to PGND. PGND 11 11 - The PGND should serve as the current return for the high-current output drivers OUT and AUX. Ideally, the current path from the outputs to the switching devices, and back would be as short as possible, and enclose a minimal loop area. RSLOPE 8 8 I A resistor connected from this pin to GND programs an internal current source that sets the slope compensation ramp for the current mode control circuitry. RTDEL 1 1 I A resistor from this pin to GND programs the turn-on delay of the two gate drive outputs to accommodate the resonant transitions of the active clamp power converter. RTOFF 3 3 I A resistor connected from this pin to GND programs an internal current source that discharges the internal timing capacitor. RTON 2 2 I A resistor connected from this pin to GND programs an internal current source that charges the internal timing capacitor. SS/SD 10 10 I A capacitor from SS/SD to ground is charged by an internal current source of IRTON to program the soft-start interval for the controller. During a fault condition this capacitor is discharged by a current source equal to IRTON. SYNC 5 5 I The SYNC pin serves as a unidirectional synchronization input for the internal oscillator. The synchronization function is implemented such that the user programmable maximum duty cycle (set by RTON and RTOFF) remains accurate during synchronized operation. VDD 14 14 I This is the power supply for the device. There should be a 1-F capacitor directly from VDD to PGND. The capacitor value should be minimum 10 times greater than that on VREF. PGND and GND should be connected externally and directly from PGND to GND. VIN 16 - I For the UCC2891 and UCC2893, this pin is connected to the input power rail directly. Inside the device, a high-voltage start-up device is utilized to provide the start-up current for the controller until a bootstrap type bias rail becomes available. VREF 4 4 O This is the 5-V reference voltage that can be utilized for an external load of up to 5 mA. Since this reference provides the supply rail for internal logic, it should be bypassed to AGND as close as possible to the device. The VREF bias profile may not be monotonic before VDD reached 5 V. www.ti.com 7 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 DETAILED PIN DESCRIPTIONS RDEL (pin 1) This pin is internally connected to an approximately 2.5-V DC source. A resistor (RDEL) to GND (pin 6) sets the turn-on delay for both gate drive signals of the UCC2981 family of controllers. The delay time is identical for both switching transitions, between OUT (pin 13) is turning off and AUX (pin 14) is turning on as well as when AUX (pin 14) is turning off and OUT (pin 13) is turning on. The delay time is defined as: t DEL1 + t DEL2 + 11.1 10 *12 R DEL ) 15 10 *9 seconds (1) For proper selection of the delay time refer to the various references describing the design of active clamp power converters. RTON (pin 2) This pin is internally connected to an approximately 2.5-V DC source. A resistor (RON) to GND (pin 6) sets the charge current of the internal timing capacitor. The RTON pin, in conjunction with the RTOFF pin (pin 3) are used to set the operating frequency and maximum operating duty cycle of the UCC2891 family. RTOFF (pin3) This pin is internally connected to an approximately 2.5-V DC source. A resistor (ROFF) to GND (pin 6) sets the discharge current of the internal timing capacitor. The RTON and RTOFF pins are used to set the switching period (TSW) and maximum operating duty cycle (DMAX) according to the following equations: t ON + 36.1 t OFF + 15 10 *12 10 *12 R ON * t DEL1 seconds R OFF ) t DEL1 ) 170 (2) 10 *9 seconds T SW + t ON ) t OFF D MAX + (3) (4) t ON T SW (5) VREF (pin 4) The controller's internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a good quality ceramic bypass capacitor (CVREF) to GND (pin 6) for noise filtering and to provide compensation to the regulator circuitry. The recommended CVREF value is 0.22-F. The minimum bypass capacitor value is 0.022-F limited by stability considerations of the bias regulator, while the maximum is approximately 22-F. Also, capacitor value on VDD should be minimum 10 times greater than that on VREF. The VREF pin is internally current limited and can supply approximately 5-mA to external circuits. The 5-V bias is only available when the undervoltage lock out (UVLO) circuit enables the operation of UCC289x controllers. For the detailed functional description of the undervoltage lock out (UVLO) circuit refer to the Functional Description section of this datasheet. 8 www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) SYNC (pin 5) This pin provides an input for an external clock signal which can be used to synchronize the internal oscillator of the UCC289x family of controllers. The synchronizing frequency must be higher than the free running frequency of the onboard oscillator T SYNC t T SW. The acceptable minimum pulse width of the synchronization signal is approximately 50 ns (positive logic), and it should remain shorter than 1 * DMAX T SYNC where DMAX is set by RON and ROFF. If the pulse width of the synchronization signal stays within these limits, the maximum operating duty ratio remains valid as defined by the ratio of RON and ROFF, and DMAX is the same in free running and in synchronized modes of operation. If the pulse width of the synchronization signal would exceed the 1 * D MAX T SYNC limit, the maximum operating duty cycle is defined by the synchronization pulse width. For more information on synchronization of the UCC2891 family refer to the Functional Description section of this datasheet. GND (pin 6) This pin provides a reference potential for all small signal control and programming circuitry inside the UCC2891 family. CS (pin 7) This is a direct input to the PWM and current limit comparators of the UCC2891 family of controllers. The CS pin should never be connected directly across the current sense resistor (RCS) of the power converter. A small, customary R-C filter between the current sense resistor and the CS pin is necessary to accommodate the proper operation of the onboard slope compensation circuit and in order to protect the internal discharge transistor connected to the CS pin (RF, CF). Slope compensation is achieved across RF by a linearly increasing current flowing out of the CS pin. The slope compensation current is only present during the on-time of the gate drive signal of the main power switch (OUT) of the converter. The internal pull-down transistor of the CS pin is activated during the discharge time of the timing capacitor. This time interval is 1 * D MAX T SW long and represents the guaranteed off time of the main power switch. RSLOPE (pin 8) A resistor (RSLOPE) connected between this pin and GND (pin 6) sets the amplitude of the slope compensation current. During the on time of the main gate drive output (OUT) the voltage across RSLOPE is a representation of the internal timing capacitor waveform. As the timing capacitor is being charged, the voltage across RSLOPE also increases, generating a linearly increasing current waveform. The current provided at the CS pin for slope compensation is proportional to this current flowing through RSLOPE. Due to the high speed, AC voltage waveform present at the RSLOPE pin, the parasitic capacitance and inductance of the external circuit components connected to the RSLOPE pin should be carefully minimized. For more information on how to program the internal slope compensation refer to the Setup Guide section of this datasheet. www.ti.com 9 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) FB (pin 9) This pin is an input for the control voltage of the pulse width modulator of the UCC2891 family. The control voltage is generated by an external error amplifier by comparing the converters output voltage to a voltage reference and employing the compensation for the voltage regulation loop. Usually, the error amplifier is located on the secondary side of the isolated power converter and its output voltage is sent across the isolation boundary by an opto coupler. Thus, the FB pin is usually driven by the opto coupler. An external pull-up resistor to the VREF pin (pin 4) is also needed for proper operation as part of the feedback circuitry. The control voltage is internally buffered and connected to the PWM comparator through a voltage divider to make it compatible to the signal level of the current sense circuit. The useful voltage range of the FB pin is between approximately 1.25 V and 4.5 V. Control voltages below the 1.25-V threshold result in zero duty cycle (pulse skipping) while voltages above 4.5 V result in full duty cycle (DMAX) operation. SS/SD (pin 10) A capacitor (CSS) connected between this pin and GND (pin 6) programs the soft start time of the power converter. The soft-start capacitor is charged by a precise, internal DC current source which is programmed by the RON resistor connected to pin 2. The soft-start current is defined as: I SS + 0.43 I RTON + 0.43 V REF 2 1 R ON (6) This DC current charges CSS from 0 V to approximately 5 V. Internal to the UCC2891 family of controllers, the soft start capacitor voltage is buffered and ORed with the control voltage present at the FB pin (pin 9). The lower of the two voltages manipulates the controller's PWM engine through the voltage divider described with regards to the FB pin. Accordingly, the useful control range on the SS pin is similar to the control range of the FB pin and it is between 1.25 V and 4.5 V approximately. PGND (pin 11) This pin serves as a dedicated connection to all high-current circuits inside the UCC2891 family of parts. The high-current portion of the controller consists of the two high-current gate drivers, and the various bias connections except VREF (pin 4). The PGND (pin 11) and GND (pin 6) pins are not connected internally, a low-impedance, external connection between the two ground pins is also required. It is recommended to form a separate ground plane for the low current setup components (RDEL, RON, ROFF, CVREF, CF, RSLOPE, CSS and the emitter of the opto-coupler in the feedback circuit). This separate ground plane (GND) should have a single connection to the rest of the ground of the power converter (PGND) and this connection should be between pin 6 and pin 11 of the controller. AUX (pin 12) This is a high-current gate drive output for the auxiliary switch to implement the active clamp operation for the power stage. The auxiliary output (AUX) of the UCC2891 and UCC2892 drives a P-channel device as the clamp switch therefore it requires an active low operation (the switch is ON when the output is low). The UCC2893 and UCC2894 controllers are optimized for N-channel auxiliary switch therefore it employs the traditional active high drive signal. 10 www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) OUT (pin 13) This high-current output drives an external N-channel MOSFET. Each controller in the UCC2891 family uses active high drive signals for the main switch of the converter. Due to the high speed and high-drive current capability of these outputs (AUX, OUT) the parasitic inductance of the external circuit components connected to these pins should be carefully minimized. A potential way of avoiding unnecessary parasitic inductances in the gate drive circuit is to place the controller in close proximity to the MOSFETs and by ensuring that the outputs (AUX, OUT) and the gates of the MOSFET devices are connected by wide, overlapping traces. VDD (pin 14) The VDD rail is the primary bias for the internal, high-current gate drivers, the internal 5-V bias regulator and for parts of the undervoltage lockout circuit. To reduce switching noise on the bias rail, a good quality ceramic capacitor (CHF) must be placed very closely between the VDD pin and PGND (pin 11) to provide adequate filtering. The recommended CHF value is 1-F for most applications but its value might be affected by the properties of the external MOSFET transistors used in the power stage. In addition to the low-impedance, high-frequency filtering, the controller's bias rail requires a larger value energy storage capacitor (CBIAS) connected parallel to CHF. The energy storage capacitor must provide the hold up time to operate the UCC2891 family (including gate drive power requirements) during start up. In steady state operation the controller must be powered from a bootstrap winding off the power transformer or by an auxiliary bias supply. In case of an independent auxiliary bias supply, the energy storage is provided by the output capacitance of the bias supply. When using the internal JFET for startup, the external load on VDD must be limited to less than 4 mA. LINEUV (pin 15) This input monitors the incoming power source to provide an accurate undervoltage lockout function with user programmable hysteresis for the power supply controlled by the UCC2891 family. The unique property of the UCC2891 family is to use only one pin to implement these functions without sacrificing on performance. The input voltage of the power supply is scaled to the precise 1.27-V threshold of the undervoltage lockout comparator by an external resistor divider (RIN1, RIN2 in Figure 7). Once the line monitor's input threshold is exceeded, an internal current source gets connected to the LINEUV pin. The current generator is programmed by the RDEL resistor connected to pin 1 of the controller. The actual current level is given as: I HYST + V REF 2 1 R DEL 0.05 (7) As this current flows through RIN2 of the input divider, the undervoltage lockout hysteresis is a function of IHYST and RIN2 allowing accurate programming of the hysteresis of the line monitoring circuit. For more information on how to program the line monitoring function refer to the Setup Guide of this datasheet. www.ti.com 11 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) VIN (pin 16 - UCC2891 and UCC2893 only) The UCC2891 and UCC2893 controllers are equipped with a high voltage, P-channel JFET start up device to initiate operation from the input power source of the converter in applications where the input voltage does not exceed the 110-V maximum rating of the start up transistor. In these applications, the VIN pin can be connected directly to the positive terminal of the input power source. The internal JFET start up transistor provides approximately 15-mA charge current for the energy storage capacitor (CBIAS) connected across the VDD (pin 14) and PGND (pin 11) terminals. Note that the start up device is turned off immediately when the voltage on the VDD pin exceeds approximately 13.5 V, the controller's undervoltage lockout threshold for turn-on. The JFET is also disabled at all times when the high-current gate drivers are switching to protect against excessive power dissipation and current through the device. When using the internal JFET for startup, the external load on VDD must be limited to less than 4 mA. For more information on biasing the UCC2891 family, refer to the Setup Guide and Additional Application Information Sections of this datasheet. LINEOV (pin 16 - UCC2892 and UCC2894 only) In the UCC2892 and UCC2894 controllers the high-voltage start-up device is not utilized thus pin 16 is used for a different function. This input monitors the incoming power source to provide an accurate overvoltage protection with user programmable hysteresis for the power supply controlled by the controller. The circuit implementation of the overvoltage protection function is identical to the technique used for monitoring the input power rail for undervoltage lockout. This allows implementing an accurate threshold and hysteresis using only one pin. The input voltage of the power supply is scaled to the precise 1.27-V threshold of the overvoltage protection comparator by an external resistor divider (RIN3, RIN4 in Figure 7). Once the line monitor's input threshold is exceeded, an internal current source gets connected to the LINEOV pin. The current generator is programmed by the RDEL resistor connected to pin 1 of the controller. The actual current level is given as: I HYST + V REF 2 1 R DEL 0.05 (8) As this current flows through RIN4 of the input divider, the overvoltage protection hysteresis is a function of IHYST and RIN4 allowing accurate programming of the hysteresis of the line monitoring circuit. For more information on how to program the overvoltage protection, refer to the Setup Guide of this datasheet. 12 www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 FUNCTIONAL DESCRIPTION JFET Control and UVLO The UCC2891 and UCC2893 controllers include a high voltage JFET start up transistor. The steady state power consumption of the of the control circuit which also includes the gate drive power loss of the two power switches of an active clamp converter exceeds the current and thermal capabilities of the device. Thus the JFET should only be used for initial start up of the control circuitry and to provide keep-alive power during stand-by mode when the gate drive outputs are not switching. Accordingly, the start-up device is managed by its own control algorithm implemented on board the UCC2891 and UCC2893. The following timing diagram illustrates the operation of the JFET start up device. V ON V IN 13.5V 10.0V 8V <VDD < 10V 8.0V Bootstrap bias V DD OFF JFET OFF OFF ENABLE (See diagram on p.6) SS/SD OUTPUTs OFF OFF SWITCHING SWITCHING OFF UDG-03148 Figure 2. JFET Control Startup and Shutdown During initial power up the JFET is on and charges the CBIAS and CHF capacitors connected to the VDD pin (pin 14). The VDD pin is monitored by the controller's undervoltage lockout circuit to ensure proper biasing before the operation is enabled. When the VDD voltage reaches approximately 12.7 V (UVLO turn-on threshold) the UVLO circuit enables the rest of the controller. At that time, the JFET is turned off and 5 V appears on the VREF terminal (pin 4). Switching waveforms might not appear at the gate drive outputs unless all other conditions of proper operation are met. These conditions are: D D D D sufficient voltage on the VREF pin (VVREF > 4.5V) the voltage on the CS pin is below the current limit threshold the control voltage is above the zero duty cycle boundary (VFB > 1.25 V) the input voltage is in the valid operating range (VVON<VVIN<VVOFF) i.e. the line under or overvoltage protections are not activated. www.ti.com 13 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 FUNCTIONAL DESCRIPTION As the controller starts operation it draws its bias power from the CBIAS capacitor until the bootstrap winding takes over (refering to Figure 12). During this time VDD voltage is falling rapidly as the JFET is already off but the bootstrap voltage is still not sufficient to power the control circuits. It is imperative to store enough energy in CBIAS to prevent the bias voltage to dip below the turn off threshold of the UVLO circuit during the start up time interval. Otherwise the power supply goes through several cycles of retry attempts before steady state operation might be established. During normal operation the bias voltage is determined by the bootstrap bias design. The UCC289x family can tolerate a wide range of bias voltages between the minimum operating voltage (UVLO turn-off threshold) and the absolute maximum operating voltage as defined in the Recommended Operating Conditions. In applications where the power supply must be able to go to stand by in response to an external command, the bias voltage of the controller must be kept alive to be able to react intelligently to the control signal. In stand by mode, switching action is suspended for an undefined period of time and the bootstrap power is unavailable to bias the controller. Without an alternate power source the bias voltage would collapse and the controller would initiate a re-start sequence. To avoid this situation, the on board JFET of the UCC289x controllers can keep the VDD bias alive as long as the gate drive outputs remain inactive. As shown in the timing diagram in Figure 2, the JFET is turned on when VDD = 10 V and charges the CBIAS capacitor to approximately 13.5 V. At that time the JFET turns off and VDD gradually decreases to 10 V then the procedure is repeated. When the power supply is enabled again, the controller is fully biased and ready to initiate its soft start sequence. As soon as the gate drive pulses appear the JFET are turned off and bias must be provided by the bootstrap bias generator. During power down the situation is different as switching action might continue until the VDD bias voltage drops below the controller's own UVLO turn-off threshold (approximately 8 V). At that time the UCC289x shuts down completely turning off its 5 V bias rail and returning to start up state when the JFET device is turned on and the CBIAS capacitor starts charging again. In case the converter's input voltage is re-established, the UCC289x attempts to restart the converter. Line Undervoltage Protection As shown in Figure 3, when the input power source is removed the power supply is turned off by the line undervoltage protection because the bootstrap winding keeps the VDD bias up as long as switching takes place in the power stage. As the power supply's input voltage gradually decreases towards the line cut off voltage the converter's operating duty cycle must compensate for the lower input voltage. At minimum input voltage the duty cycle nears its maximum value (DMAX). Under these conditions the voltage across the clamp capacitor approaches its highest value since the transformer must be reset in a relatively short time. The timing diagram in Figure 3 highlights that in the instance when the converter stops switching the clamp capacitor voltage might be at its maximum level. Since the clamp capacitor's only load is the power transformer, this high voltage could linger across the clamp capacitor for a long time when the converter is off. With this high voltage present across the clamp capacitor a soft start would be very dangerous, due to the narrow duty cycle of the main switch and the long on-time of the clamp switch. This could cause the power transformer to saturate during the next soft-start cycle. 14 www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 FUNCTIONAL DESCRIPTION VOFF VIN V CLAMP, MAX VCLAMP VSS TSW OUT AUX Figure 3. Line Undervoltage Shutdown Waveforms, P-Channel To eliminate this potential hazard the UCC289x controllers safely discharge the clamp capacitor during power down. The AUX and OUT output continues switching while the soft-start capacitor CSS is being slowly discharged. Notice that the AUX and OUT pulse width gradually decreases as the clamp voltage decreases never applying the high voltage across the transformer for extended period of time. From this, the function of soft stop is achieved. Line Overvoltage Protection When the line overvoltage protection is triggered in the UCC2892 and UCC2894 controllers, the gate drive signals are immediately disabled. At the same time, the slow discharge of CSS is initiated. While the soft-start capacitor is discharging the gate drive signals remains disabled. Once VSS = 0.5 V and the overvoltage disappears from the input of the power supply, operation resumes through a regular soft-start of the converter as it is demonstrated in Figure 4. www.ti.com 15 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 FUNCTIONAL DESCRIPTION VOVP VOVH VIN VSS OUT AUX UDG-03150 Figure 4. Line Overvoltage Sequence, P-Channel Pulse Skipping During output load current transients or light load conditions most PWM controllers needs to be able to skip some number of PWM pulses. In an active clamp topology where the clamp switch is driven complementarily to the main switch, this would apply the clamp voltage across the transformer continuously. Since operating conditions might require skipping several switching cycles on the main transistor, saturating the transformer is very likely if the AUX output stays on. D = 0 Boundary 1.25 V FB TSW OUT UDG-03151 AUX Figure 5. Pulse Skipping Operation, P-Channel To overcome this problem, the UCC2891 family incorporates pulse skipping for both outputs in the controller. As can be seen above, when a pulse is skipped at the main output (OUT) because the feedback signal demands zero duty ratio, the corresponding output pulse on the AUX output is omitted as well. This operation allows to prevent reverse saturation of the power transformer and to preserve the clamp capacitor voltage level during pulse skipping operation. 16 www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 FUNCTIONAL DESCRIPTION Synchronization The UCC2891 family has a synchronization input pin which can be used to synchronize their oscillator to a constant frequency system clock. The synchronization signal must have a higher frequency than the free running oscillator frequency and can be either in-phase or out-of-phase for interleaved operation. The operation of the oscillator and relevant other waveforms in free running and synchronized mode are shown in Figure 6. SYNC CT DMAX OUT AUX UDG-03152 Figure 6. Synchronization Waveforms, P-Channel The most critical and unique feature of the oscillator is to limit the maximum operating duty cycle of the converter. It is achieved by accurately controlling the charge and discharge intervals of the on board timing capacitor. The maximum on-time of OUT (pin 13), which is also the maximum duty cycle of the active clamp converter is limited by the charging interval of the timing capacitor. While the capacitor is being reset to its initial voltage level OUT is guaranteed to be off. When synchronization is used, the rising edge of the signal terminates the charging period and initiate the discharge of the timing capacitor. Once the timing capacitor voltage reaches the predefined valley voltage, a new charge period starts automatically. This method of synchronization leaves the charge and discharge slopes of the timing waveform unaffected thus maintains the maximum duty cycle of the converter, independent of the mode of operation. Although the synchronization circuit is level sensitive, the actual synchronization event occurs at the rising edge of the waveform. This allows the synchronizing pulse width to vary significantly but certain limitations must be observed. The minimum pulse width should be sufficient to guarantee reliable triggering of the internal oscillator circuitry, therefore it should be greater than approximately 50 nanoseconds. The other limiting factor is to keep it shorter than 1 * D MAX T SYNC where TSYNC is the period of the synchronization frequency. www.ti.com 17 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 FUNCTIONAL DESCRIPTION When a wider than 1 * D MAX T SYNC pulse is connected to the SYNC input, the oscillator is not able to maintain the maximum duty cycle, originally set by the timing resistor ratio (RON, ROFF). Furthermore, the timing capacitor waveform has a flat portion as highlighted by the vertical marker in the timing diagram. During this flat portion of the waveform both outputs is off which state is not compatible with the operation of active clamp power converters. Therefore, this operating mode is not recommended . Note that both outputs of the UCC289x controllers are off if the synchronization signal stays continuously high. APPLICATION INFORMATION: SETUP GUIDE RIN2 RIN1 RIN2 RIN1 RIN4 RIN3 +VIN +VIN 1 RDEL RDEL 1 RDEL LINEOV 16 VIN 16 2 RTON LINEUV 15 2 RTON LINEUV 15 3 RTOFF VDD 14 4 VREF OUT 13 CVREF ROT 5 SYNC 6 GND -VIN RSLOPE 8 RSLOPE 4 VREF OUT 13 5 SYNC AUX 12 6 GND PGND 11 7 CS SS/SD 10 FB 9 8 RSLOPE CSS CSS RVREF Isolated Feedback Figure 7. UCC289x Typical Setup 18 www.ti.com FB 9 RF RF RVREF -VIN CF SS/SD 10 RSLOPE VDD 14 ROT CF 7 CS 3 RTOFF CVREF AUX 12 PGND 11 CHF ROFF POWER STAGE CHF ROFF CBIAS RON CBIAS RON UCC2892 UCC2894 POWER STAGE RDEL UCC2891 UCC2893 Isolated Feedback SLUS542F - OCTOBER 2003 - REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE The UCC2891 family offers a highly integrated feature set and excellent accuracy to control an active clamp forward or active clamp flyback power converter. In order to take advantage of all the benefits integrated in these controllers, the following procedure can simplify the setup and avoid unnecessary iterations in the design procedure. Refer to Figure 7 setup diagrams for component names. Before the controller design begins, the power stage design must be completed. From the power stage design the following operating parameters are needed to complete the setup procedure of the controller: D D D D D D D D D D D Switching frequency (fSW) Maximum operating duty cycle (DMAX) Soft start duration (tSS) Gate drive power requirements of the external power MOSFETs (QG(main), QG(aux)) Bias method and voltage for steady state operation (bootstrap or bias supply) Gate drive turn-on delay (tDEL) Turn-on input voltage threshold (VON) Minimum operating input voltage (VOFF) where VIN (off) < VIN(on) Maximum operating input voltage (VOVP) overvoltage protection hysteresis (VOVH) The down slope of the output inductor current waveform reflected across the primary side current sense resistor dV Ldt Step 1. Oscillator The two timing elements of the oscillator can be calculated from fSW and DMAX by the following two equations: R ON + t ON 37.33 R OFF + 10 *12 t OFF 16 10 *12 Ws + f Ws + f D MAX SW 37.33 10 *12 1 * D MAX SW 16 10 *12 Ws Ws (9) (10) where DMAX is a dimensionless number between 0 and 1. Step 2. Soft Start Once RON is defined, the charge current of the soft-start capacitor can be calculated as: I SS + 0.43 V REF 2 1 R ON (11) During soft start, CSS is being charged from 0 V to 5 V by the calculated ISS current. The actual control range of the soft-start capacitor voltage is between 1.25 V and 4.5 V. Therefore, the soft-start capacitor value must be based on this narrower control range and the required start up time (tSS) according to: C SS + I SS t SS 4.5 V * 1.25 V (12) www.ti.com 19 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE Note, that tSS defines a time interval to reach the maximum current capability of the converter and not the time required to ramp the output voltage from 0 V to its nominal, regulated level. Using an open-loop start up scheme does not allow accurate control over the ramp up time of the output voltage. In addition to the ISS and CSS values, the time required to reach the nominal output voltage of the converter is a function of the maximum output current (current limit), the output capacitance of the converter and the actual load conditions. If it is critical to implement a tightly controlled ramp-up time at the output of the converter, the soft-start must be implemented using a closed loop technique. Closed loop soft-start can be implemented with the error amplifier of the voltage regulation loop when its voltage reference is ramped from 0 V to its final steady state value during the required tSS start up time interval. Step 3. VDD Bypass Requirements First, the high-frequency filter capacitor is calculated based on the gate charge parameters of the external MOSFETs. Assuming that the basic switching frequency ripple should be kept below 0.1-V across CHF, its value can be approximated as: C HF + Q G(main) ) Q G(aux) (13) 0.1 V The energy storage requirements are defined primarily by the start up time (tSS) and turn-on (approximately 12.7 V) and turn-off (approximately 8 V) thresholds of the controller's undervoltage lockout circuit monitoring the VDD voltage at pin 14. In addition, the bias current consumption of the entire primary side control circuit (IDD + IEXT) must be known. This power consumption can be estimated as: P BIAS + I DD ) I EXT ) Q G(main) ) Q G(aux) f SW V DD (14) During start up (tSS) this power is provided by CBIAS while its voltage must remain above the UVLO turn-off threshold. This relationship can be expressed as: P BIAS t SS t 1 2 C BIAS 13 2 * 8.5 2 (15) Rearranging the equation yields the minimum value for CBIAS: C BIAS u 2 P BIAS t SS 2 2 13 * 8.5 (16) Step 4. Delay Programming From the power stage design, the required turn-on delay (tDEL) of the gate drive signals is defined. The corresponding RDEL resistor value to implement this delay is given by: R DEL + T DEL1 0.91 10 11 Ws (17) R DEL + T DEL2 0.91 10 11 Ws (18) or 20 www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE Step 5. Input Voltage Monitoring The input voltage monitoring functions is governed by the following two expressions of the voltage at the LINEUV terminal (pin 15): R IN2 at turn on, and R IN1 ) R IN2 V LINEUV + V ON V LINEUV + V OFF * V VON ) I HYST R IN1 R IN2 at turn off. (19) (20) Since VON and VOFF are given by the power supply specification, VLINEUV equals the 1.27-V threshold of the line monitor and IHYST is already defined as: I HYST + V REF 2 1 R DEL 0.05 (21) the two unknown, RIN1 and RIN2 are fully determined. Solving the equations results the following two expressions for the input voltage divider: R IN1 + VON * VOFF I HYST R IN2 + R IN1 (22) 1.27 V V ON * 1.27 V (23) Similar methods can be used to define the divider components of the overvoltage protection input of the UCC2892 and UCC2894 controllers. Step 6. Current Sense and Slope Compensation The UCC2891 family offers onboard, user programmable slope compensation. The programming of the right amount of slope compensation is accomplished by the appropriate selection of two external resistors, RF and RSLOPE. First, the current sense filter resistor value (RF) must be calculated based on the desired filtering of the current sense signal. The filter consists of two components, CF and RF. The CF filter capacitor is connected between the CS pin (pin 7) and the GND terminal (pin 6). While the value of CF can be freely selected as the first step of the filter design, it should be minimized to avoid filtering the slope compensation current exiting the CS pin. The recommended range for the filter capacitance is between 50 pF and 270 pF. The value of the filter resistor can be calculated from the filter capacitance and the desired filter corner frequency fF. RF + 2p 1 fF CF (24) After RF is defined RSLOPE can be calculated. The amount of slope compensation is defined by the stability requirements of the inner peak current loop of the control algorithm and is measured by the number m. When the slope of the applied compensation ramp equals the down slope of the output inductor current waveform reflected across the primary side current sense resistor dV Ldt, m equals 1. The minimum value of m is 0.5 to prevent current loop instability. Best current mode performance can be achieved around m=1. The further increase of m moves the control closer to voltage mode control operation. www.ti.com 21 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE In the UCC289x controllers, slope compensation is implemented by sourcing a linearly increasing current at the CS pin. When this current passes through the current sense filter resistor (RF), it is converted to a slope compensation ramp which can be characterized by its dV Sdt. The dV Sdt of the slope compensation current is defined by RSLOPE according to: dI S 5 2V + t ON R SLOPE dt (25) where D 2V is the peak-to-peak ramp amplitude of the internal oscillator waveform D 5 is the multiplication factor of the internal current mirror The voltage equivalent of the compensation ramp dV Sdt can be easily obtained by multiplying with RF. After introducing the application specific m and dV Ldt values, the equation can be rearranged for RSLOPE: R SLOPE + 5 t ON 22 2V m RF dV L dt (26) www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION The UCC2891 family of controllers is dedicated to control current mode active clamp flyback or forward converters in an isolated power supply. The key advantage of the active clamp topologies is the zero voltage switching (ZVS) of the primary side semiconductors. This operating mode reduces the switching losses of the converter, thus facilitates higher switching frequencies or improves efficiency when operated at similar frequencies as its hard switched designs. The simplified schematics below demonstrate the typical implementations of these converters. This active clamp flyback converter shown in Figure 8 highlights a high-side clamp circuit using an N-channel MOSFET transistor as the auxiliary clamp switch. +VIN CCLAMP Bootstrap Bias Load 16 VIN 14 QAUX VDD AUX N-Channel Gate Drive 12 Synchronous Rectifier Control UCC2893 QMAIN OUT CBIAS 13 CIN ROT CS 7 FB 9 RCS GND Secondary-Side Error Amplifier and Isolation 6 -VIN UDG-03153 Figure 8. Zero Voltage Switching Flyback Application +VIN Load Bootstrap Bias 16 CCLAMP VIN 14 VDD AUX 12 CIN UCC2891 CBIAS 13 CS 7 FB Synchronous Rectifier Control QMAIN OUT ROT GND QAUX P-Channel Gate Drive RCS 9 Secondary-Side Error Amplifier and Isolation 6 -VIN UDG-03154 Figure 9. Active Clamp Forward Converter www.ti.com 23 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION Figure 9 shows an active clamp forward converter with high-side clamp utilizing a P-channel auxiliary switch. Detailed analysis and design examples of active clamp converters are published in the references listed at the end of this datasheet. Gate Drive Implementations Both topologies can make use of either the high-side or the low-side clamp arrangement. Depending on the choice of the clamp circuit, the gate drive requirements of the auxiliary switch are different. +VIN 12 +VIN CCLAMP CCLAMP QAUX QAUX QMAIN AUX 12 P QMAIN Figure 10. High-Side N-Channel (UCC2893/4) Figure 11. Low-Side P-Channel (UCC2891/2) Interfacing with a high side N-channel clamp switch is achievable by using high side gate drive integrated circuits or through a gate drive transformer. When a transformer is used, special attention must be paid to the fact that the clamp switch is operated by the complementary waveform of the main power switch. Since the operating duty cycle of the converter can vary between 0 and DMAX, the gate drive transformer must be able to drive the auxiliary switch with any duty cycle from 1-DMAX to near 1. The low side P-channel gate drive circuit involves a level shifter using a capacitor and a diode which ensures that the gate drive amplitude of the auxiliary switch is independent of the actual duty cycle of the converter. Detailed analysis and design examples of these and many similar gate drive solutions are given in reference [6]. Bootstrap Biasing Many converters use a bootstrap circuit to generate its own bias power during steady state operation. The popularity of this solutions is justified by the simplicity and high efficiency of the circuit. Usually, bias power is derived from the main transformer by adding a dedicated, additional winding to the structure. Using a flyback converter as shown in Figure 12, a bootstrap winding provides a quasi-regulated bias voltage for the primary side control circuits. The voltage on the VDD pin is equal to the output voltage times the turns ratio between the output and the bootstrap windings in the transformer. Since the output is regulated, the bias rail is regulated as well. 24 www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION While the same arrangement can be used in a forward type converter, the bootstrap winding off the main power transformer would not be able to provide a quasi-regulated voltage. In the forward converter, the voltage across the bootstrap winding equals the input voltage times the turns ratio. Accordingly the bias voltage would vary with the input voltage and most likely would exceed the maximum operating voltage of the control circuits at high line. A linear regulator can be used to limit and regulate the bias voltage if the power dissipation is acceptable. Another possible solution for the forward converter is to generate the bias voltage from the output inductor as shown in Figure 13. Bootstrap Bias 1 +VIN 16 LOAD VIN VDD 14 UCC2891 CIN CBIAS GND Synchronous Rectifier Control QMAIN 6 -VIN UDG-03155 Figure 12. Bootstrap Bias 1, Flyback Example This solution uses the regulated output voltage across the output inductor during the freewheeling period to generate a quasi-regulated bias for the control circuits. Bootstrap Bias 2 +VIN 16 LOAD VIN VDD UCC2891 GND 14 CIN CBIAS Synchronous Rectifier Control QMAIN 6 -VIN UDG-03156 Figure 13. Bootstrap Bias 2, Forward Example www.ti.com 25 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION This solution uses the regulated output voltage across the output inductor during the freewheeling period to generate a quasi-regulated bias for the control circuits. Both of the illustrated solution provides reliable bias power during normal operation. Note that in both cases, the bias voltages are proportional to the output voltage. This nature of the bootstrap bias supply causes the converter to operate in a hiccup mode under significant overload or under short-circuit conditions as the bootstrap winding is not able to hold the bias rail above the undervoltage lockout threshold of the controller. ADDITIONAL APPLICATION INFORMATION References and Additional Development Tools 1. Evaluation Module: UCC2891EVM, 48-V to 3.3-V, 30-A Forward Converter with Active Clamp Reset. 2. User's Guide: Using the UCC2891EVM, 48-V to 3.3-V, 30-A Forward Converter with Active Clamp Reset, (SLUU178) 3. Application Note: Designing for High Efficiency with the UCC2891 Active Clamp PWM Controller, Steve Mappus (SLUA303) 4. Power Supply Design Seminar Topic: Design Considerations for Active Clamp and Reset Technique, D. Dalal, SEM1100-Topic3 (SLUP112) 5. Power Supply Design Seminar Topic: Active Clamp and Reset Technique Enhances Forward Converter Performance, B. Andreycak, SEM1000-Topic 3. (SLUP108) 6. Power Supply Design Seminar Topic: Design and Application Guide for High Speed MOSFET Gate Drive Circuits, L. Balogh, SEM1400-Topic 2 (SLUP169) 7. Datasheet: UCC3580, Single Ended Active-Clamp/Reset PWM Controller, (SLUS292A) 8. Evaluation Module: UCC3580EVM, Flyback Converters, Active Clamp vs. Hard-Switched (SLUU085) 9. Reference Designs: Highly Efficient 100W Isolated Power Supply Reference Design Using UCC3580-1, Texas Instruments Hardware Reference Design Number PMP206-C (SLUU146) 10. Reference Designs: Active Clamp Forward Reference Design using UCC3580-1. Texas Instruments Hardware Reference Design Number PMP368 (SLVR053, SLVR079, SLVR096) Reference Circuit For completeness, the schematic diagram of a complete active clamp forward converter is shown in Figure 14. The detailed description of the circuit operation and design procedure can be found in SLUU178. 26 www.ti.com SLUS542F - OCTOBER 2003 - REVISED JULY 2009 + + + + ADDITIONAL APPLICATION INFORMATION Figure 14. UCC2891 EVM Schematic www.ti.com 27 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 TYPICAL CHARACTERISTICS UVLO VOLTAGE THRESHOLDS vs JUNCTION TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE 2.5 12 UVLO On IDD - Supply Current - mA VUVLO - UVLO Voltage Thresholds - V 14 10 8 UVLO Off 6 UVLO Hysteresis 4 2.0 1.5 1.0 0.5 2 0 -50 0 -25 0 25 50 75 100 125 0 4 2 TJ - Junction Temperature - C 6 8 10 12 VDD - Supply Voltage - V Figure 15 UCC2891/UCC2893 VIN = 36 V No Load 10 mA Load 0 VREF - Reference Voltage - V IDD - Supply Current - mA REFERENCE VOLTAGE vs TEMPERATURE 10 0 -10 -20 -30 JFET Source Current -10 -20 -30 -40 -40 -50 0 2 4 6 8 10 12 VDD - Supply Voltage - V 14 16 -50 -50 -25 0 25 50 75 TJ - Junction Temperature - C Figure 17 28 16 Figure 16 SUPPLY CURRENT vs SUPPLY VOLTAGE 10 14 Figure 18 www.ti.com 100 125 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 TYPICAL CHARACTERISTICS VTH - Line Thresholds - V 1.28 1.26 1.24 1.22 1.20 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 15 Softstart Discharge Current 10 5 0 -5 -10 -15 -20 -50 125 Softstart Charge Current -25 0 25 50 75 100 125 TJ - Junction Temperature - C Figure 20 Figure 19 SOFTSTART/SHUTDOWN THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs PROGRAMMING RESISTANCE 10 M 0.60 0.58 0.56 fSW - Switching Frequency - Hz VTH - Softstart/Shutdown Threshold Voltage - V SOFTSTART CURRENTS vs TEMPERATURE 20 ISS(DIS)/ISS(CHG)- Softstart Currents-A 1.30 LINE UV/OV VOLTAGE THRESHOLD vs JUNCTION TEMPERATURE 0.54 0.52 0.50 0.48 0.46 0.44 1M 100 K 10 K 0.42 0.40 -50 -25 0 25 50 75 100 125 TJ - Junction Temperature - C 1K 10 100 RON = ROFF - Timing Resistance - k 1000 Figure 22 Figure 21 www.ti.com 29 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE MAXIMUM DUTY CYCLE vs JUNCTION TEMPERATURE 74 275 RON = ROFF = 75 k RON = ROFF = 75 k 73 265 DMAX- Maximum Duty Cycle - % fSW - Switching Frequency - kHz 270 260 255 250 245 240 235 71 70 69 68 67 230 225 -50 72 -25 0 25 50 75 100 TJ - Junction Temperature - C 66 -50 125 -25 0 25 50 75 100 125 TJ - Junction Temperature - C Figure 23 Figure 24 CURRENT SENSE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE SYNCHRONIZATION THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1.4 1.2 VSYNC - Synchronization Threshold Voltage - V VCS - Current Sense Threshold Voltage - V 2.50 UCC2892/UCC2894 1.0 0.8 UCC2891/UCC2893 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 125 2.40 2.35 2.30 2.25 2.20 2.15 2.10 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C Figure 25 30 2.45 Figure 26 www.ti.com 125 SLUS542F - OCTOBER 2003 - REVISED JULY 2009 TYPICAL CHARACTERISTICS DELAY TIME vs DELAY RESISTANCE OUT AND AUX RISE AND FALL TIME vs JUNCTION TEMPERATURE 25 800 CLOAD = 2 nF 700 t DEL1 600 15 tDEL- Delay Time - ns tR/tF - Rise and Fall Times - ns Rise Time 20 Fall Time 10 t DEL2 500 400 300 200 5 100 0 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature - C 0 125 10 20 30 40 50 60 70 RDEL - Delay Resistance - k Figure 28 Figure 27 DELAY TIME vs JUNCTION TEMPERATURE DELAY TIME vs JUNCTION TEMPERATURE 250 800 RDEL = 10 k RDEL = 50 k 700 200 tDEL- Delay Time - s tDEL- Delay Time - ns 600 OUT to AUX 150 100 500 AUX to OUT OUT to AUX 400 300 200 AUX to OUT 50 100 0 -50 -25 0 25 50 75 100 125 0 -50 -25 0 25 50 75 100 125 TJ - Junction Temperature - C TJ - Junction Temperature - C Figure 29 Figure 30 www.ti.com 31 PACKAGE OPTION ADDENDUM www.ti.com 5-Mar-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp UCC2891D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2891DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2891DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2891DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2891PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2891PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2891PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2891PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2892D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2892DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2892DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2892DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2892PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2892PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2892PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2892PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2893D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 5-Mar-2011 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp UCC2893DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2893DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2893DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2893PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2893PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2893PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2893PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2894D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2894DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2894DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2894DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2894PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2894PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2894PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC2894PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 5-Mar-2011 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.3 2.1 8.0 16.0 Q1 UCC2891DR SOIC D 16 2500 330.0 16.4 6.5 UCC2891PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 UCC2892DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2892PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 UCC2893DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2893PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 UCC2894DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2894PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC2891DR SOIC D 16 2500 333.2 345.9 28.6 UCC2891PWR TSSOP PW 16 2000 367.0 367.0 35.0 UCC2892DR SOIC D 16 2500 333.2 345.9 28.6 UCC2892PWR TSSOP PW 16 2000 367.0 367.0 35.0 UCC2893DR SOIC D 16 2500 333.2 345.9 28.6 UCC2893PWR TSSOP PW 16 2000 367.0 367.0 35.0 UCC2894DR SOIC D 16 2500 333.2 345.9 28.6 UCC2894PWR TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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