SPICE Device Model Si4804DY Vishay Siliconix Dual N-Channel 30-V (D-S) MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model schematic is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71487 01-May-01 www.vishay.com 1 SPICE Device Model Si4804DY Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit Static VGS(th) VDS = VGS, ID = 250 A .98 V On-State Drain Current ID(on) VDS 5 V, VGS = 10 V 281 A Drain-Source On-State Resistancea rDS(on) VGS = 10V, ID = 7.5 A 0.016 VGS = 4.5V, ID = 6.5 A 0.023 Gate Threshold Voltage a a Forward Transconductance a Diode Forward Voltage Dynamic gfs VDS = 15 V, ID = 7.5 A 20 S VSD IS = 1.7 A, VGS = 0 V 0.80 V b Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) 8 tr 10 Rise Time Turn-Off Delay Time td(off) Fall Time tf Source-Drain Reverse Recovery Time trr 13 VDS = 15 V, VGS = 10 V, ID = 7.5 A 2 nC 2.7 VDD = 15 V, RL = 15 ID 1 A, VGEN = 10 V, RG = 6 14 ns 26 IF = 1.7 A, di/dt = 100 A/s 40 Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 71487 01-May-01 SPICE Device Model Si4804DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 71487 01-May-01 www.vishay.com 3