70T3519S166BFG8 - IDT, Integrated Device Technology Inc

JUNE 2018

DSC 5666/12

Functional Block Diagram

◆Interrupt and Collision Detection Flags

◆Separate byte controls for multiplexed bus and bus

matching compatibility

◆Dual Cycle Deselect (DCD) for Pipelined Output Mode

◆2.5V (±100mV) power supply for core

◆LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

◆Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

◆Available in a 256-pin Ball Grid Array (BGA), a 208-pin

Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball

Grid Array (fpBGA)

◆Supports JTAG features compliant with IEEE 1149.1

◆Due to limited pin count JTAG is not supported on the 208-

pin PQFP package

◆◆

◆Green parts available, see ordering information

HIGH-SPEED 2.5V

256/128/64K x 36

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70T3519/99/89S

REPEAT

CNTEN

ADS

Dout0-8_R

Dout9-17_R

I/O

- I/O

35R

Din_R

ADDR_R

R/W

1/0

FT/PIPE

1a 0a1b 0b1c 0c1d 0d

dcba

CLK

Counter/

Address

Reg.

dcba

0/1

0d 1d0c 1c

0b 1b0a 1a

FT/PIPE

Counter/

Address

Reg.

CNTEN

ADS

REPEAT

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L Dout18-26_R

Dout27-35_R

I/O

-I/O

35L

17L

(1)

Din_L

ADDR_L

5666 drw 01

R/W

256/128/64K x 36

MEMORY

ARRAY

CLK

abcd

FT/PIPE

L0/1

1d 0d 1c 0c 1b 0b 1a 0a

JTAG

TCK

TRST

TMS

TDO

TDI

1/0

0d 1d0c 1c0b 1b0a 1a

abcd

FT/PIPE

L1/0

1/0

INTERRUPT

COLLISION

DETECTION

LOGIC

CE1L

CE1R

INT

COL

INT

COL

CONTROL

LOGIC

L(2)

R(2)

17R

(1)

Features:

◆True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

◆Selectable Pipelined or Flow-Through output mode

◆Counter enable and repeat features

◆Dual chip enables allow for depth expansion without

additional logic

◆Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

1. Address A17 is a NC for the IDT70T3599. Also, Addresses A17 and A16 are NC's for the IDT70T3589.

2 . The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

NOTES:

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70T3519/99/89 is a high-speed 256/128/64K x 36 bit

synchronous Dual-Port RAM. The memory array utilizes Dual-Port

memory cells to allow simultaneous access of any address from both ports.

Registers on control, data, and address inputs provide minimal setup and

hold times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times. With an input data register, the

IDT70T3519/99/89 has been optimized for applications having unidirec-

tional or bidirectional data flow in bursts. An automatic power down feature,

controlled by CE0 and CE1, permits the on-chip circuitry of each port to

enter a very low standby power mode.

The 70T3519/99/89 can support an operating voltage of either 3.3V

or 2.5V on one or both ports, controllable by the OPT pins. The power

supply for the core of the device (VDD) is at 2.5V.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration (3,4,5,6)

NOTES:

1. Pin is a NC for IDT70T3599 and IDT70T3589.

2. Pin is a NC for IDT70T3589.

3. All VDD pins must be connected to 2.5V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

set to VSS (0V).

5. All VSS pins must be connected to ground supply.

6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

70T3519/99/89BC

BC256(7)

256-Pin BGA

Top View(8)

E16

I/O

14R

D16

I/O

16R

C16

I/O

16L

B16

A16

A15

B15

I/O

17L

C15

I/O

17R

D15

I/O

15L

E15

I/O

14L

E14

I/O

13L

D14

I/O

15R

D13

C12

6L C14

OPT

B14

A14

A12

B12

C11

ADS

D12

DDQR

D11

DDQR

C10

CLK

B11

REPEAT

A11

CNTEN

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

14L

15L

13L

DDQL

PIPE/

TDO

I/O

20L

I/O

19R

I/O

19L

TDI

I/O

18L

I/O

18R

I/O

20R

I/O

21R E2

I/O

21L E3

I/O

22L E4

DDQL

I/O

23L F2

I/O

22R F3

I/O

23R F4

DDQL

I/O

24R G2

I/O

24L G3

I/O

25L

DDQR

I/O

26L H2

I/O

25R

I/O

26R H4

DDQR

I/O

27L J2

I/O

28R J3

I/O

27R J4

DDQL

I/O

29R

I/O

29L K3

I/O

28L

DDQL

I/O

30L L2

I/O

31R

I/O

30R L4

DDQR

I/O

32R M2

I/O

32L M3

I/O

31L M4

DDQR

I/O

33L N2

I/O

34R N3

I/O

33R

PIPE/

I/O

35R P2

I/O

34L P3

TMS

I/O

35L R2

TRST

TCK

13R

15R

P12

1R P9

P10

CLK

T11

CNTEN

P11

ADS

R12

T12

P13

R13

T13

12R

14R T14

R14

OPT

P14

I/O

0L P15

I/O

R15

T15

T16

R16

P16

I/O

N16

I/O

N15

I/O

N14

I/O

M16

I/O

M15

I/O

M14

I/O

L16

I/O

L15

I/O

L14

I/O

K16

I/O

K15

I/O

K14

I/O

J16

I/O

J15

I/O

J14

I/O

H16

I/O

10R

H15

H14

I/O

G16

I/O

11R

G15

I/O

11L

G14

I/O

10L

F16

I/O

12L

F14

I/O

12R F15

I/O

13R

0R R11

REPEAT

11R

11L

B10

R/W

C13

10R

R10

R/W

T10

DD E7

INT

LE8

SS E9

SS E10

SS E11

DD E12

DD E13

DDQR

DD F6

SS F10

SS F12

DD F13

DDQR

SS G6

SS G7

SS G9

SS G10

SS G11

G12

SS G13

DDQL

SS H6

SS H8

SS H9

SS H10

H11

SS H12

SS H13

DDQL

RJ6

SS J7

SS J8

SS J9

SS J10

SS J11

SS J12

J13

DDQR

SS K7

DD L6

COL

RL8

DD M6

DD M7

INT

RM8

DDQR N6

DDQR N7

DDQL

K10

SS K11

K12

SS L10

L11

SS L12

SS M10

SS M11

DD M12

DDQR N10

DDQR N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

COL

LF11

5666 drw 02d

06/19/02

17R

(1)

17L

(1)

16L

(2)

16R

(2)

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration (3,4,5,6,9) (con't.)

NOTES:

3. All VDD pins must be connected to 2.5V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to Vss (0V).

5. All VSS pins must be connected to ground supply.

6. Package body is approximately 28mm x 28mm x 3.5mm.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

9. Due to limited pin count, JTAG is not supported in the DR208 package.

1. Pin is a NC for IDT70T3599 and IDT70T3589.

2. Pin is a NC for IDT70T3589.

100

101

102

103

104

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

70T3519/99/89DR

DR208

(7)

208-Pin PQFP

Top View

(8)

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

DDQL

I/O

35R

I/O

35L

PL/FT

COL

INT

17R(1)

16R(2)

15R

14R

13R

12R

11R

10R

CLK

R/W

ADS

CNTEN

REPEAT

OPT

I/O

DDQL

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

DDQR

I/O

18R

I/O

18L

PL/FT

COL

INT

17L(1)

16L(2)

15L

14L

13L

12L

11L

10L

CLK

R/W

ADS

CNTEN

REPEAT

OPT

I/O

17L

I/O

17R

DDQR

5666 drw 02a

02/03/14

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

NOTES:

3. All VDD pins must be connected to 2.5V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

set to VSS (0V).

5. All VSS pins must be connected to ground supply.

6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

Pin Configuration (3,4,5,6) (con't.)

1. Pin is a NC for IDT70T3599 and IDT70T3589.

2. Pin is a NC for IDT70T3589.

A17

B17

I/O

15R

C17

D17

I/O

14R

E16

SS E17

I/O

13L

D16

I/O

14L

C16

I/O

15L

B16

I/O

16L

A16

I/O

17L

A15

OPT

B15

DDQR

C15

I/O

16R

D15

DDQL

E15

I/O

13R

E14

I/O

12L

D14

I/O

17R

D13

C12

6L C14

B14

A14

A12

CNTEN

B12

C11

R/W

D12

D11

REPEAT

C10

B11

ADS

A11

CLK

D10

10L

B13

A13

A10

12L

13L

14L

11L

COL

INT

15L

TDO

TDI

PL/FT

I/O

20L

I/O

18R

DDQR

I/O

21L

I/O

19R

I/O

18L

I/O

19L

I/O

20R

DDQL

I/O

22L

I/O

23L E2

I/O

22R E3

DDQR E4

I/O

21R

DDQL F2

I/O

23R F3

I/O

24L F4

I/O

26L G2

SS G3

I/O

25L

I/O

24R

DD H2

I/O

26R

DDQR H4

I/O

25R

DDQL J2

DD J3

SS J4

I/O

28R

SS K3

I/O

27R

I/O

29R L2

I/O

28L

DDQR L4

I/O

27L

DDQL M2

I/O

29L M3

I/O

30R M4

I/O

31L N2

SS N3

I/O

31R

I/O

30L

I/O

32R P2

I/O

32L P3

DDQR P4

I/O

35R

SS R2

I/O

33L R3

I/O

34R R4

TCK

I/O

33R

I/O

34L T3

DDQL T4

TMS

SS U2

I/O

35L U3

PL/FT

RU4

COL

TRST

11R

P12

U10

P10

T11

R/W

P11

CLK

R12

T12

U12

P13

12R

R13

T13

U13

13R

INT

7R U14

T14

R14

P14

I/O

2L P15

I/O

R15

DDQL

T15

I/O

U15

OPT

U16

I/O

U17

I/O

T16

SS T17

I/O

R17

DDQR

R16

I/O

P17

I/O

P16

N17

I/O

N16

I/O

N15

DDQL

N14

I/O

M17

DDQR

M16

I/O

M15

I/O

M14

L17

I/O

L16

L15

I/O

L14

I/O

K17

K16

I/O

K15

DDQL

K14

I/O

J17

DDQR

J16

J15

J14

H17

I/O

10R

H16

H15

I/O

H14

G17

I/O

11R

G16

I/O

10L

G15

DDQL

G14

I/O

F17

DDQR

F16

I/O

11L

F14

70T3519/99/89BF

BF208(7)

208-Pin fpBGA

Top View(8)

F15

I/O

12R

0R R11

ADS

14R

B10

C13

R10

T10

10R

U11

REPEAT

15R

5666 drw 02c

17R(1)

17L(1)

16L(2)

16R(2)

02/03/14

CNTEN R

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port Right Port Nam es

Chip E nab le s (Inp ut)

(7)

R/W

Re ad /Wri te E nab le (Inp ut)

Outp ut Enab l e (Inp ut)

- A

17L

(6)

- A

17R

(6)

Address (Input)

I/O

- I/O

35L

I/O

- I/O

35R

Data In p ut/ Ou tp ut

CLK

Clock (Input)

PL/FT

Pipeline/Flow-Through (Input)

ADS

Address Strobe Enable (Input)

CNTEN

Co unte r Enab l e (Inp ut)

REPEAT

Counter Repeat

(3)

- BE

B yte Enab l e s (9-b i t b y te s) (Inp ut)

(7)

DDQL

DDQR

P owe r (I/ O Bus ) (3. 3V o r 2. 5V)

(1)

(Inp ut)

OPT

Opti o n fo r s e l e c ti ng V

DDQX

(1,2)

(Input)

Sleep Mode pin

(4)

(Inp ut)

P owe r (2.5V)

(1)

(Input)

Gro und (0V) (Inp ut)

TDI

(5)

Te s t Da ta Inp u t

TDO

(5)

Te s t Da ta Ou tp ut

TCK

(5)

Test Logic Clock (10MHz) (Input)

TMS

(5)

Test Mode Select (Input)

TRST

(5)

Re s et (Initial iz e TA P Co ntro lle r) (Inp ut)

INT

Inter rup t F l ag (Ou tp ut)

COL

Co llision Alert (Output)

5666 tb l 01

NOTES:

1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that

port's I/Os and address controls will operate at 2.5V levels and VDDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

3. When REPEATX is asserted, the counter will reset to the last valid address loaded

via ADSX.

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins

themselves (ZZx) are not affected during sleep mode. It is recommended that

boundry scan not be operated during sleep mode.

5. Due to limited pin count, JTAG is not supported in the DR208 package.

6. Address A17x is a NC for the IDT70T3599. Also, Addresses A17x and A16x are

NC's for the IDT 70T3589.

7 . Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the

signals take two cycles to deselect.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1 . "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, REPEAT = X.

3. OE and ZZ are asynchronous input signals.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table I—Read/Write and Enable Control (1,2,3,4)

OE CLK CE

R/WZZ Byte 3

I/O

27-35

Byte 2

I/O

18-26

Byte 1

I/O

9-17

Byt e 0

I/O

0-8

MODE

X↑H X X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down

X↑X L X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down

X↑L H H H H H X L Hi gh-Z Hig h-Z Hig h-Z Hig h-Z Al l By te s Des e le cted

X↑L H H H H L L L High-Z High-Z High-Z D

W ri te to By te 0 Onl y

X↑LHHHLHLLHigh-ZHigh-Z D

High-Z Write to Byte 1 Only

X↑LHHLHHLLHigh-Z D

High-Z High-Z Write to Byte 2 Only

X↑LHLHHHLL D

High-Z High-Z High-Z Write to Byte 3 Only

X↑L H H H L L L L High-Z High-Z D

Write to Lo we r 2 By te s Only

X↑LHLLHHLL D

High-Z High-Z Write to Upper 2 bytes Only

X↑LHLLLLLL D

Write to Al l Bytes

L↑L H H H H L H L High-Z High-Z High-Z D

OUT

Re ad B yte 0 Only

L↑LHHHLHHLHigh-ZHigh-ZD

OUT

Hig h -Z Re ad B y te 1 On ly

L↑LHHLHHHLHigh-ZD

OUT

Hig h -Z Hig h-Z Re ad B y te 2 Onl y

L↑LHLHHHHL D

OUT

High-Z High-Z High-Z Read Byte 3 Only

L↑L H H H L L H L High-Z High-Z D

OUT

Re ad Lo we r 2 By tes Only

L↑LHLLHHHL D

OUT

High-Z High-Z Read Upper 2 Bytes Only

L↑LHLLLLHL D

OUT

Re ad Al l By tes

H↑X X X X X X X L Hig h-Z Hig h-Z Hig h-Z Hig h-Z Outputs Dis able d

X X X X X X X X X H High-Z High-Z High-Z High-Z Sleep Mode

566 6 t bl 0 2

Truth Table II—Address Counter Control (1,2)

NOTES:

1 . "H" = VIH, "L" = VIL, "X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.

3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.

4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.

6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded

via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

Address

Internal

Address

Internal

Address

Used CLK ADS CNTEN REPEAT

(6)

I/O

(3)

MODE

An X An ↑ L

(4)

XHD

I/O

(n) External Address Used

XAnAn + 1

↑H L

(5)

I/O

(n+1) Counter Enab le d—Internal Ad d re ss ge neratio n

X An + 1 An + 1 ↑HH HD

I/O

(n+1) External Addres s Bloc ked—Counter disabl ed (An + 1 reused)

XXAn

↑XX L

(4)

I/O

(n ) Co u nte r S e t to l as t v al i d ADS lo ad

5666 tbl 03

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage (1)

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

Grade Ambient

Temperature GND V

Commercial 0

C to + 70

C0V2.5V

100mV

Industrial -40

C to +85

C0V2.5V

100mV

5666 tbl 04

Recommended DC Operating

Conditions with VDDQ at 3.3V

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.

3 . To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin

for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated

above.

Symbol Parameter Min. Typ. Max. Unit

Core Supp ly Voltag e 2.4 2.5 2.6 V

DDQ

I/ O Supp ly Vo ltage

(3)

3.15 3.3 3.45 V

Ground 0 0 0 V

Inp u t Hig h Vo l tag e

(Ad d re s s , Co ntro l

& Data I/ O Inp uts )

(3)

2.0

____

DDQ

+ 150mV

(2)

Inp u t Hig h Vo l tag e

JTAG 1.7

____

+ 100mV

(2)

Input High Voltage -

ZZ, OPT, PIPE/ FT V

- 0.2V

____

+ 100mV

(2)

Inpu t Lo w Vo l tag e - 0. 3

(1)

____

0.8 V

Inpu t Lo w Vo l tag e -

ZZ, OPT, PIPE/ FT -0.3

(1)

____

0.2 V

5666 tbl 05b

Recommended DC Operating

Conditions with VDDQ at 2.5V

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT

pin for that port must be set to Vss(0V), and VDDQX for that port must be supplied as indicated

above.

Symbol Parameter Min. Typ. Max. Unit

Core Sup ply Voltag e 2. 4 2.5 2.6 V

DDQ

I/ O Supp ly Vo ltage

(3)

2.4 2.5 2.6 V

Ground 0 0 0 V

Inp u t Hi g h Vo l l tag e

(Ad d res s , Co ntro l &

Da ta I/ O Inp u ts )

(3)

1.7

____

DDQ

+ 100mV

(2)

Inp u t Hi g h Vo l tag e

JTAG 1.7

____

+ 100mV

(2)

Input High Voltage -

ZZ, OPT, PIPE/FT V

- 0.2V

____

+ 100mV

(2)

Inp u t Lo w Vol tage - 0. 3

(1)

____

0.7 V

Inp u t Lo w Vol tage -

ZZ, OPT, PIPE/FT -0.3

(1)

____

0.2 V

5666 tb l 05 a

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings (1)

Symbol Rating Commercial

& In dustrial Unit

TERM

Te rminal Voltag e

wi th Re s p e c t to GND -0.5 to 3.6 V

TERM(2)

DDQ

Te rminal Voltag e

wi th Re s p e c t to GND -0.3 to V

DDQ

+ 0.3 V

TERM

(2)

(INPUTS and I/O' s) Inp u t and I/ O Te rm inal

Voltage with Respect to GND -0.3 to V

DDQ

+ 0.3 V

BIAS(3)

Te mp erature Unde r Bias -55 to +125

STG

Storage Temperature -65 to +150

Junction Temperature +150

OUT

(Fo r V

DDQ

3.3V ) DC Outp ut Curre nt 50 mA

OUT

(Fo r V

DDQ

2.5V ) DC Outp ut Curre nt 40 mA

5666 tbl 06

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

2. This is a steady-state DC parameter that applies after the power supply has reached its

nominal operating value. Power sequencing is not necessary; however, the voltage on

any Input or I/O pin cannot exceed VDDQ during power supply ramp up.

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. COUT also references CI/O.

Capacitance (1)

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Symbol Parameter Conditions(2) Max. Unit

CIN Input C ap ac i tanc e V IN = 3dV 8 pF

COUT(3) Output Cap acitanc e VOUT = 3dV 10.5 pF

5666 tbl 07

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

Symbol Parameter Test Conditions

70T3519/99/89S

UnitMin. Max.

| Input Leakag e Curre nt

(1)

DDQ

= Max., V

= 0V to V

DDQ

___ 10 µA

| JTAG & ZZ Inp ut Leakag e Curre nt

(1,2)

DD =

Max.

= 0V to V

___ ±30 µA

| Outp ut Le akag e Curre nt

(1,3)

= V

or CE

= V

, V

OUT

= 0V to V

DDQ

___ 10 µA

(3. 3V) Outp ut Lo w Vol ta ge

(1)

= +4mA, V

DDQ

= Min. ___ 0.4 V

(3. 3V) Outp ut Hig h Vo ltag e

(1)

= -4mA, V

DDQ

= Mi n. 2. 4 ___ V

(2. 5V) Outp ut Lo w Vol ta ge

(1)

= +2mA, V

DDQ

= Min. ___ 0.4 V

(2. 5V) Outp ut Hig h Vo ltag e

(1)

= -2mA, V

DDQ

= Mi n. 2. 0 ___ V

5666 tb l 08

NOTES:

1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.

2. Applicable only for TMS, TDI and TRST inputs.

3. Outputs tested in tri-state mode.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

T emperature and Supply Voltage Range (3) (VDD = 2.5V ± 100mV)

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3 . Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 15mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V

CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V

"X" represents "L" for left port or "R" for right port.

6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.

7. 166MHz I-Temp is not available in the BF208 package.

8. 200Mhz is not available in the BF208 and DR208 packages.

70T3519/99/89

S200

Com'l Only

(8)

70T3519/99/89

S166

Com'l

& I nd

(7)

70T3519/99/89

S133

Com'l

& I nd

S ym bol Param eter Test Condition Version Typ.

(4)

Max. Typ.

(4)

Max. Typ.

(4)

Max. Unit

Dy nami c Op erati ng

Current (Both

Ports Ac tive)

CEL and CER= V

Outp uts Disable d,

f = f

MAX

(1)

COM'L S 375 525 320 450 260 370 mA

IND S

___ ___

320 510 260 450

SB1

(6)

Standby Current

(Bo th Po rts - TTL

Le v el Inp uts )

= CE

= V

f = f

MAX

(1)

COM'L S 205 270 175 230 140 190 mA

IND S

___ ___

175 275 140 235

SB2

(6)

Standby Current

(One Po rt - TTL

Le v el Inp uts )

"A"

= V

and CE

"B"

= V

(5)

Active Port Outputs Disabled,

f=f

MAX

(1)

COM'L S 300 375 250 325 200 250 mA

IND S

___ ___

250 365 200 310

SB3

Full Standby Current

(Bo th Po rts - CMOS

Le v el Inp uts )

Both Po rts CE

and

> V

DDQ

- 0. 2V, V

> V

DDQ

- 0. 2V

or V

< 0. 2V, f = 0

(2)

COM'L S 515 5 15 5 15 mA

IND S

___ ___

520520

SB4

(6)

Full Standby Current

(One Po rt - CMOS

Le v el Inp uts )

"A"

< 0. 2V and CE

"B"

> V

DDQ

- 0. 2V

(5)

> V

DDQ

- 0. 2V o r V

< 0. 2V

A cti v e Port, Outp uts Di s ab le d, f = f

MAX

(1)

COM'L S 300 375 250 325 200 250 mA

IND S

___ ___

250 365 200 310

Izz Sleep Mode Current

(Bo th Po rts - TTL

Le v el Inp uts )

L =

R =

f=f

MAX

(1)

COM'L S 515 5 15 5 15 mA

IND S

___ ___

520520

5666 tb l 09

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

AC T est Conditions (VDDQ - 3.3V/2.5V)

Figure 1. AC Output Test load.

Input Pulse Levels (Address & Controls)

Inp ut P ul se Le v e ls (I/ Os )

Inp ut Ri s e /Fall Ti me s

Inp ut Timi ng Re fe re nc e Le v e ls

Outp ut Re fe re nc e Le v e ls

Outp ut Load

GND to 3

0V/ GND to 2.4V

GND to 3. 0V/GND to 2.4V

2ns

1.5V/1.25V

Figure 1

5666 tbl 10

1.5V/1.25

50Ω

5666 drw 03

10pF

(Tester)

DATA

OUT

∆

Capacitance (pF) from AC Test Load

5666 drw 04

∆

tCD

(Typical, ns)

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)

NOTES:

1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when PL/FTX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1) apply

when PL/FT = Vss (0V) for that port.

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), PL/FT and OPT. PL/FT and OPT should be

treated as DC signals, i.e. steady state during operation.

3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.

4. 166MHz I-Temp is not available in the BF208 package.

5. 200Mhz is not available in the BF208 and DR208 packages.

6. Guaranteed by design (not production tested).

70T3519/99/89

S200

Com'l Only

(5)

70T3519/99/89

S166

Com'l

& I nd

(4)

70T3519/99/89

S133

Com'l

& I nd

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

CYC1

Clock Cycle Time (Flow-Through)

(1)

____

CYC2

Clock Cycle Time (Pipelined)

(1)

____

7.5

____

CH1

Clo c k Hig h Time (F lo w-Thro ug h)

(1)

____

CL1

Clo c k Low Tim e (Fl o w-Thro ug h)

(1)

____

CH2

Clock High Time (Pipelined)

(2)

____

2.4

____

CL2

Clock Low Time (Pipelined)

(1)

____

2.4

____

Address Setup Time 1.5

____

1.7

____

1.8

____

Address Hold Time 0.5

____

0.5

____

0.5

____

Chip Enab le S e tup Tim e 1. 5

____

1.7

____

1.8

____

Chip Enab le Ho ld Tim e 0. 5

____

0.5

____

0.5

____

Byte Enable Setup Tim e 1.5

____

1.7

____

1.8

____

By te E nabl e Ho ld Time 0. 5

____

0.5

____

0.5

____

R/ W Setup Tim e 1. 5

____

1.7

____

1.8

____

R/ W Ho ld Time 0. 5

____

0.5

____

0.5

____

In p ut Data S e tup Ti m e 1. 5

____

1.7

____

1.8

____

In p ut Data Ho l d Tim e 0. 5

____

0.5

____

0.5

____

SAD

ADS Setup Time 1.5

____

1.7

____

1.8

____

HAD

ADS Ho l d Tim e 0.5

____

0.5

____

0.5

____

SCN

CNTEN Setup Time 1.5

____

1.7

____

1.8

____

HCN

CNTEN Ho ld Tim e 0.5

____

0.5

____

0.5

____

SRPT

REPEAT Setup Time 1.5

____

1.7

____

1.8

____

HRPT

REPEAT Ho ld Time 0.5

____

0.5

____

0.5

____

Outp ut E nab le to Data Vali d

____

4.4

____

4.4

____

4.6 ns

OLZ

(6)

Outp ut Enab le to Output Lo w-Z 1

____

OHZ

(6)

Outp ut Enab le to Output Hig h-Z 1 3.4 1 3. 6 1 4.2 ns

CD1

Clo c k to Da ta Valid (F low-Thro ug h )

(1)

____

15 ns

CD2

Clock to Data Valid (Pipelined)

(1)

____

3.4

____

3.6

____

4.2 ns

Data Outp ut Ho l d A fter Cl o c k Hig h 1

____

CKHZ

(6)

Clock High to Output High-Z 1 3.4 1 3.6 1 4.2 ns

CKLZ

(6)

Clo c k Hi g h to Ou tput L o w-Z 1

____

INS

Inte rru p t F lag S e t Ti me

____

7ns

INR

Inte rru p t F lag Res e t Ti me

____

7ns

COLS

Co lli sio n Flag Se t Ti me

____

3.4

____

3.6

____

4.2 ns

COLR

Co lli sio n Flag Re se t Time

____

3.4

____

3.6

____

4.2 ns

ZZSC

Sleep Mode Set Cycles 2

____

cycles

ZZRC

Sleep Mode Recovery Cycles 3

____

cycles

Port-to-Port Delay

Clo c k -to -Cl o ck Offs e t 4

____

OFS

Clo c k -to -Cl o ck Offs e t fo r Co l lis io n De te c tio n P le as e re fe r to Co ll is io n De te c tio n Timi ng Tab l e o n Pag e 21

5666 tb l 11

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

An An + 1 An + 2 An + 3

CYC2

CH2

CL2

ADDRESS

CLK

(3)

DATA

OUT

CD2

CKLZ

Qn Qn+1 Qn+2

OHZ

OLZ

5666 drw 05

(1)

(4)

(1 Latency)

(5)

Timing Wa vef orm of Read Cyc le for Pipelined Operation

(FT/PIPE'X' = VIH)(1,2)

NOTES:

1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.

2. ADS = VIL, CNTEN and REPEAT = VIH.

3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).

6. "x" denotes Left or Right port. The diagram is with respect to that port.

Timing Wa veform of R ead Cyc le for Flow-through Output

(FT/PIPE"X" = VIL)(1,2,6)

An An+ 1 An + 2 An + 3

CYC1

CH1

CL1

ADDRESS

DATA

OUT

CLK

CD1

CKLZ

Qn Qn + 1 Qn + 2

OHZ

OLZ

CKHZ

5666 drw 06

(5)

(1)

BEn

(3)

(4)

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

0(B1)

ADDRESS

(B1)

CLK

DATA

OUT(B1)

CH2

CL2

CYC2

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD2

CKHZ

CD2

CKLZ

CKHZ

CD2

CKLZ

CKHZ

CKLZ

CD2

5666 drw 07

Timing Waveform of a Multi-De vice Pipelined Read (1,2)

NOTES:

1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3519/99/89 for this waveform,

and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.

2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.

Timing Waveform of a Multi-Device Flow-Through Read (1,2)

0(B1)

ADDRESS

(B1)

CLK

5666 drw 08

CD1

CKLZ

CKHZ

(1) (1)

DATA

OUT(B1)

CH1

CL1

CYC1

(1)

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD1

CKHZ

CD1

CKLZ

(1)

CKHZ

(1)

CKLZ

(1)

CD1

CKLZ

(1)

CKHZ

(1)

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

CLK

"A"

R/W

"A"

ADDRESS

"A"

DATA

IN"A"

CLK

"B"

R/W

"B"

ADDRESS

"B"

DATA

OUT"B"

(3)

CD2

MATCH

VALID

MATCH

VALID

5666 drw 09

Timing Wa v ef orm of Left P ort Write to Pipelined Right P ort R ead (1,2,4)

NOTES:

1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.

3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be

tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port

will be tCO + tCYC2 + tCD2).

4 . All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"

Timing Waveform with Port-to-Port Flow-Through Read (1,2,4)

DATA

IN "A"

CLK

"B"

R/W

"B"

ADDRESS

"A"

R/W

"A"

CLK

"A"

ADDRESS

"B"

MATCH

VALID

CD1

DATA

OUT "B"

5666 drw 10

VALID

CD1

(3)

NOTES:

1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be

tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will

be tCO + tCD1).

4 . All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4

DATA

Dn + 2

CLK

5666 drw 11

Qn Qn + 3

DATA

OUT

CD2

CKHZ

CKLZ

CD2

CH2

CL2

CYC2

READ NOP READ

(3)

(1)

WRITE

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = VIL)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5

DATA

Dn + 3Dn + 2

CLK

5666 drw 12

DATA

OUT

Qn Qn + 4

CH2

CL2

CYC2

CKLZ

CD2

OHZ

CD2

READ WRITE READ

(3)

(1)

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) (2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Timing Wa vef orm of Flo w-Through Read-to-Write-to-R ead ( OE = VIL)(2)

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4

DATA

Dn + 2

CLK

5666 drw 13

DATA

OUT

BEn

CD1

Qn + 1

CH1

CL1

CYC1

CD1

CKHZ

Qn + 3

CD1

READ NOP READ

CKLZ

(3)

(1)

WRITE

(5)

ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5

(3)

DATAIN Dn + 2

CLK

5666 drw 14

DATAOUT

CE1

BEn

tCD1

tCH1 tCL1

tCYC1

tSD tHD

tCD1 tDC

Qn + 4

tCD1

tDC

tSC tHC

tSB tHB

tSW tHW

tSA tHA

READ WRITE READ

tCKLZ

(1)

Dn + 3

tOHZ

tSW tHW

tOE

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

ADDRESS An

CLK

DATA

OUT

Qx - 1

(2)

Qx Qn Qn + 2

(2)

Qn + 3

ADS

CNTEN

CYC2

CH2

CL2

5666 drw 15

SAD

HAD

CD2

READ

EXTERNAL

ADDRESS READ WITH COUNTER COUNTER

HOLD

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

Qn + 1

Timing Waveform of Pipelined Read with Address Counter Advance (1)

NOTES:

1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH.

2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then

the data output remains constant for subsequent clocks.

Timing Waveform of Flow-Through Read with Address Counter Advance (1)

ADDRESS An

CLK

DATA

OUT

(2)

Qn Qn + 1 Qn + 2 Qn + 3

(2)

Qn + 4

ADS

CNTEN

CYC1

CH1

CL1

5666 drw 16

SAD

HAD

READ

EXTERNAL

ADDRESS

READ WITH COUNTER COUNTER

HOLD

CD1

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

ADDRESS An

CYC2

CLK

DATA

REPEAT

5666 drw 18

INTERNAL(3)

ADDRESS

ADS

CNTEN

WRITE TO

ADS

ADDRESS

ADVANCE

COUNTER

WRITE TO

An+1

ADVANCE

COUNTER

WRITE TO

An+2

HOLD

COUNTER

WRITE TO

An+2

REPEAT

READ LAST

ADS

ADDRESS

DATA

OUT

SAD

HAD

SCN

HCN

SRPT

HRPT

CD1

An+1 An+2 An+2 An An+1 An+2 An+2

An An+1 An+2 An+2

ADVANCE

COUNTER

READ

An+1

ADVANCE

COUNTER

READ

An+2

HOLD

COUNTER

READ

An+2

(4)

Timing Waveform of Write with Address Counter Advance

(Flow-through or Pipelined Inputs) (1)

Timing Wa veform of Counter Repeat (2,6)

ADDRESS An

CLK

DATA

Dn Dn + 1 Dn + 1 Dn + 2

ADS

CNTEN

CH2

CL2

CYC2

5666 drw 17

INTERNAL

(3)

ADDRESS An

(7)

An + 1 An + 2 An + 3 An + 4

Dn + 3 Dn + 4

SAD

HAD

WRITE

COUNTER HOLD WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

SCN

HCN

NOTES:

1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.

2. CE0, BEn = VIL; CE1 = VIH.

3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid

ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.

5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

T ruth T able III — Interrupt Flag (1)

Left Port Right Port

FunctionCLK

R/W

(2)

17L

-A

(3,4,5)

INT

CLK

R/W

(2)

17R

-A

(3,4,5)

INT

↑LL3FFFFX↑X X X L S e t Ri g ht INT

Flag

↑XX X X↑H L 3FFFF H Res e t Right INT

Flag

↑XX X L↑L L 3FFFE X Se t Left INT

Flag

↑H L 3FFFE H ↑X X X X Re s et Le ft INT

Flag

5666 tbl 12

NOTES:

1. INTL and INTR must be initialized at power-up by Resetting the flags.

2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.

3. A17X is a NC for IDT70T3599, therefore Interrupt Addresses are 1FFFF and 1FFFE.

4. A17X and A16X are NC's for IDT70T3589, therefore Interrupt Addresses are FFFF and FFFE.

5. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

Waveform of Interrupt Timing (2)

NOTES:

1. CE0 = VIL and CE1 = VIH

2. All timing is the same for Left and Right ports.

3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

3FFFF

CLK

(1)

ADDRESS

(3)

3FFFF

INR

CLK

R/W

ADDRESS

(3)

(1)

5666 drw 19

INT

INS

R/W

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

(3)

COLS

COLR

COLS

COLR

5666 drw 20

COL

(4)

CLK

ADDRESS

OFS

(4)

CLK

ADDRESS

OFS

Wa v eform of Collision Timing(1,2)

Both P orts Writing with Left Port Clock Leading

NOTES:

1. CE0 = VIL, CE1 = VIH.

2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.

3 . Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.

4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

Collision Detection Timing(3,4)

Cycl e Ti me

OFS

(ns )

Region 1 (ns)

(1)

Region 2 (ns)

(2)

5ns 0 - 2.8 2.81 - 4.6

6ns 0 - 3.8 3.81 - 5.6

7.5ns 0 - 5.3 5.31 - 7.1

5666 tb l 13

NOTES:

1. Region 1

Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.

2. Region 2

Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.

while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.

3. All the production units are tested to midpoint of each region.

4. These ranges are based on characterization of a typical device.

Left Port Right Port

FunctionCLK

R/W

(1)

17L

-A

(2)

COL

CLK

R/W

(1)

17R

-A

(2)

COL

↑HLMATCHH↑HLMATCHH

Both po rts reading. Not a valid co llision.

No flag output on either port.

↑HLMATCHL↑LLMATCHH

Left port reading, Right port writing.

Valid collision, flag output on Left port.

↑LLMATCHH↑HLMATCHL

Right port reading, Left port writing.

Valid collision, flag output on Right port.

↑LLMATCHL↑LLMATCHL

Both po rts writing. Valid collisio n. Flag

output on both ports.

5666 tbl 14

Truth Table IV — Collision Detection Flag

NOTES:

1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.

2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

(3)

R/W

Timing W av eform - Entering Sleep Mode (1,2)

DATA

OUT

R/W

(4)

Dn Dn+1

An+1An

(5)

Timing Wav ef orm - Exiting Sleep Mode (1,2)

NOTES:

1. CE1 = VIH.

2. All timing is same for Left and Right ports.

3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).

4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).

5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70T3519/99/89 provides a true synchronous Dual-Port Static

RAM interface. Registered inputs provide minimal set-up and hold times

on address, data, and all critical control inputs. All internal registers are

clocked on the rising edge of the clock signal, however, the self-timed

internal write pulse width is independent of the cycle time.

An asynchronous output enable is provided to ease asyn-

chronous bus interfacing. Counter enable inputs are also provided to stall

the operation of the address counters for fast interleaved

memory applications.

A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down

the internal circuitry to reduce static power consumption. Multiple chip

enables allow easier banking of multiple IDT70T3519/99/89s for depth

expansion configurations. Two cycles are required with CE0 LOW and

CE1 HIGH to re-activate the outputs.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt

flag (INTL) is asserted when the right port writes to memory location

3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the

Truth Table. The left port clears the interrupt through access of

address location 3FFFE when CEL = VIL and R/WL = VIH. Likewise, the

right port interrupt flag (INTR) is asserted when the left

port writes to memory location 3FFFF (HEX) and to clear the interrupt

flag (INTR), the right port must read the memory location 3FFFF (1FFFF

or 1FFFE for IDT70T3599 and FFFF or FFFE for IDT70T3589). The

message (36 bits) at 3FFFE or 3FFFF (1FFFF or 1FFFE for IDT70T3599

and FFFF or FFFE for IDT70T3589) is user-defined since it is an

addressable SRAM location. If the interrupt function is not used, address

locations 3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70T3599 and

FFFF or FFFE for IDT70T3589) are not used as mail boxes, but as part

of the random access memory. Refer to Truth Table III for the interrupt

operation.

Collision Detection

Sleep Mode

The IDT70T3519/99/89 is equipped with an optional sleep or low

power mode on both ports. The sleep mode pin on both ports is

asynchronous and active high. During normal operation, the ZZ pin is

pulled low. When ZZ is pulled high, the port will enter sleep mode where

it will meet lowest possible power conditions. The sleep mode timing

diagram shows the modes of operation: Normal Operation, No Read/Write

Allowed and Sleep Mode.

For normal operation all inputs must meet setup and hold times prior

to sleep and after recovering from sleep. Clocks must also meet cycle high

and low times during these periods. Three cycles prior to asserting ZZ

(ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device

must be disabled via the chip enable pins. If a write or read operation occurs

during these periods, the memory array may be corrupted. Validity of data

out from the RAM cannot be guaranteed immediately after ZZ is asserted

(prior to being in sleep). When exiting sleep mode, the device must be in

Read mode (R/Wx = VIH)when chip enable is asserted, and the chip

enable must be valid for one full cycle before a read will result in the output

of valid data.

During sleep mode the RAM automatically deselects itself. The RAM

disconnects its internal clock buffer. The external clock may continue to run

without impacting the RAMs sleep current (IZZ). All outputs will remain in

high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM

will not be selected and will not perform any reads or writes.

Collision is defined as an overlap in access between the two ports

resulting in the potential for either reading or writing incorrect data to a

specific address. For the specific cases: (a) Both ports reading - no

data is corrupted, lost, or incorrectly output, so no collision flag is output

on either port. (b) One port writing, the other port reading - the end

result of the write will still be valid. However, the reading port might

capture data that is in a state of transition and hence the reading port’s

collision flag is output. (c) Both ports writing - there is a risk that the two

ports will interfere with each other, and the data stored in memory will

not be a valid write from either port (it may essentially be a random

combination of the two). Therefore, the collision flag is output on both

ports. Please refer to Truth Table IV for all of the above cases.

The alert flag (COLX) is asserted on the 2nd or 3rd rising clock

edge of the affected port following the collision, and remains low for

one cycle. Please refer to Collision Detection Timing table on Page 21.

During that next cycle, the internal arbitration is engaged in resetting

the alert flag (this avoids a specific requirement on the part of the user

to reset the alert flag). If two collisions occur on subsequent clock

cycles, the second collision may not generate the appropriate alert

Collision detection on the IDT70T3519/99/89 represents a sig-

nificant advance in functionality over current sync multi-ports, which

have no such capability. In addition to this functionality the

IDT70T3519/99/89 sustains the key features of bandwidth and

flexibility. The collision detection function is very useful in the case

of bursting data, or a string of accesses made to sequential ad-

dresses, in that it indicates a problem within the burst, giving the user

the option of either repeating the burst or continuing to watch the alert

flag to see whether the number of collisions increases above an

acceptable threshold value. Offering this function on chip also allows

users to reduce their need for arbitration circuits, typically done in

CPLD’s or FPGA’s. This reduces board space and design complex-

ity, and gives the user more flexibility in developing a solution.

flag. A third collision will generate the alert flag as appropriate. In

the event that a user initiates a burst access on both ports with the

same starting address on both ports and one or both ports writing

during each access (i.e., imposes a long string of collisions on

contiguous clock cycles), the alert flag will be asserted and

cleared every other cycle. Please refer to the Collision Detection

timing waveform on Page 21.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Figure 4. Depth and Width Expansion with IDT70T3519/99/89

Depth and Width Expansion

The IDT70T3519/99/89 features dual chip enables (refer to Truth

Table I) in order to facilitate rapid and simple depth expansion with no

requirements for external logic. Figure 4 illustrates how to control the

various chip enables in order to expand two devices in depth.

The IDT70T3519/99/89 can also be used in applications requiring

expanded width, as indicated in Figure 4. Through combining the control

signals, the devices can be grouped as necessary to accommodate

applications needing 72-bits or wider.

NOTE:

1. A18 is for IDT70T3519, A17 is for IDT70T3599, A16 is for IDT70T3589.

5666 drw 23

IDT70T3519/99/89

Control Inputs

Control Inputs BE,

R/W,

OE,

CLK,

ADS,

REPEAT,

CNTEN

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

JT AG AC Electrical

Characteristics (1,2,3,4)

70T3519/99/89

Symbol Parameter Min. Max. Units

JCYC

JTAG Clock Input Period 100

____

JCH

J TAG Clo c k HIGH 40

____

JCL

JTAG Clock Low 40

____

J TA G Cl o c k Ri se Ti me

____

(1)

JTAG Clock Fall Time

____

(1)

JRST

JTAG Reset 50

____

JRSR

JTAG Reset Recovery 50

____

JCD

J TAG Da ta Ou tp ut

____

25 ns

JDC

J TA G Da ta Ou tp ut H o ld 0

____

JTAG Setup 15

____

JTAG Hold 15

____

5666 tb l 15

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

JTAG Timing Specifications

TCK

Device Inputs

(1)

TDI/TMS

Device Outputs

(2)

TDO

TRST

JCD

JDC

JRST

JCYC

JRSR

JCL

JCH

5666 drw 24

Figure 5. Standard JTAG Timing

NOTES:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

I nstruction Fi eld Value Descripti on

Rev isio n Numb e r (31:28) 0x 0 Res erv ed fo r v ers io n numb er

IDT Device ID (27:12) 0x330

(1)

Define s IDT p art numb e r

IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

5666 tb l 16

NOTE:

1. Device ID for IDT70T3599 is 0x331. Device ID for IDT70T3589 is 0x332.

Scan Register Sizes

Regi ster Name Bi t Si ze

Ins tr uc ti o n (IR) 4

Byp ass (BYR) 1

Id e n tifi c ati o n ( IDR) 32

Bo und ary S can (B SR) No te (3)

5666 tb l 17

System Interface Parameters

Instruction Code Description

EXTE S T 0000 Fo rc e s c o nte nts o f the b o und ary s c an c e ll s o nto the d e v ic e o utp uts

(1)

Pl ace s the b o und ary sc an reg is te r (BS R) be twe en TDI and TDO.

BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.

IDCODE 0010 Loads the ID register (IDR) with the vend or ID code and places the

HIGHZ 0100 Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state except COLx & INTx outputs.

CLAMP 0011 Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

SA MP LE/PRE LOAD 0001 Plac e s the b ound ary s can re g is te r (BS R) be twe e n TDI and TDO.

SAMPLE allows data from device inputs

(2)

to be captured in the

b o undary sc an c e lls and shi fte d se rially thro ug h TDO. PRELOAD all ows

d a ta to b e i np u t s e ri al l y in to the b o u nd a ry s c an c e l ls v i a the TDI.

RESE RVE D 0101, 0111, 1000, 1001,

1010, 1011, 1100 Several combinations are reserved. Do not use codes other than tho se

identified above.

PRIVATE 0110,1110,1101 Fo r inte rnal use o nly.

5666 tb l 18

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

Power

999

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

200

166

133

S Standard Power

XXXXX

Device

Type

9Mbit (256K x 36) 2.5V Synchronous Dual-Port RAM

4Mbit (128K x 36) 2.5V Synchronous Dual-Port RAM

2Mbit (64 x 36) 2.5V Synchronous Dual-Port RAM

70T3519

70T3599

70T3589

5666 drw 25

Speed in nanoseconds

Commercial Only

(2)

Commercial & Industrial

(1)

Commercial & Industrial

256-pin BGA (BC256)

208-pin PQFP (DR208)

208-pin fpBGA (BF208)

(3)

Green

Blank

8 Tube or Tray

Tape and Reel

NOTES:

1. 166MHz I-Temp is only available in the BC256 package.

2. 200Mhz is only available in the BC256 package.

3. Green parts available. For specific speeds, packages and powers contact your local sales office.

LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02

IDT Clock Solution for IDT70T3519/99/89 Dual-Port

IDT Dual-Port

Part N umbe r

Dual-Por t I/O Specitications Clock Specifications IDT

PLL

Clock Device

IDT

Non-PLL

Clock Device

Voltage I/O Input

Capacitance

Input Duty

Cycle

Requirement

Maximum

Frequency Jitter

Tolerance

70T3519/99/89 2.5 LVTTL 8pF 40% 200 75ps 5T2010 5T905, 5T9050

5T907, 5T9070

5666 t bl 1 9

6.42

IDT70T3519/99/89S

High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Datasheet Document History:

01/23/03: Initial Datasheet

01/30/03: Page 1 Corrected 208-pin package from TQFP to PQFP

04/25/03: Page 11 Added Capacitance Derating drawing

Page 12 Changed tINS and tINR specs in AC Electrical Characteristics table

11/11/03: Page 10 Updated power numbers in DC Electrical Characteristics table

Page 12 Added tOFS symbol and parameter to AC Electrical Characteristics table

Page 21 Updated Collision Timing waveform

Page 22 Added Collision DetectionTiming table and footnotes

Page 26 Updated HIGHZ function in System Interface Parameters table

Page 27 Added IDT Clock Solution table

03/30/04: Page 22 & 23 Clarified Sleep Mode Text and Waveforms

Page 1 & 27 Removed Preliminary status

04/22/04: Page 6 Added another sentence to footnote 4 to recommend that boundary scan not be operated during sleep mode

04/12/05: Page 27 Clarified footnotes 1 & 2 for the ordering information

Page 1 & 28 Replaced old IDT TM with new IDT TM logo

Page 1 Added green availability to features

Page 27 Added green indicator to ordering information

02/07/06: Page 7 Changed footnote 2 for Truth Table I from ADS, CNTEN, REPEAT = VIH to ADS, CNTEN, REPEAT = X

04/10/06: Page 1,3 & 12 Changed FTx/PLx to PLx/FTx on diagrams and Notes.

07/28/08: Page 10 Corrected a typo in the footnotes of DC Chars table

01/19/09: Page 27 Removed "IDT" from orderable part number

03/19/14: Page 3, 4 & 5 Removed the footnote that referenced the future use of HSTL for each of the Pin configurations

Page 3 & 27 The label BC-256 changed to BC256 in the Pin configuration, throughout the datasheet and in

the Ordering Information to accurately match the standard packge code

Page 4 & 27 The label DR-208 changed to DR208 in the Pin configuration, throughout the datasheet and in

the Ordering Information to accurately match the standard packge code

Page 5 & 27 The label BF-208 changed to BF208 in the Pin configuration, throughout the datasheet and in

the Ordering Information to accurately match the standard packge code

Page 27 Added Tape & Reel indicator to Ordering Information

Page 27 Removed obsolete clock device 5T9010 from the Clock Solution table

Product Discontinuation Notice - PDN# SP-17-02

Last time buy expires June 15, 2018

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

06/19/18: