1. Product profile
1.1 General description
Passivated ultra sensitive gate thyristor in a SOT54 plastic package.
1.2 Features
1.3 Applications
1.4 Quick reference data
2. Pinning information
EC103D1
Thyristor, sensitive gate
Rev. 02 — 31 July 2008 Product data sheet
nUltra sensitive gate nDirect interfacing to low power gate
trigger circuits
nEarth leakage circuit breakers or
Ground Fault Circuit Interrupters (GFCI)
nGeneral purpose switching
nSolid state relays nSmall engine ignition
nVDRM ≤400 V nIT(RMS) ≤ 0.8 A
nVRRM ≤400 V nIGT ≤12 µA
nITSM ≤ 8 A (t = 10 ms)
Table 1. Pinning
Pin Description Simplified outline Graphic symbol
1 anode (A)
SOT54 (TO-92)
2 gate (G)
3 cathode (K)
123
sym037
AK
G
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 2 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
3. Ordering information
4. Limiting values
Table 2. Ordering information
Type number Package
Name Description Version
EC103D1 TO-92 plastic single-ended leaded (through hole) package; 3 leads SOT54
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDRM repetitive peak off-state voltage - 400 V
VRRM repetitive peak reverse voltage - 400 V
VDSM non-repetitive peak off-state voltage - 450 V
VRSM non-repetitive peak reverse voltage - 450 V
IT(AV) average on-state current half sine wave; Tlead ≤92 °C;
see Figure 1 - 0.5 A
IT(RMS) RMS on-state current all conduction angles;
see Figure 4 and 5- 0.8 A
ITSM non-repetitive peak on-state current half sine wave; Tj=25°C prior to
surge; see Figure 2 and 3
t = 10 ms - 8 A
t = 8.3 ms - 9 A
I2tI
2t for fusing tp = 10 ms - 0.32 A2s
dIT/dt rate of rise of on-state current ITM = 2 A; IG= 10 mA;
dIG/dt = 0.1 A/µs-50A/µs
IGM peak gate current - 1 A
VRGM peak reverse gate voltage - 5 V
PGM peak gate power - 2 W
PG(AV) average gate power over any 20 ms period - 0.1 W
Tstg storage temperature −40 +150 °C
Tjjunction temperature - 125 °C
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 3 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
Form factor a = IT(RMS)/IT(AV)
Fig 1. Total power dissipation as a function of average on-state current; maximum values
f = 50 Hz
Fig 2. Non-repetitive peak on-state current as a function of the number of sinusoidal current cycles; maximum
values
003aaa111
0.0
0.2
0.4
0.6
0.0 0.1 0.2 0.3 0.4 0.5 0.6
IT(AV) (A)
Ptot
(W)
a =1.57
1.9
2.2
2.8
4conduction
angle
(degrees)
form
factor
a
30
60
90
120
180
4
2.8
2.2
1.9
1.57
α
003aaa110
4
6
2
8
10
ITSM
(A)
0
number of cycles
1 103
102
10
tp
Tj(init) = 25 °C max
ITITSM
t
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 4 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
tp≤ 10 ms
Fig 3. Non-repetitive peak on-state current as a function of pulse duration; maximum values
f = 50 Hz
Tlead = 92 °C
Fig 4. RMS on-state current as a function of surge
duration; maximum values Fig 5. RMS on-state current as a function of lead
temperature; maximum values
003aac340
10
102
103
10-5 10-4 10-3 10-2
tp (s)
ITSM
(A)
tp
Tj(init) = 25 °C max
ITITSM
t
003aaa117
0
2
4
6
8
10
12
10-2 10-1 1 10
sur ge duration (s)
IT(RMS)
(A)
003aaa116
0
0.2
0.4
0.6
0.8
1
-50 0 50 100 150
Tlead (°C)
IT(RMS)
(A)
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 5 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
5. Thermal characteristics
Table 4. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-lead) thermal resistance from junction to
lead see Figure 6 --60K/W
Rth(j-a) thermal resistance from junction to
ambient printed-circuit board
mounted; lead length 4 mm - 150 - K/W
Fig 6. Transient thermal impedance from junction to lead as a function of pulse duration
003aaa108
1
102
10−1
10
Zth(j-lead)
(K/W)
10−2
tp (s)
10−511010−1
10−2
10−410−3
tp
tp
T
P
t
T
δ =
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 6 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
6. Characteristics
Table 5. Characteristics
T
j
= 25
°
C unless otherwise stated.
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
IGT gate trigger current VD= 12 V; IT= 0.1 A; see Figure 8 -312µA
ILlatching current VD= 12 V; IGT = 0.5 mA; RGK =1kΩ;
see Figure 10 - 26mA
IHholding current VD= 12 V; IGT = 0.5 mA; RGK =1kΩ;
see Figure 11 - 25mA
VTon-state voltage IT= 1 A - 1.2 1.35 V
VGT gate trigger voltage IT= 10 mA; see Figure 7
VD= 12 V - 0.5 0.8 V
VD=V
DRM(max); Tj= 125 °C 0.2 0.3 - V
IDoff-state current VD=V
DRM(max); Tj= 125 °C;
RGK =1kΩ- 0.05 0.1 mA
IRreverse current VR=V
RRM(max); Tj= 125 °C;
RGK =1kΩ- 0.05 0.1 mA
Dynamic characteristics
dVD/dt rate of rise of off-state
voltage VDM = 0.67 × VDRM(max); Tj= 125 °C;
exponential waveform; RGK = 1 kΩ;
see Figure 12
- 150 - V/µs
tgt gate-controlled turn-on
time ITM = 2 A; VD=V
DRM(max);I
G= 10 mA;
dIG/dt = 0.1 A/µs-2-µs
tqcommutated turn-off
time VDM = 0.67 × VDRM(max); Tj= 125 °C;
ITM = 1.6 A; VR=35V;
(dIT/dt)M=30A/µs; dVD/dt = 2 V/µs;
RGK =1kΩ
- 100 - µs
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 7 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
Fig 7. Normalized gate trigger voltage as a function of
junction temperature Fig 8. Normalized gate trigger current as a function of
junction temperature
Vo= 0.895 V
Rs= 0.195 Ω
(1) Tj = 125 °C; typical values
(2) Tj = 125 °C; maximum values
(3) Tj = 25 °C; typical values
RGK =1kΩ
Fig 9. On-state current as a function of on-state
voltage Fig 10. Normalized latching current as a function of
junction temperature
Tj (°C)
−50 150100050
003aaa112
0.8
1.2
1.6
0.4
VGT
VGT(25°C)
Tj (°C)
−50 150100050
003aaa113
0.8
1.2
2.0
0
IGT
IGT(25°C)
0.4
1.6
003aaa109
VT (V)
0.4 1.61.20.8
1.0
1.5
0.5
2.0
2.5
IT
(A)
0
(1) (2) (3)
Tj (°C)
−50 150100050
003aaa114
0.8
1.2
2.0
0
IL
IL(25°C)
0.4
1.6
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 8 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
7. Package information
Epoxy meets requirements of UL 94 V-0 at 3.175 mm
RGK =1kΩ(1) RGK =1kΩ
Fig 11. Normalized holding current as a function of
junction temperature Fig 12. Critical rate of rise of off-state voltage as a
function of junction temperature; typical values
Tj (°C)
−50 150100050
003aaa115
0.8
1.2
2.0
0
IH
IH(25°C)
0.4
1.6
003aac341
Tj (°C)
0 15010050
103
102
104
dVD/dt
(V/µs)
10
(1)
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 9 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
8. Package outline
Fig 13. Package outline SOT54 (TO-92)
UNIT A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 5.2
5.0
b
0.48
0.40
c
0.45
0.38
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
L
14.5
12.7
e
2.54
e1
1.27
L1(1)
max.
2.5
b1
0.66
0.55
DIMENSIONS (mm are the original dimensions)
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
SOT54 TO-92 SC-43A 04-06-28
04-11-16
A L
0 2.5 5 mm
scale
b
c
D
b1L1
d
E
Plastic single-ended leaded (through hole) package; 3 leads SOT54
e1e
1
2
3
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 10 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
9. Revision history
Table 6. Revision history
Document ID Release date Data sheet status Change notice Supersedes
EC103D1_2 20080731 Product data sheet - EC103D1-01
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Table 3 “Limiting values” on page 2; VDSM and VRSM added.
•Table 5 “Characteristics” on page 6; dVD/dt uprated.
•Figure 4 on page 4;graph redrawn.
•Figure 6 on page 5; graph redrawn.
•Figure 11;graph added.
•Figure 12;graph added.
EC103D1-01
(9397 750 08574) 20011101 Product data - -
EC103D1_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 31 July 2008 11 of 12
NXP Semiconductors EC103D1
Thyristor, sensitive gate
10. Legal information
10.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
10.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
10.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
10.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
11. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors EC103D1
Thyristor, sensitive gate
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 31 July 2008
Document identifier: EC103D1_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
12. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Package information . . . . . . . . . . . . . . . . . . . . . 8
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
9 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
10.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
10.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
11 Contact information. . . . . . . . . . . . . . . . . . . . . 11
12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
