© 2005 Fairchild Semiconductor Corporation DS012639 www.fairchildsemi.com
August 1998
Revised March 2005
74LCX241 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
74LCX241
Low Voltage Octal Buffer/Line Driver with
5V Tolerant Inputs and Outputs
General Descript ion
The LCX2 41 is an octal buffer and line driver designed to
be employed as a m em ory add re ss dr i ver, clock driver a nd
bus oriented transmitter or receiver. The device is designed
for low v oltage (2.5V or 3.3V) VCC ap plications with capa-
bility of interfacing to a 5V signal environment.
The LCX241 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
5V tolerant inputs and outputs
2.3V – 3.6V VCC specifications provided
6.5 ns tPD max (VCC
3.3V), 10
P
A ICC max
Power-down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
Implements patented noise/EMI reduction circuitry
Latch-up per for man c e exce eds 500 mA
ESD performa nce :
Human Body Model
!
2000V
Machine Model
!
200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC and OE should be ti ed to GND through a resistor: t he
minimum value or the re sistor is de termin ed by the c urrent -sourcin g capa-
bility of the driver.
Ordering Code:
Devices also available in Tape and Ree l. Specify by append ing the suffix let t er X to th e ordering co de.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74LCX241WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX241SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX241MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LCX241MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
OE1, OE23-STATE Output Enable Inputs
I0I7Inputs
O0O7Outputs
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74LCX241
Logic Symbol
Truth Tables
H
HIGH Voltage Level
L
LOW Volt age Level
X
Immaterial
Z
High Impeda nc e
Inputs Outputs
(Pins 12, 14, 16, 18)
OE1In
LL L
LH H
HX Z
Inputs Outputs
(Pins 3, 5, 7, 9)
OE2In
HH H
HL L
LX Z
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74LCX241
Absolute Maximum Ratings(Note 2)
Recommended Operating Conditions (Note 4)
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operat ed
at these limits. The para metric value s defined in the Elec trical Cha racteristic s tables are n ot guarantee d at the A bsolute Ma ximum R atings . The Recom-
mended Operating Conditions table will def ine the con dit ions for act ual dev ic e operation.
Note 3: IO Absolu te Maximu m Rating must be observed.
Note 4: Unused input s m ust be he ld H I GH or LOW. They may not f loat.
DC Electrical Characteristics
Symbol Parameter Value Conditions Units
VCC Supply Voltage
0.5 to
7.0 V
VIDC Input Voltage
0.5 to
7.0 V
VODC Output Volta ge
0.5 to
7.0 Output in 3-STATE V
0.5 to VCC
0.5 Output in HIGH or LOW State (Note 3)
IIK DC Input Diode Current
50 VI
GND mA
IOK DC Output Diode Current
50 VO
GND mA
50 VO
VCC
IODC Output Source/Sink Current
r
50 mA
ICC DC Supply Current per Supply Pin
r
100 mA
IGND DC Ground Current per Ground Pin
r
100 mA
TSTG Storage Temperature
65 to
150
q
C
Symbol Parameter Min Max Units
VCC Supply Vo ltage Operati ng 2.0 3.6 V
Data Retention 1.5 3.6
VIInput Voltage 0 5.5 V
VOOutput Voltage HIGH or LOW State 0 VCC V
3-STATE 0 5.5
IOH/IOL Output Current VCC
3.0V
3.6V
r
24 mAVCC
2.7V
3.0V
r
12
VCC
2.3V
2.7V
r
8
TAFree-Air Operating Temperature
40 85
q
C
'
t/
'
V Input Edge Rate, VIN
0.8V
2.0V, VCC
3.0V 0 10 ns/V
Symbol Parameter Conditions VCC TA
40
q
C to
85
q
CUnits
(V) Min Max
VIH HIGH Level Input Voltage 2.3
2.7 1.7 V
2.7
3.6 2.0
VIL LOW Level Input Voltage 2.3
2.7 0.7 V
2.7
3.6 0.8
VOH HIGH Level Output Voltage IOH
100
P
A2.3
3.6 VCC - 0.2
V
IOH
8 mA 2.3 1.8
IOH
12 mA 2.7 2.2
IOH
18 mA 3.0 2.4
IOH
24 mA 3.0 2.2
VOL LOW Level Output Voltage IOL
100
P
A2.3
3.6 0.2
V
IOL
8 mA 2.3 0.6
IOL
12 mA 2.7 0.4
IOL 16 mA 3.0 0.4
IOL
24 mA 3.0 0.55
IIInput Leakage Current 0
d
VI
d
5.5V 2.3 - 3.6
r
5.0
P
A
IOZ 3-STATE Output Leakage 0
d
VO
d
5.5V 2.3 - 3.6
r
5.0
P
A
VI
VIH or VIL
IOFF Power-Off Leakage Current VI or VO
5.5V 0 10
P
A
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74LCX241
DC Electrical Characteristics (Continued)
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Note 6: Skew is de fi ned as th e absolut e valu e of the difference betwee n t he ac tu al propaga t ion delay f or any t w o separa t e outputs of t he same device. The
specif ic ation ap plies to an y o ut puts switch ing in the same direc t ion, either HIGH-to- LOW (tOSHL) or LO W-to-HIGH (t OSLH).
Dynamic Switching Characteristics
Capacitance
Symbol Parameter Conditions VCC TA
40
q
C to
85
q
CUnits
(V) Min Max
ICC Quiescent Supply Current VI
VCC or GND 2.3 - 3.6 10
P
A
3.6V
d
VI, VO
d
5.5V (Note 5) 2.3 - 3.6
r
10
'
ICC Increase in ICC per Input VIH
VCC
0.6v 2.3 - 3.6 500
P
A
Symbol Parameter
TA
40
q
C to
85
q
C, RL
500
:
Units
VCC
3.3V
r
0.3V VCC
2.7V VCC
2.5V
r
0.2V
CL
50 pF CL
50 pF CL
30 pF
Min Max Min Max Min Max
tPHL Propagation Delay 1.5 6.5 1.5 7.5 1.5 7.8 ns
tPLH Data to Output 1.5 6.5 1.5 7.5 1.5 7.8
tPZL Output Enable Time 1.5 8.0 1.5 9.0 1.5 10.0 ns
tPZH 1.5 8.0 1.5 9.0 1.5 10.0
tPLZ Output Disable Time 1.5 7.0 1.5 8.0 1.5 8.4 ns
tPHZ 1.5 7.0 1.5 8.0 1.5 8.4
tOSHL Output to Output Skew (Note 6) 1.0 ns
tOSLH 1.0
Symbol Parameter Conditions VCC TA
25
q
CUnits
(V) Typical
VOLP Quiet Output Dynamic Peak VOL CL
50 pF, VIL
3.3V, VIL
0V 3.3 0.8 V
CL
30 pF, VIH
2.5V, VIL
0V 2.5 0.6
VOLV Quiet Output Dynamic Valley VOL CL
50 pF, VIL
3.3V, VIL
0V 3.3
0.8 V
CL
30 pF, VIH
2.5V, VIL
0V 2.5
0.6
Symbol Parameter Conditions Typical Units
CIN Input Capacitance VCC
Open, VI
0V or VCC 7pF
COUT Output Capacitance VCC
3.3V, VI
0V or VCC 8pF
CPD Power Dissipation Capacitance VCC
3.3V, VI
0V or VCC, f
10 MHz 25 pF
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74LCX241
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and trec Waveforms
3-STATE Output Low Enable and
Disable Times for L o gic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
FIGURE 2. Waveform s
(Input Characteristics; f = 1MHz, tR = tF = 3ns)
Test Switch
tPLH, tPHL Open
tPZL, tPLZ 6V at VCC
3.3
r
0.3V
VCC x 2 at VCC
2.5
r
0.2V
tPZH,tPHZ GND
Symbol VCC
3.3V
r
0.3V 2.7V 2.5V
r
0.2V
Vmi 1.5V 1.5V VCC/2
Vmo 1.5V 1.5V VCC/2
VxVOL
0.3V VOL
0.3V VOL
0.15V
VyVOH
0.3V VOH
0.3V VOH
0.15V
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74LCX241
Schematic Diagram Generic for LCX Family
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74LCX241
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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74LCX241
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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74LCX241
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
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74LCX241 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLI CY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent in any componen t of a life support
device or system whose failure to perform can be rea-
sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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