TF-AHP-1070HTT-A2-1010 - AAEON ELECTRONIC

• Single device line interface for DS3 and STS-1

• Meets ANSI Standard T1.102-1993

• Meets ‘crossconnect frame’ mask requirements

• Adaptive equalization for 0 - 900 ft. of cable

• Input dynamic range of 28.5 dB (35 mV - 0.95V)

• Meets approved DS3/STS-1 jitter requirements

• Selectable B3ZS line encoding/decoding

• Line and terminal side DS3 AIS insertion

• Full loopback capability

• Coding Violation and Excessive Zeros monitors

• Loss of signal detection (per T1/M1 Spec)

• On-device Tx line buffer/filter and optional Tx line

build-out bypass

• Power-down mode

• Plastic leaded chip carrier packages:

- 44-pin (ART)

- 68-pin (A RTE) with Extended featur es

• Single +5V power supply

The Advanced DS3/STS-1 Receiver/Transmitter (ART)

device performs the receive and transmit line interface

functions required for transmission of DS3 (44.736

Mbit/s) or STS -1 (51. 840 Mb it/s) s ignal s acr oss a coa x-

ial interface.

The ART operates fro m a s in gle +5 V s upp ly with a min-

imum number of (passive) external components. Perfor-

mance monitoring, loo pbacks, DS3 AIS generatio n and

B3ZS encoding/decoding functions are included.

A single-device solution for interfacing DS3 or STS-1

signals to DSX or STS-X crossconnect frames, the ART

meets all applicable ANSI, BellCore, and ITU intercon-

nection spe cification s for a wide range of system appl i-

cations.

The ARTE has the same performance as the ART but

nine additional input and output pins provide additional

Extended features.

• Multiplexers

• DSX/STSX and performance monitoring cross

connects

• Fiber optic and microwave radio terminals

• High speed DSU

• Any DS3/STS-1 transmission application

ART Devices

Advanced DS3/STS-1 Receiver/Transm itter

ART: TXC-02020 (44-Pin)

ARTE: TXC-02021 (68-Pin)

Frame

ART and ARTE

Advanced DS3/STS-1

Receiver/Transmitter

Line Inputs Terminal Outputs

Terminal Inputs

Status/Performance

Monitors

Line Outputs

Control

LINE SIDE TERMINAL SIDE

Inputs

Document Number:

TXC-02020-MB

Ed. 5, March 1998

U.S. Patent No. 5,119,326

U.S. and/or foreign patents issued or pending

TranSwitch and TXC are registered trademarks of TranSwitch Corporation

DATA SHEET

APPLICATIONS

DESCRIPTION

FEATURES

TranSwitch Corporati on •3 Enterprise Drive ••

••

Shelton, Connecticut 06484 USA

Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

TABLE OF CONTENTS

SECTION PAGE

Block Diagram .............................................................................................................3

Block Diagram Description ..........................................................................................3

Pin Diagrams ................................ ........................................ .......................................7

Pin Descriptio ns ................. ....................... ....................................... ............................9

Absolute Maximum Ratings and Environmental Limitations ......................................13

Thermal Characteristics .............................................................................................13

Power Requiremen ts ......... ...... ..... ....................... ....................................... ...............13

Input and Output Parameters ....................................................................................14

Timing Characteristics ...............................................................................................15

Operation ..............................................................................................................21-34

Receiver Input Requirements ..............................................................................21

Interfering Tone Tolerance ..................................................................................22

Receiver Output Specifications ...........................................................................22

Transmitter Spec ifi ca tio ns ............ ...... ..... ...... ..... ....................... ..........................23

AIS and Loopback Control Signal Arbitration ......................................................27

Power-Down Mode ....................... ...... ..... ...... ..... ........................................ .........27

Jitter Transfer ......................................................................................................28

Jitter Generation ..................................................................................................29

Jitter Tolerance ....................................................................................................29

Physical Design ...................................................................................................31

Package Information ..................................................................................................35

Ordering Information ..................................................................................................36

Related Products .......................................................................................................36

Standards Documentation Sources ...........................................................................37

List of Data Sheet Changes .......................................................................................39

Documentation Update Registration Form * .........................................................43

* Please note that TranSwitch provides documentation for all of its products. Customers who are us-

ing a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing De-

partment to receive relevant updated and supplemental documentation as it is issued. They should

also contact the Applications Engineering Department to ensure that they are provided with the latest

available information about the product, especially before undertaking development of new designs

incorporating the product.

LIST OF FIGURES

Figure 1. ART and ARTE Block Diagram ..............................................................3

Figure 2. ART Pin Diagram - 44 PLCC Package ...................................................7

Figure 3. ARTE Pin Diagram - 68 PLCC Package ................................................8

Figure 4a. DS3 Interface Isolated Pulse Mask ......................................................15

Figure 4b. DS3 Interface Isolated Pulse Mask Equations .....................................16

Figure 4c. STS-1 Interface Isolated Pulse Mask Equations ..................................16

Figure 4d. STS-1 Interface Eye Diagram Mask .....................................................17

Figure 5. Receiver CLKO to Data Output Timing ................................................18

Figure 6. Receiver CLKO to Data Output Timing ................................................18

Figure 7. Transmitter Input Timing ......................................................................19

Figure 8. Coding Violation Pulse Timing ............................................................. 19

Figure 9. Excessive Zeros Pulse Timing .............................................................20

Figure 10a. Examples of B3ZS Coding ...................................................................25

Figure 10b. Examples of Idealized Transmit Input and Output Data .......................26

Figure 10c. Jitter Transfer Test Arrangement .........................................................28

Figure 10d. Jitter Generation Test Arrangement .....................................................29

Figure 11a. ART and ARTE Input Jitter Tolerance for DS3 .....................................30

Figure 11b. ART and ARTE Input Jitter Tolerance for STS-1 .................................30

Figure 12. Interference Margin Test Configuration ................................................30

Figure 13a. External Components, Pin Connections and Power/Grounds ..............33

Figure 13b. Single-Ended Receive Termination ......................................................34

Figure 13c. Suggested Single-Ended Termination Circuit for

Non-Monitor Functions ....................................................................34

Figure 14. ART in a 44-Pin Plastic Leaded Chip Carrier .......................................35

Figure 15. ARTE in a 68-Pin Plastic Leaded Chip Carrier .....................................35

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

BLOCK DIAGRAM

Figure 1. ART and ARTE Block Diagram

BLOCK DIAGRAM DESCRIPTION

Receiver Functions

The A daptive Equ alizer/AGC bloc k in the ART receiv er is used to rec over CMOS level P/N rail data fr om the

bipolar B3ZS encoded input pulses. The AGC in the ART has a dynamic range of 28.5 dB (35 mV to 0.95 volts)

which al low s th e de vi ce to b e used i n a ppl ic ati ons where the input signal is att enua ted bey ond the lev el of th e

pulse template (such as bridging repeaters or protection switches). Adaptive equalization is included to restore

the integrity of the signal after it has been attenuated by the frequency-dependent loss of up to 900 feet of

coaxia l cable. The equali zed and a utomatic gain cont rolled d ifferential sig nals are p rovided as output s on the

EYEP and EYEN pins.

Differential inputs DI1 and DI2 are provided to allow optimum performance of the device in noisy environ-

ments. Alternatively, single ended operation can be used in less critical environments or where the use of a

transfo rmer is not desired (th e input si gnal can b e AC coupl ed via a c apacitor) . When the di ffer ential mod e is

used, the AC voltage measured between DI1 and DI2 is a maximum magnitude of 0.95 volts. For single-ended

operation, the voltage measured at DI1 (DI2) relative to the DC bias voltage at DI2 (DI1) is a maximum of

+0.95 volts . Since the ART/A RTE has a sensitive rec eiver, the 4 d B attenuator of Figure 13c s hould be use d

for all new designs. The attenuator has eliminated bit errors in some designs where noise was present. For

DI1

DI2

ALOS*

Adaptive

AGC

Clock

Recovery B3ZS

Decoder

DS3 AIS

Generator

DLOS LOS

Detector

RX I/O

Control

REFCK

DO1*

DO2*

DOUT

TAIS

DSXDIS

TRLBK

RAIS

RP/RD

CLKO

B3ZSDIS

TP/TD

CLKI

RXDIS*

Line Side Terminal Side

TPLLC

RZTXIN

TEST1*

BIST

ZERO

CLKO

LNLBK

EXZ* CVEYEP* EYEN*

PRBS

Generator

PRBS

Analyzer

TEST0*

*Note: The nine signal terminations denoted with an asterisk (*) are provided in the 68-pin Extended features ARTE

version of the ART (TXC-02021). These terminations are not provided in the 44-pin ART device (TXC-02020).

Equalizer/

Control

TX I/O

Output Control

•• •

(Thick and dashed lines

show parts of loopback

paths)

TRANSMIT

RECEIVE

B3ZS

Encoder

Auxiliary

Control

Loopback Loopback

Controls

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TXC-02020-MB

Ed. 5, March 1998

input lev el s la rg er tha n 0. 95Vpeak, a s tep -d own trans for me r or resi s tiv e a tten uato r should b e used (see Fig ur e

13c for suggested attenuator topology - the circuit may be modified to provide the desired attenuation).

The PLL-based Clock Recovery block is used to recover a CMOS level clock from the equalized and sliced

input pulses. The filters are internal. When data is present, DLOS is hi gh, an d TEST1 is high, then CLKO is the

clock recovered from the data. For DLOS low and TEST1 high then CLKO is equal to DCK +/- 10%. When

TEST1 is low or TRLBK is low then the CLKO is equal to the transmit input clock, CLKI.

The B3ZS Decoder block decodes the B3ZS encoded line signal and detects coding errors and excessive

zeros in the incoming data stream. An active-high pulse is generated on the CV output whenever the input sig-

nal viol ates the B3ZS encodi ng seq uence fo r bipolar v iolations or co ntains thr ee or mor e zeros. A n activ e-low

pulse is generated on the EXZ output when a string of three or more zeros is detected, and it remains low until

a one is detected. The B3ZSDIS control input is used to bypass the decoder, but the decoder is always operat-

ing.

The R X I/O Contr ol block m ultiplex es the ap propriate si gnals to the Receiver Term inal Sid e outputs. The out-

put NRZ data formats include:

1. B3ZS decoded output recovered from the line (RP/RD contains recovered data; RN is held low).

This mode is referred to as NRZ mode.

2. Encoded outputs from the Clock Recovery block (RP/RD contains positive data; RN contains neg-

ative data). This mode allows an external device such as a DS3 Framer (TXC-03401B) to perform

the B3ZS encoding/decoding functions. B3ZSDIS ena bles thi s mod e; this is r eferred to as PN rai l

mode.

3. Loopback sig nals fro m the Transmitter term inal s ide input s. Th ese sign als a re looped throu gh the

digi tal l ogic when TRLBK is low. The receiver and clock recovery are bypassed.

4. AIS DS3 framed format signals when RAIS is low.

5. Loopback sig nals fro m the Transmitter term inal s ide input s. Th ese sign als a re looped throu gh the

clock recovery when TEST1 is low .

Outputs CLKO and CLKO provide true and inverted clocks for all formats.

The RXDIS signal forces the RP/RD and RN outputs to a low state.

The LOS Detector block generates active low outputs which indicate the absence of the line side input sig-

nal(s) . The DLO S output goes low when a str in g of 17 5 ±75 consecutive zeros occurs on the line. This output

is reset whe n the dete cted 1’s den sity is in the rang e of 28 to 33 % (or > 33% ) f or 1 75 ±75 pulse s. The AL OS

output goe s high when th e 1’s de nsity is greater than 33% and g oes low when th e 1’s density is below 28%.

Between 28 and 33% ALOS output may toggle between the active and inactive states.

The LOS detector block always uses the receiver outputs which a re based u pon the receiver inputs DI1 and

DI2 for LOS. Whe n TRB LK is low the clock recovery block is still recovering the clock from the receiver inputs.

Therefore the DLOS and ALOS signals are still valid. When TEST1 is low th e clock recovery block will recover

the cloc k fro m the in ternal ly loope d tran smitte r inp uts. In t his s tate D LOS and ALOS will be ac tive b ut may n o

longer meet the limits given above.

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

Transmitter Functions

The TX I/O Control block multiplexes the appropriate signals for use by the transmitter. The selectable formats

include:

1. Unencoded NRZ input data (TP/TD contains data, TN must be grounded). This is referred to as

NRZ mode.

2. B3ZS encoded NRZ input data (TP/TD contains positive data, TN contains negative data).

B3ZSDIS enables this mode (PN rail mode)

3. B3ZS encoded RZ input data (TP/TD contains positive data, TN contains negative data). This

mode is enabled by RZTXIN.

4. Loopback signals from the B3ZS Decoder when LNLBK is low.

5. AIS DS3 framed format signals when TAIS is low.

6. 215-1 PRBS Generator output when TEST0 is low.

The CLKI pin is the input clock for the above formats. When RZTXIN is low, the CLKI signal is ignored and

should be tied low.

The B3ZS Encoder block encodes the input NRZ mode data so as to be compliant with ANSI Specification

T1.102A. Figure 10a gives examples of B3ZS coding. The B3ZSDIS control pin can be used to bypass this

block. B3ZSDIS must be low when RZTXIN is low.

The Output Control block contains the pulse shaping circuitry required to transform the B3ZS-encoded data

into pulses that meet the mask templates and power requirements for DS3 and STS-1 line rates. An interna l

line driver is included which enables the ART to drive this signal directly from DOUT into the 75 ohm load of the

output ca ble .

The DSXDIS input determines which of two output types is enabled. DOUT is a single-ended output which

meets the DS3/STS-1 mask templates. An internal transversal filter is used to create this output. Outputs DO1

and DO2 are rectangular pulses representing level-translated versions of the input digital signal(s). An external

transformer is required to translate these pulses to the appropriate +/- polarity waveform. When DSXDIS is

high the DOUT output is enabled. When DSXDIS is lo w the DO1/ DO 2 outp uts ar e en abled. Fi gur e 1 0b shows

idealized transmitter waveforms for both output modes.

An external capacitor connected from TPLLC to the proper Analog Ground is required for the internal PLL used

to calibrate the transversal filter circuit (see Figure 13a and Note 9). Input ZERO improves the DOUT pulse

shape for short cable (0 to 100 feet) by lowering the amplitude and widening the pulse; the ZERO pin is act iv e

low.

Loopbacks and AIS Insertion

The Loopback Co ntr ol s block en abl es th e i npu t s ignal s o f th e A RT to b e looped bac k on both the l ine an d te r-

minal sides of the device. When TRLBK (Terminal Loopback) is low the TP/TD, TN, and CLKI inputs are

directly looped back to the RP/RD, RN, and CLKO pins via the RX I/O Control Block (all digital signal path).

When LNLBK i s low the DI 1/DI2 signals are looped back to the D OUT or DO1/DO 2 outputs v ia the Adaptiv e

Equalizer/AGC, Clock Recovery, B3ZS Decoder, RX I/O Control, Loopback Controls, TX I/O Control, B3ZS

Encoder, and Output Con trol blo ck s ; the lo oped da ta c ome s f ro m th e B 3ZS decode r re gardl es s o f th e s tate of

B3ZSIDS. These loop backs may be operate d independentl y or simultaneo usly. It sh ould be noted that, whe n

TRLBK is active , the CV, DLO S,EXZ and ALOS outpu t signals will s till respo nd to the line inp ut data signals

applied at pins DI1 and DI2 and will be valid.

The DS3 AIS Generator block generates a DS3 alarm indication signal (AIS) compliant with Bellcore Specifica-

tion TR191 on the li ne or termin al sides of the devic e (selected with TAIS or RAIS ). For STS-1 operation the

inputs to the device must contain the correct overhead required for path sectionalization, i.e., this block gener-

ates

DS3 format AIS onl

. AIS will override the loopback commands.

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

For the ARTE device, TEST1 will loop back the terminal input data through the B3ZS Encoder, Auxiliary Loop-

back Control, Clock Recovery and B3ZS Decoder blocks, as described below. When TXAIS is active at the

same time as TEST1, AIS will loop through this path.

Testability

The 215-1 PRBS Generator and PRBS Analyzer blocks (PRBS means Pseudo-Random Binary Sequence) are

used to pr ovide d iagnos tic f unctions such as interna l Bui lt-In Sel f Test (BIST ). When the TEST0 pin is low th e

output of the PRBS generator is driven through the TX I/O Control, B3ZS Encoder , and Output Control block to

either DOUT when DSXDIS is high or DO1/DO2 when DSXDIS is low. Th e encoder is always enabl ed when

TEST0 is low regardless of the B3ZSDIS pin state; the generator will work in NRZ mode or PN data mode.

The PR BS Analyz er monito rs the output of the RX I/O Control b lock. If th e output signals conform t o the co r-

rect 215-1 pattern and the decoder is enabled (B3ZSDIS is high) the BIST output will go high. Note that the

PRBS Analyzer always functions, regardless of the state of the TEST0 pin; whenever a valid 215-1 pattern (this

pattern c an contain a s ignificant numb er of errors a nd still be val id) appears at t he receiver outp uts the BIST

pin will go high.

The analyzer must be run with the B3ZSDIS pin held high since the PRBS analyzer works with NRZ data only.

The Generator /Analyzer comb ination can be us ed in conjunct ion with an external line- side loopback fo r diag-

nostic purposes. Since the combination of TEST0 and TEST1 low sends signals through all of the data path

blocks in the device it is particularly useful for manufacturing test.

The TEST1 pin enables an auxiliary terminal-side loopback primarily intended for use during device testing.

Signals fr om the Transmitter te rm in al- side in puts are routed thro ugh the TX I/O Cont ro l, B 3ZS En coder, Auxi l-

iary Loopback Control, Clock Recovery, B3ZS Decoder, and RX I/O Control blocks to the Receiver terminal-

side outputs.

Input Reference Clock

An input CMOS level clock at the DS3 or STS-1 rate must be applied to the REFCK input for the ART to oper-

ate. This w ill typically be supp lied by a loca l oscillator on the board. The tolerance required is ±200 ppm for

operati on wh en t he DS 3 A IS gen erator i s not used. To generate a v al id AIS pa ttern a tol er ance of ±20 ppm is

required.

Functional Differences Between the 68-Pin (ARTE) and 44-Pin (ART) Versions of ART

The 68-pin version (ARTE) has all of the features and terminations of the 44-pin version (ART), plus the follow-

ing nine additional t e rminati ons (Extended features):

DO1 Transmit output rectangular positive pulse

DO2 Transmit output rectangular negative pulse

RXDIS Receive output disable

ALOS Analog loss of signal indicator

EYEP Positive eye pattern monitor

EYEN Negative eye pattern monitor

TEST0 Enables internal PRBS generator. Selects PRBS output for transmitting

TEST1 Enables a terminal side loopback from the TP/TD and TN signals to the

receiver clock recovery, then to the receiver outputs

EXZ Excessive zeros i n the received pa ttern

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

PIN DIAGRAMS

Figure 2. ART Pin Diagram - 44 PLCC Package

AVDDRX

AGNDRX

REFCK

RAIS

BIST

DLOS

RP/RD

CLKO

DGND

TRLBK

DGND

TP/TD

CLKI

DSXDIS

ZERO

RZTXIN

TAIS

LNLBK

DVDD

DI1

DI2

TPLLC

AGNDTX

CLKO

DVDD

AVDDTX

DOUT

AGNDTX

AVDDTX

B3ZSDIS

ART

(Top View)

1135

Pin Diagram

44-Pin PLCC

AVDDRX

AGNDRX

AVDDRX

AVDDTPLL

AGNDRX

AVDDTX

AGNDTPLL

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

Figure 3. ARTE Pin Diagram - 68 PLCC Package

AVDDRX

AGNDRX

REFCK

AVDDRX

EXZ

BIST

DLOS

AVDDRX

ALOS

RP/RD

CLKO

DGND

TRLBK

RXDIS

DGND

TP/TD

CLKI

DVDD

DSXDIS

ZERO

RZTXIN

TEST0

TAIS

RAIS

LNLBK

DVDD

DI1

DI2

AGNDRX

AVDDTPLL

TPLLC

AGNDTPLL

AGNDTX

DO2

DO1

AVDDTX

TEST1 EYEP

EYEN

AGNDRX

CLKO

DVDD

AVDDTX

DOUT

AGNDTX

AVDDTX

B3ZSDIS

ARTE

Pin Diagram

(Top View)

68-Pin PLCC

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

PIN DESCRIPTIONS

Power Supply and Ground

*Note: I = Input; O = Output; P = Power

Receive Interface

Symbol

Pin No.

I/O/P* Type Name/Function

ART

(44-Pin) ARTE

(68-Pin)

AVDDTX 5

PAnalog VDD Transm it: + 5 Volt Supply ± 5%

AVDDRX 25

PAnalog VDD Receive: +5 Volt Supply± 5%

AVDDTPLL 34 51 P Analog VDD Transmit PLL: + 5 Volt Supply ± 5%

DVDD 10

17 17

PDigital VDD: + 5 Volt Supply ± 5%

AGNDTX 3

PAnalog Ground Transmit: 0 Volts Reference

AGNDRX 24

PAnalog Ground Receive: 0 Volts Reference

AGNDTPLL 36 53 P Analog Ground Transmit PLL: 0 Volts Reference

DGND 11

12 18

19 PDigital Ground: 0 Volts Reference

Symbol

Pin No.

I/O/P Type * Name/Function

ART

(44-Pin) ARTE

(68-Pin)

DI1 31 48 I Analog Data in 1, Data In 2: Line Side Inputs. For single-

ended operation DI1 or DI2 must be AC coupled to

ground via a capacitor . For differential operation both

inputs can be tied directly to a transformer.

DI2 32 49 I Analog

EYEP N/A 42 O Analog Positive Eye Pattern Monitor: Monitors non-

inverted, automatic gain controlled and equalized

output from Adaptive Equalizer/AGC block.

*See Input and Output Parameters section below for digital Ty pe definitions.

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

*Note: For TRLBK low (active), this output signal responds to the receiver input at the DI1 and DI2 pins.

EYEN N/A 41 O Analog Negative Eye Pattern Monitor: Monitors inverted,

automatic gain controlled and equalized output from

Adaptive Equalizer/AGC block.

EXZ N/A 31 O CMOS Excessive Zeros: Low when three or more consecu-

tive zeros occur in the input data stream. Valid

regardless of the state of B3ZSDIS. *

CV 18 27 O CMOS Coding Violation: High when incoming data violates

B3ZS coding for bipolar violations or when three or

more consecutive zeros occur in the input data

stream. Valid regardless of the state of B3ZSDIS. *

DLOS 20 32 O CMOS Digital LOS: Low when 175 ± 75 consecutive zeros

appear in the incoming data stream. Cleared when

ones pulse density is in the range of 28 to 33% (or >

33%) for 175 + 75 pulses. Valid regardless of the

state of TRLBK *

ALOS N/A 29 O CMOS Analog LOS: Low when pulse density < 28% for 175

± 75 pulses. Cleared when pulse density is > 33% for

175 ± 75 pulses . ALOS may toggle between active

and inactive when between 28 and 33%. Valid

regardless of the state of TRLBK.*

RP/RD 16 23 O CMOS Receiver Positive/Data: Generates B3ZS decoded

NRZ, combined data (B3ZSDIS high) or the positive

rai l portio n of PN data (B 3ZSDIS low). Held low when

RXDIS is low.

RN 15 22 O CMOS Receiver Negative: Generates negative rail portion

of PN data when B3ZSDIS is low. Held low when

B3ZSDIS is high and/or when RXDIS is low.

CLKO 14 21 O CMOS Receiver Clock Out: Receiver output clock.

CLKO 13 20 O CMOS Receiver Clock Out Inverted: Receiver inverted

output clock.

BIST 22 34 O CMOS Built-In Self Test Output: High when a valid

unframed 215-1 PRBS pattern is detected at the

receiver outputs. Valid for B3ZSDIS high only.

Symbol

Pin No.

I/O/P Type * Name/Function

ART

(44-Pin) ARTE

(68-Pin)

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

Transmit Interface

Control/Ref erence Pins (All control pins perform their enable or disable functions when set low, i.e., to 0V)

Symbol

Pin No.

I/O/P Type Name/Function

ART

(44-Pin) ARTE

(68-Pin)

TP/TD 9 16 I CMOS Transmitter Positive/Data: Input for unencoded

NRZ mode, combined data (B3ZSDIS high) or posi-

tive portion of PN rail data (B3ZSDIS low).

TN 8 15 I CMOS Transmitter Negative: Input for negative portion of

PN rail data when B3ZSDIS is low. Must be tied low

when B3ZSDIS is high.

CLKI 7 14 I CMOS Transmitter Input Clock: Transmitter clock input.

Required frequency tolerance is +/- 20 ppm of the

nominal bit rate. Required duty cycle is (50+/-10) %

TPLLC 35 52 I Analog Transmit PLL Capacitor: Capacitor pin for transver-

sal filter calibration PLL (see Figure 13a and its fol-

lowing notes for proper connection).

DO1 N/A 60 O Analog Data Out Positive: Rectangular positive pulse out-

put - enabled when DSXDIS is low.High impedance

when DSXDIS is high.

DO2 N/A 58 O Analog Data Out Negative: Rectangular negative pulse out-

put - enabled when DSXDIS is low. High impedance

when DSXDIS is high.

DOUT 38 56 O Analog Data Out: DS X filtered single-ended outp ut -

enabled when DSXDIS is high. Low with low imped-

ance when DSXDIS is low.

Symbol

Pin No.

I/O/P Type Name/Function

ART

(44-Pin) ARTE

(68-Pin)

RAIS 19 28 I TTLp Receive AIS Enable: Enables generation of DS3

framed format AIS on the receiver outputs. (See

Note 1.)

RXDIS N/A 25 I TTLp Receive Output Disable: Forces RP/RD and RN to

a low state.

TRLBK 2 1 I TTLp Terminal Loopback Enable: Enables a loopback

from the transmitter inputs to the receiver outputs via

the TX I/O Control block, the Loopback Controls

block and the RX I/O Control block.

LNLBK 1 68 I TTLp Line Loopback Enable: Enables a loopback from

the DI1/DI2 inputs to the DOUT or DO1/DO2 outputs

via the Adaptive Eq/AGC, Clock Recovery, B3ZS

Decoder, RX I/O Control, Loopback Controls, TX I/O

Control, B3ZS Encoder and Output Control blocks.

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

Note 1: DS3 AIS is defined as a valid M-frame with proper subframe structure. The data payload is a 1010 ... sequence

starting with a 1 after each overhead bit. Overhead bits are as follows: F0=0, F1=1, M0=0, M1=1; C-bits are set

to 0; X-bits are set to 1; and P-bits are set for valid parity.

No Connects

RZTXIN 43 66 I TTLp T ransmit RZ Input Enable: When low accepts B3ZS

encoded return-to-zero pulses (properly timed) on

the transmitter TP/TD and TN inputs. The CLKI and

B3ZSDIS inputs must be tied low in this mode.

B3ZSDIS 23 35 I TTLp B3ZS Codec Disable: Bypasses the internal B3ZS

Encoder and Decoder functions.

ZERO 42 65 I TTLp Transmit Zero Cable Enable: Improves DOUT out-

put mask for short cable lengths (< 100 feet). Pin is

active low.

TAIS 44 67 I TTLp Transmit AIS Enable: Enables generation of DS3

AIS on the transmitter outputs. (See Note 1.)

DSXDIS 41 64 I TTLp Transmit DSX Output Disable: Disables DOUT out-

put and enables DO1/DO2 outputs.

TEST0 N/A 30 I TTLp Test In 0: Enables internal unframed 215-1 PRBS

generator. Valid for NRZ or PN rail mode. This func-

tion is described in the Block Diagram Description,

Testability section.

TEST1 N/A 62 I TTLp Test In 1: Enables a terminal side loopback from the

TP/TD and TN signals to the receiver outputs via the

TX I/O Control, B3ZS encoder, Clock Recovery,

B3ZS Decoder, and RX I/O Control blocks.

REFCK 21 33 I CMOS Reference Clock Input: Input reference clock at the

system frequency required for device operation,

namely 44.736 MHz for DS3 applications or 51.840

MHz for STS-1 applications. Required tolerance is

± 20 ppm when DS3 AIS generation is required and

± 200 ppm otherwise. This clock can be the same as

CLKI if not using loop timing. The duty cycle must be

(50 + 10) %.

Symbol

Pin No.

I/O/P Type Name/Function

ART

(44-Pin) ARTE

(68-Pin)

NC 26

6 - 13

38-40

No Connect. NC pins are not to be connected, not

even to another NC pin, but must be left floating.

The device may be damaged if NC pins are con-

nected.

Symbol

Pin No.

I/O/P Type Name/Function

ART

(44-Pin) ARTE

(68-Pin)

- 13 -

ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

ABSOLUTE MAXIMUM RATINGS AND ENVIRONMENTAL LIMITATIONS

Notes:

1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max

values for extended periods may impair device reliability.

2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the

“CAUTION” label on the drypack bag in which devices are supplied.

THERMAL CHARACTERISTICS

POWER REQUIREM ENTS

Parameter Symbol Min Max Unit Conditions

Supply voltage VDD -0.3 +7.0 V Note 1

DC input voltage VIN -0.3 VDD + 0.3 V Note 1

Storage temperature range TS-55 150 oCNote 1

Ambient operating temperature range TA-40 85 oC 0 ft/min linear airflow

Component Temperature x Time TI 270 x 5 oC x s Note 1

Moisture Exposure Level ME 5 Level per EIA/JEDEC

JESD22-A112-A

Relative Humidity, during assembly RH 30 60 % Note 2

Relative Humidity, in-circuit RH 0 100 % non-condensing

ESD Classification ESD ±2000 V per MIL-STD-883D

Method 3015.7

Parameter Min Typ Max Unit Test Conditions

Thermal resistance, junction to

ambient, ART 44-pin PLCC -- 50 -- oC/W 0 ft/min linear airflow

Thermal resistance, junction to

ambient, ARTE 68-pin PLCC -- 40 -- oC/W 0 ft/min linear airflow

Parameter Min Typ Max Unit Test Conditions

VDD 4.75 5.0 5.25 V

IDD 180 190 mA Outputs terminated

PDD 950 1000 mW Inputs switching,

VDD=5.25

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TXC-02020-MB

Ed. 5, March 1998

INPUT AND OUTPUT PARAMETERS

INPUT PARAMETERS FOR TTLp

Note: All TTL input pads have an internal pull-up resistor.

INPUT PARAMETERS FOR CMOS

OUTPUT PARAMETERS FOR CMOS

Note: For driving traces greater than 1 inch or driving multiple loads, the ART outputs should be buffered.

Parameter Min Typ Max Unit Test Conditions

VIH 2.0 VDD + 0.3 V

VIL - 0.3 0 . 8 V

IIH -10 µAV

DD = 5.25V

IIL 550 µAV

DD = 5.25V

Input

Capacitance 10 pF

Parameter Min Typ Max Unit Test Conditions

VIH VDD - (VDD / 3) VDD + 0.3 V

VIL - 0.3 (V DD / 3) V

IIH -10 µAV

DD = 5.25V

IIL 10 µAV

DD = 5.25V

Input

Capacitance 10 pF

Parameter Min Typ Max Unit Test Conditions

VOH VDD - 0.5 V 4 mA source

VOL 0.5 V 4 mA sink

IOH - 4.0 mA VDD = 4.75V

IOL 4.0 mA VDD = 4.75V

tRISE 1.7 2.7 4.2 ns CLOAD = 15 pF

tFALL 1.9 2.8 4.1 ns CLOAD = 15 pF

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TXC-02020-MB

Ed. 5, March 1998

TIMING CHARACTERISTICS

Line Side Timing Characteristics

The line s ide signal characte ristics are design ed so that the output m eets the r equiremen ts of ANS I standar d

T1.102-1993. When terminated into a test load of 75Ω±5% using ATT 734A coaxial cable the ART device will

meet the D S3 o r STS- 1 in terfac e i so late d pu lse mas k s de fin ed be lo w in Fig ures 4a thr ou gh 4 c for a c abl e di s-

tance of 0 to 450 f eet. The pul se meas urement is made using a Hewlett P ackard HP 54502A o scilloscop e (or

equivalent) in the average mode, which is described in the HP instruction manual for this instrument. The input

to the ART/ARTE device is a 215 - 1 pseudo-random binary sequence (PRBS) signal.

For pulse sequences the output also meets the STS-1 interface eye diagram mask shown in Figure 4d.

Figure 4a. DS3 Interface Isolated Pulse Mask

MAXIMUM*

MINIMUM*

* Note: The DS3 curves shown are approximate representations of the equations in Figure 4b. The corre-

sponding STS-1 curves (not shown) would be slightly different, as indicated by the equations in Figure 4c.

**Note: UI = 1 / (System Clock Frequency)

0.8

0.6

0.4

0.2

0.0-0.4-0.8 +0.4 +0.8 +1.2 +1.6

1.0

NORMALIZED

AMPLITUDE

TIME, T, IN UNIT INTERVALS (UI)**

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TXC-02020-MB

Ed. 5, March 1998

Figure 4b. DS3 Interface Isolated Pulse Mask Equations

Figure 4c. STS-1 Interface Isolated Pulse Mask Equations

CURVE TIME IN

UNIT INTERVALS NORMALIZED

AMPLITUDE

MAXIMUM

MINIMUM

-0.85 < T< -0.68

-0.68 < T< 0.36

0.36 < T< 1.4

-0.85 < T< -0.36

-0.36 < T< 0.36

0.36 < T< 1.4

0.03

0.5 1+ sin (1+ )

[π

2 T

0.34 ]+0.03

- 0.03

0.5 1+ sin (1+ )

[π

0.18 ]- 0.03

0.08 + 0.407e -1.84( T- 0.3 6)

- 0.03

CURVE

(UPPER)

CURVE

(LOWER)

CURVE TIME IN

UNIT INTERVALS NORMALIZED

AMPLITUDE

MAXIMUM

MINIMUM

-0.85 < T< -0.68

-0.68 < T< 0.26

0.26 < T< 1.4

-0.85 < T< -0.38

-0.38 < T< 0.36

0.36 < T< 1.4

0.03

0.5 1+ sin (1+ )

[π

2 T

0.34 ]+0.03

- 0.03

0.5 1+ sin (1+ )

[π

0.18 ]- 0.03

0.1 + 0.61e -2.4(T-0.26)

- 0.03

CURVE

(UPPER)

CURVE

(LOWER)

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Ed. 5, March 1998

Figure 4d. STS-1 Interface Eye Diagram Mask

*Note: UI = 1 / (System Clock Frequency)

Note - Both inner and outer regions are symmetric about zero amplitude axis.

Outer region corner points Inner region corner points

Point Time Amplitude Point Time Amplitude

A -0.5 0.426 I -0.245 0.214

B -0.261 0.904 J -0.187 0.455

C -0.136 1.03 K -0.104 0.67

D -0.028 1.03 L -0.017 0.67

E 0.094 0.883 M 0.077 0.581

F 0.187 0.723 N 0.18 0.14

G 0.31 0.566 O -0.054 0.16

H0.50.426

0.25

0.5

0.75

-0.25

-0.5

-0.75

-1

-0.5 -0.25 0 0.25 0.5

TIME IN UNIT INTERVALS (UI) *

NORMALIZED AMPLITUDE

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Ed. 5, March 1998

Timing Diagrams

Detailed tim ing di agr am s for th e A RT and ARTE a re pr ovided in Figur es 5 thr ou gh 9 , wi th val ues o f the ti min g

intervals tabulated below them. All output times are measured with a maximum 15 pF load capacitance. Timing

parameters are measured at voltage levels of (VOH + VOL)/2 for output signals or (VIH + VIL)/2 for input signals.

Figure 5. Receiver CLKO to Data Output Timing

Figure 6. Receiver CLKO to Data Output T iming

Parameter Symbol Min Typ Max Unit

CLKO, DS3 output cloc k per io d tCYC 22.353 ns

CLKO, STS-1 output clock per io d tCYC 19.290 ns

Output clock du ty cycle, tPWH/tCYC -- 45 55 %

RP/RD/RN data output delay after CLKO↓tOD 0.5 5.0 ns

Parameter Symbol Min Typ Max Unit

CLKO, DS3 output cloc k per io d tCYC 22.353 ns

CLKO, STS-1 output clock per io d tCYC 19.290 ns

Output clock du ty cycle, tPWH/tCYC -- 45 55 %

RP/RD/RN data output delay after CLKO↑tOD 0.75 5.0 ns

tOD

CLKO

RP/RD/RN

tCYC

tPWH

(Output)

tOD

CLKO

RP/RD/RN

tCYC

tPWH

(Output)

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TXC-02020-MB

Ed. 5, March 1998

Figure 7. Transmitter Input Timing

Figure 8. Coding Violation Pulse Timing

*Note: UI = 1 / (System Clock Frequency)

Parameter Symbol Min Typ Max Unit

CLKI, DS3 input clock period tCYC 22.353 ns

CLKI, STS-1 input clock period tCYC 19.290 ns

Input clock duty cycle, tPWH/tCYC -- 40 60 %

TP/TD/TN data stable to CLKI↑ setup time tSU 3.0 ns

CLKI↑ to TP/TD/TN data stable hold time tH2.0 ns

Parameter Symbol Min Typ Max Unit*

CV pulse width tPW 0.9 1.0 1.1 UI

CV pulse high time tPWH 0.8 0.9 1.0 UI

CV delay from occurrence of violation tD7.0 UI

CV Output delay after CLKO↓tOD 0.5 5.0 nS

DON’T CARE

tCYC

CLKI

TP/TD/TN

tSU

tPWH

(Input)

tPW

tPWH

tOD

CLKO

(Output)

(Input)

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TXC-02020-MB

Ed. 5, March 1998

Figure 9. Excessive Zeros Pulse Timing

*Note: UI = 1 / (System Clock Frequency)

Parameter Symbol Min Typ Max Unit*

EXZ pulse width tPW 0.9 1.0 1.1 UI

EXZ pulse low time tPWL 0.8 0.9 1.0 UI

EXZ delay from occurrence of violation tD7.0 UI

EXZ Output delay after CLKO↓tOD 0.5 5.0 nS

EXZ tPW

tPWL

tOD

CLKO

(Output)

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TXC-02020-MB

Ed. 5, March 1998

OPERATION

Receiver Input Requirements

*Note:

Refer to Operation - Jitter Tolerance section below for DS3 and STS-1 minimum requirements and measured values.

Parameter Value

Interface Cable AT&T 728A/734A coaxial cable (or equivalent)

Bit Rate:

DS3 44.736 Mbit/s ± 20 ppm

STS-1 51.840 Mbit/s ± 20 ppm

Line Code B3ZS

Input Signal Amplitude:

Single-Ended Input 35 mVp - 0.95 Vp AC (measured relative to other pin used for DC bias, DI1 or

DI2)

Differential Input 35 mVp - 0.95 Vp AC (magnitude of differential amplitude between DI1 and DI2)

Dynamic range 28.5 dB

Cable Length 0 - 900 feet (for signals meeting the transmit masks)

Input Return Loss:

DS3 > 26 dB at 22.368 MHz with external 75Ω resistor, effect of external transformer

excluded

STS-1 > 26 dB at 25.920 MHz with external 75Ω resistor, effect of external transformer

excluded

Input Resistance > 5KΩ

Signal-to-Noise Toler-

ance No greater than either the value produced by adjacent pulses in the data stream

or ±10% of the peak pulse amplitude, whichever is greater.

Input Jitter Tolerance As defined by Figures 11a and 11b: “ART and ARTE Input Jitter Tolerance”*

Signal Coupling The input signal must be AC coupled to the ART via a transformer or capacitor.

DLOS Input level A “0” is defined as a signal of amplitude ≤15 mVp at the receiver input.

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Ed. 5, March 1998

Interfering Tone Tolerance

The ART will properl y recover clock an d pres ent error- free outpu t to the receive ter minal si de interfa ce * in the

presence of a sinusoidal interfering tone signal at the following line rates:

Interfering Tone Tolerance

*Note: See Figure 12: “Interference Margin Test Configuration”

Receiver Output Specifications

Data Rate (Mbit/s) Tone Frequency (MHz) Maximum Tone Level

51.84 25.97 -20 dB

44.736 22.4 -20 dB

Parameter Value

Clock Recovery Jitter

Peaking 1 dB maximum

Clock Recovery PLL

pull-in time < 100 µS

Sequences Reported

as Coding Violations ++, --, not B0V, not 00V, three or more consecutive zeros (excessive zeros)

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TXC-02020-MB

Ed. 5, March 1998

Transmitter Specifications

Note: A 75 ohm

5% output load is assumed in these specifications. Measurements made at transmitter

unless otherwise noted.

Parameter Value

DO1/DO2 Output Charac-

teristics:

Amplitude ±1.75 volts ±10%

Pulse Width 1/2 UI ±10%*

Rise Time 2.5 ±1.5 nS

Overshoot/Undershoot < 10%

Pulse Imbalance Ratio of positive and negative pulse amplitudes: 0.9 - 1.10.

Pulse Symmetry Output power at system frequency > 20 dB below the level at 1/2 the system

frequency

DOUT Output Characteris-

tics, ZERO high:

Pulse Shape (DS3) As defined by Figure 2 in ANSI TI.404-19XX, TIE1.2/93-004 for 50 to 450 feet.

of coaxial cable.

Pulse Shape (STS-1) As defined by Figure 4-10 in T A-NWT-000253, Issue 8, October 1993 for 50 to

450 feet of coaxial cable.

Amplitude ±0.81 volts ±10%

Output jitter 0.05 UI maximum with jitter-free input clock on CLKI

Output Power for STS-1 Between -2.7 and +4.7 dBm for a STS-1 framed pattern in a wide-band power

measurement. The measurement equipment should have a low-pass filter

having a flat passband with a cutoff frequency of 207.360 MHz. The effects of

a range of connecting coaxial cable lengths from 225 feet to 450 feet must be

included in the measurement. This measurement is defined in ANSI T1.102-

1993.

Output Power for DS3 Between -4.7 and +3.6 dBm for a framed AIS pattern in a wide-band power

measurement. The measurement equipment should have a low-pass filter

having a flat passband with a cutoff frequency of 200 MHz. The effects of a

range of connecting coaxial cable lengths from 225 feet to 450 feet must be

included in the measurement. This measurement is defined in ANSI T1.102-

1993.

All Ones Output Power

for DS3 Between -1.8 and +5.7 dBm for an all ones signal measured using a bandpass

filter with a 3 dB bandwidth of 3 kHz ±1 kHz centered at 22.368 MHz.This

measurement is defined in ANSI T1.102-1993 and TA-TSY-000342.

Pulse Imbalance Ratio of positive and negative pulse amplitudes: 0.9 - 1.10.

Pulse Symmetry Output power at system frequency > 20 dB below the level at 1/2 the system

frequency

This table is continued on

the next page.

- 24 -

ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

*Note: UI = 1 / (System Clock Frequency)

DOUT Output Characteris-

tics, ZERO low:

Pulse Shape (DS3) As defined by Figure 2 in ANSI TI.404-19XX, TIE1.2/93-004, with 0 to 100 feet

of output cable

Pulse Shape (STS-1) As defined by Figure 4-10 in TR-TSY-000253, with 0 to 100 feet of output

cable

Amplitude ±0.67 Volts ±10%

Pulse Shape (DS3) As defined by Figure 9.6 in TR-TSY-000499

Pulse Imbalance Ratio of positive and negative pulse amplitudes: 0.9 - 1.10.

Pulse Symmetry Output power at system frequency > 20 dB below the level at 1/2 the system

frequency

Parameter Value

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TXC-02020-MB

Ed. 5, March 1998

B3ZS PATTERNS

E = indicates even numbe r of pulses since last violation (V).

OD = indicates odd number of pulses since last violation (V).

V = inserted pulse, in intentional violation of alternating plus and minus pulses used for 1’s.

B = inserted pulse that follows the normal alternating Bipolar coding scheme (i.e., polarity opposite to preceding pulse).

Note: Three consecutive zeros are replaced with B0V or 00V; the substitution choice is made so that the number of pulses

between inserted violation pulses (V’s) is odd; note that sequential violations are of opposite polarity so the net

charge on the transmission medium is zero.

Figure 10a. Examples of B3ZS Coding

10101010101010101

00 11

00 00 00

11111111

VOD V E OD

VVBEOD

1010 1100 0

B3ZS

00 01000 00

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

Figure 10b. Examples of Idealized Transmit Input and Output Data

Unencoded NRZ Data (0 1 0 1 0 .....)

Encoded NRZ P & N Data (0 1 0 1 0 ....)

DO1, DO2, DOUT, CLKI and TXCABLE are the same as in the unencoded NRZ case.

DO1

DO2

CLKI

TP/TD

TXCABLE

ART

1:1

DOUT 1:1

111000

TP/TD

DO1

DO2

CLKI

TXCABLE

-1

RZ pulse

DSXDIS low

ARTE only

(Bip ola r RZ signa l)

“1”

“-1”

DOUT DSXDIS high

TXCABLE DSXDIS high

VDD/2

VDD/2 + “1”

VDD/2 - “1”

(Bip ola r RZ signa l)

TP/TD

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TXC-02020-MB

Ed. 5, March 1998

AIS and Loopback Control Signal Arbitration

* Through clock recovery block for terminal transmit data in ARTE device.

Notes: X = Don’t Care. TEST0 and TEST1 inputs are provided only on ARTE device. Digital Term Loopback means

that the terminal side transmitter inputs are looped digitally, directly to the terminal side receiver outputs.

Power-Down Mode

In order to reduc e the current requi red by the ART when either the transm itter or rece iver is not used, the fo l-

lowing power pins may be tied to ground:

ART, 44-Pin Package

Receiver-Only Operation: AVDDTX pins 5, 6, 37.

Transmitter-Only Operation: AVDDRX pins 25, 28, 30.

ARTE, 68-Pin Package:

Receiver-Only Operation: AVDDTX pins 4, 5, 54, 55.

Transmitter-Only Operation: AVDDRX pins 37, 43, 47.

Current reduction in the Power-Down Mode is as follows:

Receiver-Only Operation: IDD is reduced by approximately 10 mA.

Transmitter-Only Operation: IDD is reduced by approximately 80 mA.

Note: Power must be provided to the AVDDTPLL pin in all three operational modes (Receiver and Transmitter,

Receiver-Only, Transmitter-Only). Refer to Figure 13a and associated Note 9 for power supply connections.

TEST0 TEST1 RAIS TAIS LNLBK TRLBK RX Terminal

Output TX Line Output

1 1 1 1 1 1 Normal Normal

1110X1Normal AIS

1X10 X 0DigitalT

erm

Loopback AIS

1 X 0 1 1 X AIS Normal

1 X 0 1 0 X AIS Line Loopback

1X00 XX AIS AIS

11111 0DigitalT

erm

Loopback Normal

1 1 1 1 0 1 Normal Line Loopback

11110 0 Digital T

erm

Loopback Line Loopback

10111 1T

erm Loopback* Normal

0 1 1 X X 1 Normal PRBS

001XX1T

erm Loopback

of PRBS* PRBS

0X1XX 0DigitalT

erm

Loopback* PRBS

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Ed. 5, March 1998

Jitter Transfer

Transfer of jitter through an individual unit of digital equipment is characterized by the relationship between the

applied input jitter and the resulting output jitter as a function of frequency. This standard does not apply to Line

Interfac e Units as th e r ec over ed d ata i s eithe r re- tr an smitte d wi th a l oc al o scil lator or is re -tra ns mi tted with th e

recovered clock that has been dejittered using a dejitter PLL. In short, the recovered clock is never used to

directly transmit data. Studying the jitter tolerance curve highlights the reason why this is not possible. The

receive PLL bandwidth is dictated by the jitter tolerance curve. This prevents the clock recovery having the low

bandwidth necessary for low jitter in the low frequencies necessary for transmitting.

The measu rement ma de with the t est se tup shown in Figure 10c is for inf ormation only. The measur ement of

the jitter on CLKO is a measu re of the characterist ics of the cloc k recovery PLL, not h ow much jitter is tran s-

ferred from the receiver input to the transmitter output.

For DS3, Bellcore Technical Reference TR-TSY-000499, Issue 3, December 1989 further describes and

defines jitter transfer.

For STS-1, Bellcore Technical Reference TR-NWT-000253, Issue 2, December 1991 further describes and

defines jitter transfer.

When oper ating in a loo ped-back con figuration (throu gh the receive p ath and external ly looped back through

the trans mit path), in the absen ce of applied i nput jitter the amou nt of jitter intro duced by the ART and ARTE

device s is m axim um 0.0 65 Uni t Interv als (UIs, where U I is 1 / S yste m Clo ck Freq uency ) of pe ak-t o-peak jitter

over a jitter frequency range of 20 Hz to 1 MHz (filter with a high-pass of 10 Hz and a low-pass of 1.1 MHz).

The test a rrangem ent il lust rated in Fig ure 1 0c is r ecomme nded fo r per formanc e of t he ji tter tran sfer test. This

test is made b y addin g jitter t o the li ne side d ata inpu ts (DI1 and DI2) and mea suring th e jitter a t the terminal

side receiver clock output (CLKO). Intrinsic test equipment jitter must be subtracted from the measurement.

The receive r o utpu ts (RP /RD, RN and CLKO ) ar e lo ope d ba ck to th e trans mi tter in puts (TP/TD, TN and CL KI)

using cables. The transmitter is activated to ensure that there is no crosstalk between the transmitter and

receiver.

Figure 10c. Jitter Transfer Test Arrangement

Signal

Generator*

Termination

Jitter

Analyzer*

ART/ARTE

CLKO

* Hewlett Packard HP3784A Digital Transmission Analyzer, or equivalent.

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

Jitter Generation

Jitter gen eration is the process whereby jitter appears at the output port of an individual unit of digit al equip-

ment in the absence of applied input jitter.

For DS3, Bellcor e Te chnical R eference TR-TSY-000 499, Iss ue 3, De cember 198 9 sp ecifies th e maximum jit-

ter generation to be 1.0 UI of peak-to-peak at the output of the terminal receiver for Category I equipment.

For STS-1, Bellcore Technical Reference TR-NWT-000253 , Issue 2, December 1991 specifies the maximum

jitter generation to be 1.5 UI peak-to-peak maximum at the output of the terminal receiver for Category I equip-

ment.

The test arrangement illustrated in Figure 10d is recommended for performance of the jitter generation test.

This test is made by adding jitter to the inputs of the receiver, looping the receiver outputs to the transmitter

inputs w ith ca bl es, an d th en measuri ng the ji tter at the ou tput of the tra ns mi tter. No jit ter fi lte r is us ed . In trins ic

test equipment jitter must be subtracted from the measurement. The DS3/STS-1 jitter generation within the

ART and ARTE dev ices is 0. 145 UI peak-to-p eak maximu m for all frequencie s spec ified in the two s tandards

referenced above. Note that the test is a worst case measurement as the clock recovery PLL adds a significant

amount of ji tter. In normal operati on, the transmi t cl oc k is ei the r based on a local os c illa tor or is coming from a

VCXO of a dejitter PLL.

Figure 10d. Jitter Generation Test Arrangement

Jitter Tolerance

DS3:

Input jitter tolerance is the maximum amplitude of sinusoidal jitter at a given jitter frequency, which, when mod-

ulating the s ignal at an eq uipme nt por t, resu lts i n no more than two err ored se conds cum ulative, wher e thes e

errored seconds are integr ated over s uccessive 30-secon d measureme nt interval s, and th e jitter amp litude is

increased in each succeeding measurement interval.

Requirements for input jitter tolerance are specified in terms of compliance with a jitter mask, which represents

a combin ation of points. Eac h point co rresponds to minim um amplit ude of sinu soidal j itter at a given ji tter fre-

quency wh ic h, wh en m odul ati ng the s ignal at an e qui pme nt in put port, res ult s i n two or fe wer erro red s ec onds

in a 30-second measurement interval. Bellcore Technical Reference TR-TSY-000499, Issue 3, December

1989 specifies the minimum requirement mask for Category II equipment. The mask is shown in Figure 11a.

Jitter toler ance within the ART a nd ARTE meets and exceeds the performanc e requiremen ts. Figure 11a pre-

sents the DS3 Bellcore minimum jitter tolerance requirement mask and measured performance.

Signal

Generator* RX

ART/ARTE

* Hewlett Packard HP3784A Digital Transmission Analyzer, or equivalent.

Jitter

Analyzer*

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ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

STS-1:

For STS-1, jitter tolerance is specified in Bellcore Technical Reference TR-NWT-000253. The minimum

requirement mask is shown in Figure 11b.

Jitter toler ance within the ART and ARTE mee ts and exc eed s per fo rmanc e re qui reme nts . Figur e 11b presents

the Bellcore STS-1 minimum jitter tolerance requirement mask and measured STS-1 performance.

Figure 11a. ART and ARTE Input Jitter Tolerance for DS3

Figure 11b. ART and ARTE Input Jitter Tolerance for STS-1

Figure 12. Interference Margin Test Configuration

0.1

Sinusoidal Input

Jitter Amplitude

(UI, Peak-Peak,

Jitter

Frequency

(Hz, Log Scale)

10 2.3k 60k 300k

50 kHz

Measured*

20 dB/decade

Minimum

Required * 20 UI is th e maximu m

measurement li mit of

the test equipment.

Log Scale)

1.5

0.15

30 300 2k 20k

Measured*

Minimum

Required

Jitter Frequency

50 kHz

Sinusoidal Input

Jitter Amplitude

(UI, Peak-Peak,

* 20 UI is the maximum

measurement limit of

the test equipment.

(Hz, Log Scale)

Log Scale)

Sine Wave Generator

Digital Transmission

ART and

RX In

TX Out

Line Out

Line In

Test Set

DS3/STS-1

Passive Combiner

0 - 900 feet

ARTE

RX Out

TX In

- 31 -

ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

Physical Design

Introduction

High-frequ ency de sign techni ques mus t be employ ed for lay out of the printed circuit b oard on whi ch the ART

or ARTE device is mounted. A summary of the special design requirements is provided below . More details are

available in T ranSwitch Application Note AN-406, Guidelines for ART/ARTE Printed Circuit Board Layout, Doc-

ument No. TXC-02020-AN1.

The following guidelines and suggestions should be adhered to for a successful board design. At the DS3 and

STS-1 frequencies it is important to use high-frequency layout techniques. The techniques discussed below are

the bare minimum set that should be used.

A solid ground plan e wi th no tches s houl d b e used. ‘Sol id ’ in thi s ins ta nce me ans tha t the im ped anc e fr om any

point in the plane to the board ground connection should be low. The means having as much metal left in the

plane as possible. This is very important in regards to the location of the analog ART/ARTE device since its SNR

can be s everel y degra ded by I*Z dr ops in th ese p lanes. Notchi ng is us ed to d irect ( i.e., ste er) noi se-i nduce d

current away from th e ART/ARTE ground retu rn path. Under no circums tances should an ART/ARTE ground

region be connected to the “ground” through a trace. The trace is an impedance at high frequencies; it is not a

short. Ground currents through the trace impedance will cause voltage noise. Do not run AC signals across the

notches in the ground plane as this will produce an impedance discontinuity and signal integrity will be affected.

Try to l ocate the ART/ARTE so that no high c urrent devi ces (such as osc illators or dri vers) are located in lin e

with the ART/ARTE connection to card ground.

Do not us e a solid power plane . Break the power pl ane into r egions. Placing th e power an d ground planes in

adjacen t l ay ers wi ll p roduc e an ad ditional no is e reduc ti on due to c ap ac itive c ou pli ng. For example, a s ix- lay er

board could be signal-signal-power(ground)-ground(power)-signal-signal. The following is the list of power

regions:

1. Analog Receiver power, AVDDRX

2. Analog Transmitter power, AGNDTX

3. Analog PLL power, AVDDTPLL

4. ART digital power, VDD

5. Board VDD

If ferrite be ads ar e u sed in the analog p owe r lin es, as is reco mme nde d, th er e wi ll be a n arr owin g of the p ower

plane at the ferrite bead. If the beads are not used, use as wide a path as possible back to the common

connecting point. It should be noted that not using the beads may cause a large SNR reduction in the

transcei ver. Th e effect is highly boar d- dep end ent and not easil y pr edi ct abl e.

Figures 13a an d 1 3b s ho w th e r ecom mended ground and p ower con nec ti ons fo r the ART/A R TE . The pas s ive

components should be connected to the indicated ground (a solid plane with possible notching). Connecting the

components to the wrong point will inject a noise signal into that part of the transceiver. Do not use a long trace

to connect components to ground; use as short a trace as possible. The decoupling capacitors should be placed

as close as feasible

to their associated chip pins on the same board side as the ART/ARTE chip. Put a

decoupling capacitor at every power pin. Placing the capacitors on the other side of the board may have a

measurable impact on device performance. Again, it should be pointed out that a board trace is an impedance,

not a short. The other passive components should also be placed

as close as

ossible

to their associated pins.

The ART/AR TE termina l side CMOS output drive rs have a drive of 4 mA . If drivi ng long tr aces ( the longe r the

trace, the greater the parasitic capacitance) or multiple loads these outputs may need to be buffered.

The notes f ollowing Figu re 13c give exter nal compon ent values and t ypes, a listin g of the va rious power and

ground connections, and other information.

- 32 -

ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

General Comments

A board trace at high frequencies is not a zero-impedance metal interconnection. It is a distributed L/C net-

work. The values of the L and C (per unit length) parasitic components are determined by trace geometry

(width and height) and the surrounding material (which determines the dielectric constant). A trace with a given

geome try will h ave a dif ferent impedan ce if it i s on an ou tside b oard laye r from the same t race pla ced ins tead

in an internal layer. Large branches (stubs) off a main trace will change the impedance at the branch point due

to the effect of impedances in parallel, so branch lengths should be kept to a minimum (less than a quarter

wavelength). This is very important for clock lines where load/source impedance mismatches can cause

severe r inging , which le ads to ti ming pro blems . Use buffer s to redu ce the d iffic ulty of dis tributi ng a si gnal wi th

multiple loads.

If relay s a re us ed t o s witc h t he tr an sc ei ve rs i n an d ou t, us e th e 50 ohm sh ie lde d v ar iet y to mi nim ize c r os sta lk,

especially from the power used to energize the relay. Match the impedance of the board traces of the transmit-

ter outputs and receiver inputs to the transmission line impedance (75 ohms if a 1:1 transformer is used) to

minimize reflections. Physically separate the analog signal lines from the digital lines. Route the differential

receiver lines side by side to make coupled noise common-mode. Avoid ninety-degree corners in the board

lands; k ee p l and s a s strai gh t an d s hort as possi bl e. U se ter minating (i.e ., 51 oh m s er ie s-da mpi ng) r esi sto rs in

the digital signals lines where appropriate (i.e., if the line is longer than a quarter wavelength of the highest sig-

nal frequency of importance, reflections will start causing problems).

The above comments are guidelines only. High-frequency board layout is difficult and must be done with care.

A bad board layout will reduce the SNR of the transceiver and cause timing problems with the board logic, per-

haps to the point of requiring a complete board redesign.

- 33 -

ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

Figure 13a. External Components, Pin Connections and Power/Grounds

DI1

DI2

ALOS*

DLOS

LNLBK

TEST0*

EXZ*

REFCK

DO1*

DO2*

ZERO

TAIS

DSXDIS

TRLBK

RZTXIN

RAIS

RP/RD

CLKO

B3ZSDIS TP/TD

CLKI

RXDIS*

Line Side Terminal Side

Receiver Outputs

Transmitter Inputs

Status/Perf.

Control S ignals

Reference Clock

Testability/Diagnostics

Line Input

SQR Output

ART

DVDD

DGND

TPLLC

TEST1*

BIST

DSX Output

DOUT

T1**

T2**

R5 (Note 5)

EYEN*

EYEP*

CLKO

36, 5%

AVDDRX

AGNDRX

Monitor Signals

ARTE

0.1

36, 5%

1 : 1

0.1

GRX

T3**(Note 3)

GTX GD GRX

Differential Input

Termination (Notes 4, 6, 11)

AGNDTX

AVDDTPLL AVDDTX

AGNDTPLL

GRX (Note 9)

GRX

GRX or GTX

+5V

Ferrite Bead

10 +

0.1

Ferrite Bead

0.1

GRX

Ferrite Bead

0.1 GTX

(Note 9)

See next page for *, **

and numbered Notes.

(Note 9)

(Notes 7, 8)

0.1

Note: All capacitor values

are in microfarads, all

resistor values are in

ohms, unless otherwise

marked. Place compo-

nents

to their

respective pins.

Note 10

0.1

- 34 -

ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

Figure 13b. Single-Ended Receive Termination

Figure 13c. Suggested Single-Ended Termination Circuit for Non-Monitor Functions

NOTES:

1. *The nine device signal terminations marked with asterisks are provided for the ARTE but not for the ART.

2. **T1, T2 and T3 are Coilcraft WB1010 Transformers or equivalent.

3. T3 is optional. T3 is only required if the ARTE square wave transmit output is used (DO1, DO2).

4. R1 and R2 are 1% resistors.

5. R5 and R6 are only required for ARTE monitoring purposes, not for device operation.

6. Differential Input Termination for line inputs can be replaced by circuit in Figure 13b for single-ended operation.

7. Fair Rite #2743002111 or equivalent should be used for each ferrite bead.

8. Locate ferrite bead/capacitor decoupling as close as possible to ART and ARTE. Locate the 10 µF capacitor as

close as possible to the ferrite bead, an d place an individual 0.1 µF capac it or as clo se as pos si ble to each voltag e

pin on ART/ARTE.

9. Power Connections for Transmit PLL: Avoid trace for power connection if possible. Use a decoupling capacitor.

Connect AVDDTPLL, AGNDTPLL and TPLLC as follows:

10. GD=Digital Ground; GRX=Analog Receive Ground; GTX=Analog Transmit Ground.

11. Figure 13c is the single-ended circuit suggested for future board designs in a non-monitor function. The resistive

attenuator will decrease high frequency noise and prevent the AGC from operating near its linear range limits.

Operat ing Mode AVDDTPLL Connection AGNDTPLL TPLLC Cap Ground

Receive and Transmit

Receive Only

Transmit Only

AVDDRX

AVDDTX

GRX

GTX

GRX

GTX

0.1

0.1 DI1

DI2

GRX

Line Inputs

0.1

0.1 DI1

DI2

GRX

Line Inputs

27 pF

- 35 -

ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

PACKAGE INFORMATION

ART is available in a 44-pin plastic leaded chip carrier (ART) and also with extended features in a 68-pin plas-

tic leaded chip carrier (ARTE). Both packages are suitable for socket or surface mounting. All dimensions

shown are in inches and are nominal values unless otherwise indicated.

Figure 14. ART in a 44-Pin Plastic Leaded Chip Carrier

Figure 15. ARTE in a 68-Pin Plastic Leaded Chip Carrier

TRANSWITCH

406

2818

0.500 SQ.

0.653 SQ.

0.075 0.149

0.170

BOTTOM VIEW

T O P VIEW

40 6

28 18

0.690 SQ.

0.017

typ.

0.050

typ.

TXC-02020-AIPL

0.953 SQ.

0.800 SQ.

T O P VIEW BOTTOM VIEW

0.990 SQ. 0.170

0.149

TRANSWITCH

961

27 43

0.075 0.050

typ.

0.017

typ.

TXC-02021-AIPL

- 36 -

ART and ARTE

TXC-02020-MB

Ed. 5, March 1998

ORDERING INFORMATION

ART Part Number: TXC-02020-AIPL 44-pin plastic leaded device carrier

ARTE Part Number: TXC-02021-AIPL 68-pin plastic leaded device carrier