100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 kX pull-down resistors. Y Y Y Y Y Y 35% power reduction of the 100131 2000V ESD protection Pin/function compatible with 100131 Voltage compensated operating range e b4.2V to b 5.7V Available to industrial grade temperature range Available to MIL-STD-883 Logic Symbol Pin Names Description CP0 -CP2 CPC D0 -D2 CD0 -CD2 SDn MR MS Q0-Q2 Q0 -Q2 Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs TL/F/10262 - 1 Connection Diagrams 24-Pin DIP/SOIC 28-Pin PCC 24-Pin Quad Cerpak TL/F/10262 - 3 TL/F/10262-2 C1995 National Semiconductor Corporation TL/F/10262 TL/F/10262 - 4 RRD-B30M105/Printed in U. S. A. 100331 Low Power Triple D Flip-Flop July 1992 Logic Diagram TL/F/10262 - 5 Truth Tables (Each Flip-Flop) Synchronous Operation Inputs Asynchronous Operation Outputs Inputs CPC MS SDn MR CDn Qn(t a 1) Dn CPn X X X X X X Dn CPn L H L H L L L L L L L L L L L L L L L L L H L H X X X L H X L X H L L L L L L Qn(t) Qn(t) Qn(t) H e HIGH Voltage Level L e LOW Voltage Level X e Don't Care U e Undefined t e Time before CP Positive Transition t a 1 e Time after CP Positive Transition L e LOW to HIGH Transition 2 Outputs CPC MS SDn MR CDn Qn(t a 1) X X X H L H L H H H L U Absolute Maximum Ratings Recommended Operating Conditions Above which the useful life may be impaired (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65 C to a 150 C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic Pin Potential to Ground Pin (VEE) Input Voltage (DC) Output Current (DC Output HIGH) Case Temperature (TC) Commercial Industrial Military 0 C to a 85 C b 40 C to a 85 C b 55 C to a 125 C Supply Voltage (VEE) a 175 C a 150 C b 5.7V to b 4.2V b 7.0V to a 0.5V VEE to a 0.5V b 50 mA ESD (Note 2) s 2000V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e 0 C to a 85 C (Note 3) Parameter Min Typ Max Units VOH Symbol Output HIGH Voltage b 1025 b 955 b 870 mV VOL Output LOW Voltage b 1830 b 1705 b 1620 mV VOHC Output HIGH Voltage b 1035 VOLC Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current IEE Power Supply Current mV Conditions VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V VIN e VIH (Min) or VIL (Max) Loading with 50X to b2.0V b 1610 mV b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs 0.5 b 122 mA VIN e VIL (Min) 240 mA VIN e VIH (Max) b 65 mA Inputs Open Note 3: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. 3 Commercial Version (Continued) DIP AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND (Continued) Symbol TC e 0 C Parameter Min Max TC e a 25 C TC e a 85 C Min Min Max 375 Units fmax Toggle Frequency 375 tPLH tPHL Propagation Delay CPC to Output 0.75 2.00 0.75 2.00 0.75 2.00 ns tPLH tPHL Propagation Delay CPn to Output 0.75 2.00 0.75 2.00 0.75 2.00 ns tPLH tPHL Propagation Delay CDn, SDn to Output 0.70 1.70 0.70 1.70 0.70 1.80 MHz Conditions Figures 2 and 3 Figures 1 and 3 CPn, CPC e L ns tPLH tPHL tPLH tPHL 375 Max 0.70 Propagation Delay MS, MR to Output 2.00 0.70 2.00 0.70 2.00 CPn, CPC e H CPn, CPC e L 1.10 2.60 1.10 2.60 1.10 2.60 1.10 2.80 1.10 2.80 1.10 2.80 0.35 1.30 0.35 1.30 0.35 1.30 Figures 1 and 4 ns tPLH tPHL CPn, CPC e H tTLH tTHL Transition Time 20% to 80%, 80% to 20% tS Setup Time Dn CDn, SDn (Release Time) MS, MR (Release Time) 0.40 1.30 2.30 0.40 1.30 2.30 0.40 1.30 2.30 ns tH Hold Time Dn 0.5 0.5 0.7 ns Figure 5 tpw(H) Pulse Width HIGH CPn, CPC, CDn, SDn, MR, MS 2.00 2.00 2.00 ns Figures 3 and 4 ns Figures 1, 3 and 4 Figure 5 Figure 4 SOIC, PCC and Cerpak AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e 0 C Min Max TC e a 25 C TC e a 85 C Min Min Max Toggle Frequency 400 tPLH tPHL Propagation Delay CPC to Output 0.75 1.80 0.75 1.80 0.75 1.80 ns tPLH tPHL Propagation Delay CPn to Output 0.75 1.80 0.75 1.80 0.75 1.80 ns tPLH tPHL Propagation Delay CDn, SDn to Output 0.70 1.50 0.70 1.50 0.70 1.60 tPLH tPHL tPLH tPHL Propagation Delay MS, MR to Output 400 Units fmax tPLH tPHL 400 Max MHz Conditions Figures 2 and 3 Figures 1 and 3 CPn, CPC e L ns 0.80 1.80 0.70 1.80 0.70 1.80 CPn, CPC e H 1.10 2.40 1.10 2.40 1.10 2.40 CPn, CPC e L 1.10 2.60 1.10 2.60 1.10 2.60 ns 4 CPn, CPC e H Figures 1 and 4 Commercial Version (Continued) SOIC, PCC and Cerpak AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND (Continued) Symbol Parameter TC e 0 C TC e a 25 C TC e a 85 C Min Max Min Max Min Max 0.35 1.10 0.35 1.10 0.35 1.10 Units Conditions tTLH tTHL Transition Time 20% to 80%, 80% to 20% tS Setup Time Dn CDn, SDn (Release Time) MS, MR (Release Time) 0.30 1.20 2.20 0.30 1.20 2.20 0.30 1.20 2.20 ns tH Hold Time Dn 0.5 0.5 0.7 ns Figure 5 tpw(H) Pulse Width HIGH CPn, CPC, CDn, SDn, MR, MS 2.00 2.00 2.00 ns Figures 3 and 4 tPLH tPHL Propagation Delay CPC to Output 0.75 1.40 0.75 1.40 0.80 1.50 ns tPLH tPHL Propagation Delay CPn to Output 0.70 1.40 0.75 1.40 0.80 1.50 ns tPLH tPHL Propagation Delay CDn, SDn to Output 0.70 1.50 0.70 1.50 0.80 1.60 tPLH tPHL tPLH tPHL Propagation Delay MS, MR to Output tPLH tPHL tOSHL tOSHL tOSLH tOSLH tOST tOST tps tps ns Figures 1, 3 and 4 Figure 5 Figure 4 ns Figures 1 and 3 PCC Only CPn, CPC e L PCC Only 0.80 1.70 0.80 1.70 0.80 1.80 CPn, CPC e H PCC Only 1.10 2.00 1.10 2.00 1.20 2.10 CPn, CPC e L PCC Only 1.20 2.10 1.20 2.10 1.30 2.20 ns Figures 1 and 4 CPn, CPC e H PCC Only Maximum Skew Common Edge Output-to-Output Variation Common Clock to Output Path 100 100 100 ps PCC Only (Note 1) Maximum Skew Common Edge Output-to-Output Variation CPn to Output Path 235 235 235 ps PCC Only (Note 1) Maximum Skew Common Edge Output-to-Output Variation Common Clock to Output Path 120 120 120 ps PCC Only (Note 1) Maximum Skew Common Edge Output-to-Output Variation CPn to Output Path 275 275 275 ps PCC Only (Note 1) Maximum Skew Opposite Edge Output-to-Output Variation Common Clock to Output Path 125 125 125 ps PCC Only (Note 1) Maximum Skew Opposite Edge Output-to-Output Variation CPn to Output Path 265 265 265 ps PCC Only (Note 1) Maximum Skew Pin (Signal) Transition Variation Common Clock to Output Path 90 90 90 ps PCC Only (Note 1) Maximum Skew Pin (Signal) Transition Variation CPn to Output Path 90 90 90 ps PCC Only (Note 1) Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design. 5 Industrial Version PCC DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b40 C to a 85 C (Note) Symbol TC e b40 C Parameter Min VOH TC e 0 C to a 85 C Max Min Units Conditions Max Output HIGH Voltage b 1085 b 870 b 1025 b 870 mV VOL Output LOW Voltage b 1830 b 1575 b 1830 b 1620 mV VOHC Output HIGH Voltage b 1095 VOLC Output LOW Voltage b 1610 mV VIH Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current IEE Power Supply Current b 1035 mV b 1565 VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V VIN e VIH (Min) or VIL (Max) Loading with 50X to b2.0V b 1170 b 870 b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs b 1830 b 1480 b 1830 1475 mV Guaranteed LOW Signal for All Inputs mA VIN e VIL (Min) 0.5 0.5 300 b 122 b 60 b 122 240 mA VIN e VIH (Max) b 65 mA Inputs Open Note: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. PCC AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e b40 C TC e a 25 C TC e a 85 C Min Min Min Max Max Conditions Toggle Frequency 375 tPLH tPHL Propagation Delay CPC to Output 0.75 1.80 0.75 1.80 0.75 1.80 ns tPLH tPHL Propagation Delay CPn to Output 0.70 1.80 0.75 1.80 0.75 1.80 ns tPLH tPHL Propagation Delay CDn, SDn to Output 0.60 1.50 0.70 1.50 0.70 1.60 0.70 1.80 0.70 1.80 0.70 1.80 CPn, CPC e H CPn, CPC e L tPLH tPHL Propagation Delay MS, MR to Output tPLH tPHL 400 MHz Figures 2 and 3 fmax tPLH tPHL 400 Units Max Figures 1 and 3 CPn, CPC e L ns 1.10 2.40 1.10 2.40 1.10 2.40 1.10 2.60 1.10 2.60 1.10 2.60 0.20 1.40 0.35 1.10 0.35 1.10 ns CPn, CPC e H tTLH tTHL Transition Time 20% to 80%, 80% to 20% tS Setup Time Dn CDn, SDn (Release Time) MS, MR (Release Time) 1.00 1.50 2.50 0.30 1.20 2.20 0.30 1.20 2.20 ns tH Hold Time Dn 0.7 0.5 0.7 ns Figure 5 tpw(H) Pulse Width HIGH CPn, CPC, CDn, SDn, MR, MS 2.00 2.00 2.00 ns Figures 3 and 4 6 ns Figures 1, 3 and 4 Figure 5 Figure 4 Figures 1 and 4 Military Version DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b55 C to a 125 C Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage VOHC VOLC Output HIGH Voltage Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current Power Supply Current Max Units TC b 1025 b 870 mV 0 C to a 125 C b 1085 b 870 mV b 55 C b 1830 b 1620 mV 0 C to a 125 C b 1830 b 1555 mV b 55 C Conditions Notes VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V 1, 2, 3 VIN e VIH (Min) or VIL (Max) Loading with 50X to b2.0V 1, 2, 3 0 C to b 1035 mV b 1085 mV b 55 C b 1610 mV 0 C to a 125 C b 1555 mV b 55 C Guaranteed HIGH Signal for all Inputs 1, 2, 3, 4 1, 2, 3, 4 Output LOW Voltage VIH IEE Min a 125 C b 1165 b 870 mV b 55 C to a 125 C b 1830 b 1475 mV b 55 C to a 125 C Guaranteed LOW Signal for all Inputs mA b 55 C to a 125 C VEE e b4.2V VIN e VIL (Min) 1, 2, 3 VEE e b5.7V VIN e VIH (Max) 1, 2, 3 Inputs Open 1, 2, 3 0.50 b 130 0 C to 240 mA 340 mA b 55 C b 50 mA b 55 C to a 125 C a 125 C Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at b 55 C, a 25 C, and a 125 C, Subgroups, 1, 2, 3, 7 and 8. Note 3: Sampled tested (Method 5005, Table I) on each manufactured lot at b 55 C, a 25 C, and a 125 C, Subgroups A1, 2, 3, 7 and 8. Note 4: Guaranteed by applying specified input condition and testing VOH/VOL. 7 Military Version (Continued) AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e b55 C TC e a 25 C Min Min Max Max Min Units MHz Figures 2 and 3 Toggle Frequency 400 tPLH tPHL Propagation Delay CPC to Output 0.50 2.20 0.60 2.00 0.50 2.40 ns tPLH tPHL Propagation Delay CPn to Output 0.50 2.20 0.60 2.00 0.50 2.40 ns tPLH tPHL Propagation Delay CDn, SDn to Output 0.50 2.20 0.60 2.00 0.50 2.40 tPLH tPHL Propagation Delay MS, MR to Output tPLH tPHL Conditions Notes Max fmax tPLH tPHL 400 TC e a 125 C 400 4 Figures 1 and 3 CPn, CPC e L ns 0.50 2.40 0.60 2.10 0.50 2.50 0.70 2.70 0.80 2.60 0.80 2.90 CPn, CPC e H Figures 1, 2, 3 1 and 4 CPn, CPC e L ns 0.70 2.90 0.80 2.80 0.80 3.10 0.20 1.40 0.20 1.40 0.20 1.40 CPn, CPC e H tTLH tTHL Transition Time 20% to 80%, 80% to 20% ts Setup Time Dn CDn, SDn (Release Time) MS, MR (Release Time) 1.00 1.50 2.50 0.80 1.30 2.30 0.90 1.60 2.50 ns th Hold Time Dn 1.50 1.30 1.60 ns Figure 5 tpw(H) Pulse Width HIGH CPn, CPC, CDn, SDn, MR, MS 2.00 2.00 2.00 ns Figures 3 and 4 ns Figures 1, 3 and 4 Figure 5 4 Figure 4 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at a 25 C. Temperature only, Subgroup A9. Note 3: Sample tested (Method 5005, Table I) on each Mfg. lot at a 25 C, Subgroup A9, and at a 125 C, and b 55 C Temp., Subgroups A10 and A11. Note 4: Not tested at a 25 C, a 125 C and b 55 C Temperature (design characterization data). 8 Test Circuits TL/F/10262 - 6 FIGURE 1. AC Test Circuit TL/F/10262 - 7 FIGURE 2. Toggle Frequency Test Circuit Notes: VCC, VCCA e a 2V, VEE e b 2.5V L1 and L2 e Equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0.1 mF from GND to VCC and VEE All unused outputs are loaded with 50X to GND CL e Fixture and stray capacitance s 3 pF 9 Switching Waveforms TL/F/10262 - 8 FIGURE 3. Propagation Delay (Clock) and Transition Times TL/F/10262 - 9 FIGURE 4. Propagation Delay (Resets) TL/F/10262 - 10 FIGURE 5. Data Setup and Hold Time Note: ts is the minimum time before the transition of the clock that information must be present at the data input. Note: th is the minimum time after the transition of the clock that information must remain unchanged at the data input. 10 Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100331 D C QB Device Type (Basic) Special Variation QB e Military grade device with environmental and burn-in processing. Package Code D e Ceramic DIP F e Quad Cerpak Q e Plastic Leaded Chip Carrier (PCC) P e Plastic DIP S e Small Outline (SOIC) Temperature Range C e Commercial (0 C to a 85 C) I e Industrial (b40 C to a 85 C) (PCC Only) M e Military (b55 C to a 125 C) 11 Physical Dimensions inches (millimeters) 24-Lead Ceramic Dual-In-Line Package (0.400x Wide) (D) NS Package Number J24E 24-Lead Molded Package (0.300x Wide) (S) NS Package Number M24B 12 Physical Dimensions inches (millimeters) (Continued) 24-Lead Plastic Dual-In-Line Package (P) NS Package Number N24E 28-Lead Plastic Chip Carrier (Q) NS Package Number V28A 13 100331 Low Power Triple D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Lit. Y 114912 24-Lead Quad Cerpak (F) NS Package Number W24B LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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