DS80PCI810
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SNLS493A –OCTOBER 2014–REVISED JANUARY 2015
Pin Functions(1) (continued)
PIN NAME PIN NUMBER I/O, TYPE DESCRIPTION
ENSMB = Float (SMBus MASTER MODE)
Clock output when loading EEPROM configuration, reverting to SMBus
I, LVCMOS, clock input when EEPROM load is complete (ALL_DONE = 0).
SCL 50 O, OPEN Drain External 2 kΩto 5 kΩpull-up resistor required as per SMBus interface
standards(2)
In both SMBus Modes, this pin is the SMBus data I/O. Data input or
I, LVCMOS, open drain output.
SDA 49 O, OPEN Drain External 2 kΩto 5 kΩpull-up resistor required as per SMBus interface
standards(2)
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the
user set SMBus slave address inputs.
AD0-AD3 54, 53, 47, 46 I, LVCMOS External 1 kΩpull-up or pull-down recommended.
Note: In Pin Mode, AD2 must be tied via external 1 kΩto GND.
A logic low on this pin starts the load from the external EEPROM(3).
READ_EN 26 I, LVCMOS Once EEPROM load is complete (ALL_DONE = 0), this pin functionality
remains as READ_EN. It does not revert to an SD_TH input.
Reserved
For applications requiring Signal Detect status register read-back:
I, 4-LEVEL, ●Leave Pin 21 floating.
RESERVED2 21 LVCMOS ●Write Reg 0x08[2] = 1 if Pin 21 is floating.
Otherwise, tie Pin 21 via external 1 kΩto GND (External 1 kΩto VDD
(2.5 V mode) or VIN (3.3 V mode) is also acceptable).
Reserved
I, 4-LEVEL,
RESERVED3 19 This input may be left floating, tied via 1 kΩto VDD (2.5 V mode) or VIN
LVCMOS (3.3 V mode), or tied via 1 kΩto GND.
ENSMB = 0 (PIN MODE)
EQA and EQB pins control the level of equalization for the A-channels
and B-channels, respectively. The pins are defined as EQA and EQB
only when ENSMB is de-asserted (low). Each of the four A-channels
have the same level unless controlled by the SMBus control registers.
EQA 20 I, 4-LEVEL, Likewise, each of the four B-channels have the same level unless
EQB 46 LVCMOS controlled by the SMBus control registers.
When the device operates in Slave or Master Mode, the SMBus registers
independently control each lane, and the EQB pin is converted to an
AD3 input. See Table 4.
VODB[1:0] controls the output amplitude of the B-channels. The pins are
defined as VODB[1:0] only when ENSMB is de-asserted (low). Each of
VODB0 53 I, 4-LEVEL, the four B-channels have the same level unless controlled by the SMBus
VODB1 54 LVCMOS control registers. When the device operates in Slave or Master Mode, the
SMBus registers provide independent control of each lane, and
VODB[1:0] pins are converted to AD0, AD1 inputs. See Table 5.
VODA[1:0] controls the output amplitude of the A-channels. The pins are
defined as VODA[1:0] only when ENSMB is de-asserted (low). Each of
VODA0 49 I, 4-LEVEL, the four A-channels have the same level unless controlled by the SMBus
VODA1 50 LVCMOS control registers. When the device operates in Slave or Master Mode, the
SMBus registers provide independent control of each lane and the
VODA[1:0] pins are converted to SCL and SDA. See Table 5.
Reserved in Pin Mode (ENSMB = 0)
AD2 47 I, LVCMOS This input must be tied via external 1 kΩto GND.
Controls the internal Signal Detect Status Threshold value when in Pin
Mode and SMBus Slave Mode. This pin is to be used for system
I, 4-LEVEL, debugging only, as the signal detect threshold has no impact on the data
SD_TH 26 LVCMOS path. See Table 3 for more information.
For final designs, input can be left floating, tied via 1 kΩto VDD (2.5 V
mode) or VIN (3.3 V mode), or tied via 1 kΩto GND.
Reserved
I, 4-LEVEL,
RESERVED2 21 Tie via external 1 kΩto GND (External 1 kΩto VDD (2.5 V mode) or VIN
LVCMOS (3.3 V mode) is also acceptable).
(3) When READ_EN is asserted low, the device attempts to load EEPROM. If EEPROM cannot be loaded successfully, for example due to
an invalid or blank hex file, the DS80PCI810 waits indefinitely in an unknown state where SMBus access is not possible. ALL_DONE pin
remains high in this situation.
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