Features * Organization: 65,536 words x 8 bits * Single 3.3 0.3V power supply * High speed - 20/25 ns address access time - 5/6 ns output enable access time * Very low power consumption - Active: 216 mW max, 20 ns cycle - Standby: 9.0 mW max, CMOS I/O 2.CV data retention * Equal access and cycle times * Easy memory expansion with CET, CE2 and OF inputs Logic block diagram * TTL-compatible, three-state 1/O * Ideal for cache and portable computing ~ 75% power reduction during CPU idle mode * 32-pin JEDEC standard packages - 300 mil PDIP and SOJ * ESD protection 2 2000 volts * Latch-up current > 200 mA Pin arrangement <1 DIP, SOJ Veo GND-> NC 1 Veo NC 2 AMS Input buffer Ald 3 cE2 Al2 4 WE AT 5 Al3 Aa 707 AG 6, A8 Al 5 AS Tom Ag a2 3 256x256X8 s Ad 8 om All : 3 / . A3 9 0CUY GE Aa 3 Array Hy 2 A a Alo AS 3 (324.288) & Al = CET AG L_. yoo AO VOT A? YOO vO6 Vol Vos ra WE vO2 vO4 a GND O03 Column decoder Control OE circuit le- CEL AAAAAAAA pe CES 8 9 10311213 1415 Selection guide 7035 12-20 7C35 12-25 Unit Maximum address access time 20 25 ns Maximum output enable access ime 5 6 ns Maximum operating current 60 5 mA _. Maximum CMOS standby current 2.5 2.5 mA f908 Alliance Semiconductor. All rights restrved. = x= = 7)SRAM AS7C3512 Functional description The AS7C3512 is a 3.3V high performance CMOS 524,288 -bit Static Random Access Memory (SRAM) organized as 65,536 words x 8 bits. it is designed for memory applications requiring fast data access at low voltage, including Pentium, PowerPC, and portable computing. Alliance's advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins. The device enters standby mode when CET is High or CE? is Low. CMOS standby mode consumes $9.0 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. The AS7C3512 offers 2.0V data retention. Equal address access and cycle times (tag, tac, two) of 20/25 ns with output enable access times (tog) of 5/6 ns are ideal for high performance applications. The active high and low chip enables (CET, CE2} permit easy memory expansion with multiple-bank memory systems. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CET, CE2), Data on the input pins I/O0-I/07 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CET or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CET, CE2), with write enable (WE) High. The chip drives [/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and SV tolerant. Operation is from a single 3.340.3V supply. The AS7C3512 is packaged in ali high volume industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Power supply voltage relative to GND Voc -0.5 +4.6 Vv Input voltage relative to GND Vin 0.5 +6.0 v Power dissipation Ph - 1.0 Ww Storage temperature (plastic) Tog ~55 +150 C Temperature under bias Thias -10 +85 C DC output current Tour - 20 mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper- ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabiliry Truth table CEI CE2 WE E Data Mode H xX X x High Z Standby (Isp, Isp)) x L xX x High Z Standby (Isp, Ispy) L H H H High Z Output disable L H H L Dour Read L H L x Din Write Key: X = Dont Care, L = LOW, H = HIGH ? DID 11-20015-A. Copyright 1998 Alliance Semiconductor. All rights reserved.AS7C3512 de. Recommended operating conditions (T, = 0C to +70C) Parameter Symbol Min Typ Max Unit 1 It Vec 3.0 3.3 3.6 Vv ou y VOItage PP & GND 0.0 0.0 0.0 Vv Vig 2.0 - Veco + 0.5 Vv Input voltage + Vit ~0.5 - 0.8 Vv Wi min = 2.0V for pulse width less than tyc/2. DC operating characteristics (Vee = 3.30.3V, GND = OV, T, = 0C to +70C) -20 -25 Parameter Symbol Test conditions Min Max Min Max Unit Input leakage current Til == Veo = Max, Vin = GND to Vee - 1 - 1 HA CET = Vy or CE2 = Vy, Ve = Max Output leakage current 1 tH He "CC , ~ 1 _ 1 A tp ge curr Lol Vous = GND to Veg uw O i 1 sae berating Power SUPPIY ice CED = Vy, CE2 = Viz, = imax, lout = OMA - 60 | - SS | mA current , . Isg 0 CET = Vy or CE2 = Vip, = Snax > 20 - 20 mA Standby power supply == ; current Ippo 2 Vec0-2V or CED S 0.2%, a6}. as | ma Vin S 0.2V or Vj, 2 Voc0.2V, f= 0 Vv Ig, = 8 mA, Vee = Min ~ 0.4 - 0.4 Vv Output voltage Ov Ok ce Vou. log = ~4 mA, Vec = Min 2.4 > 2.4 - v Capacitance 2 (f= | MHz, T, = Room temperature, Vcc = 3.3V} Parameter Symbol Signals Test conditions Max Unit Input capacitance Cin A, CEI, CE2, WE, GE = -Viy = OV 5 pF 1/O capacitance Cro Vo Vin = Vour= OV 7 pF 3 DID 14-20015-A_ Copyright 1993 Alliance Semiconductor. All rights reserved. SRAMNY WLULy AS7C3512 Key to switching waveforms Eie4 Rising input Read cycle 394? Falling input Ar: Undefined output/dont care (Vec = 3.340.3V, GND = OV, T, = 0C to +70C} -20 ~25 Parameter Symbol! Min Max Min Max Unit Notes Read cycle time tac 20 - 25 ~ ns Address access time taa ~ 20 ~ 25 ns 3 Chip enable (CET) access time tACEI - 20 - 25 ns 3,142 Chip enable (CE2) access time tack? - 20 - 25 ns 3,12 Output enable (OE) access time Log > ~ 6 ns Curput hold from address change ton 3 > 3 - ns 5 Chip enable (CET) to output in Low Z teLzi 3 ~ 3 ~ ns 4,5, 12 Chip enable (CE2) to output in Low Z tciz? 3 - 3 - ns 4,5, 12 Chip disable (CE1) to output in High Z tcH7) ~ 5 ~ 6 ns 4,5,12 Chip disable (CE2) to output in High Z toyz? - 5 ~ 6 ns 4,5, 12 Output enable to output in Low Z loz 0 - 0 ~ ns 4,5 Output disable to output in High Z toyz ~ 5 ~ 6 ns 4,5 Chip enable to power up time tpu 0 - 0 - ns 4,5, 12 Chip disable to power down time tpp ~ 20 ~ 25 ns 4,5,12 Read waveform |] 447,942 Address controlled tre Address tou Data valid CET and CE? controlled I tac CEI , A CE2 OE tonzi. CHz2 Dou Data valid le teoizi,'cLz2 t . ; t+ "pp lee Supply Pu AC 50% 50% Isp current 4 DID 11-20015-4. Copyright 1998 Alliance Semiconductor, All nghts reserved.AS7C3512 or: Write cycle 4? (Voc = 3.340.3V, GND = OV, T, = 0C to +70C) 20 -25 Parameter Symbol Min Max Min Max Unit - Notes Write cycle time twe 20 ~ 25 ~ ns Chip enable (CET) to write end tow] 12 - 18 ~ ns 12 Chip enable (CE2) to write end tow? 12 - 15 ~ ns 12 Address setup to write end taw 12 - 15 - ns. Address setup time tas 0 - 0 _ ns 12 Write pulse width twee 12 - 1s - ns Address hold from end of write aH 0 - 0 ~ ns Data valid to write end tow 10 - 12 _ ns Data hold time oH 0 ~ 0 ~ ns 4,5 Write enable to output in High Z twz - 5 - 5 ns 4,5 Qutput active from write end Low 3 - 3 - ns 4,5 Write waveform | 101412 WE controlled Address bw Din Data valid Dout Write waveform 2 142412 CET and CE2 controlled Wwe | taw tan > .ddress K le- tas tow, tcw2 + CEI He =e oe LY p tpw- tou Data valid T 5 DID 11-20015-A. Copyright 1998 Alliance Semiconductor. All rights reserved.AS7C3512 Data retention characteristics Parameter Occ eerrecenanel eS Symbol Test conditions Min Max Unit Ver for data retention Vor Vee = 2.0V 2.0 _ Vv Daia retention current lecpr GET 2 Vec-0.2V or 1200 HA Chip deselect to data retention time tcpR CE2 5 0.2V 9 _ ns Operation recovery time ty Vin 2 Vec0.2V ot tre ~ ns Input leakage current lhl Vin 3 0.2V - i HA Data retention waveform Data retention mode Vee 3.0V K Vpp 2 2.0V JF 3.0V fcpR Vv CET Z DR AC test conditions * Output load: see Figure B, Thevenin equivalent: except for tery and tcp see Figure C. 1682 * Input pulse level: GND to 3.0V. See Figure A. Douref~W\Yyrr 4172 Input rise and fall times: 5 ns. See Figure A. 43.3V 43.3V * Input and output timing reference levels: 1.5V. 3202 3200 +3.3V _ Dout f Don 3500 =F 30 pF* 3500S =F S pF* GND GND Oe pence Figure A: Input waveform Figure B: Output load Figure C: Output load for toyz. toyz Notes This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C This parameter is guaranteed but not tested. WE is HIGH for read cycle. CET and OF are LOW and CE? is HIGH for read cycle. Address valid prior to or coincident with CET transition LOW and All read cycle timings are referenced from the last valid address to CFT or WE must be HIGH or CE2 LOW during address transitions. try ee NR RY EY Me CET and CE? have identical timing. 6 DID 11-20015-A. During Ve power-up, a pull-up resistor to Vec on CET is required to meet Ica specification. icy and toyz are specified with CL = SpF as in Figure C. Transition is measured +$00mV from steady-state voltage. CE? transition HIGH. the first transitioning address. All write cycle timings are referenced from the last valid address to the first transitioning address. Copyright 1998 Alliance Semiconductor. All rights reserved.Typical DC and AC characteristics Normalized supply current Ic, Isp vs. supply voltage Voc 14 1.2 lec 1.0 Normalized lec, Isp 3.0 3.3 3.6 Supply voltage (V) Normalized access time ta, vs. supply voltage Vor T, = 25C Normalized access time 3.0 3.3 3.6 Supply voltage (V) Output source current Top; vs. output voltage Voz Vee = 3.3V T, = 25C Output source current (mA) 0.0 1.65 3.3 Output voltage (V) PED 11-20015-A. Normalized Ecc, Isa Normalized access time Output sink current (mA) Normalized supply current lec, Isp vs. ambient temperature T, Tec 15 10 35.605 Ambient temperature (C) Normalized access time tay vs. ambient temperature T, 1.4 Veo = 3.3V 13 1.2 11 1.0 0.9 0.8 ~15 10 35 80 85 Ambient temperature (C) Output sink current Loy vs. output voltage Voy 70 60 Veco = 3.3V 50 F 7, = 25C 40 30 20 0.0 1.65 3.3 Oueput voltage (V)} AS7C3512 Normalized supply current Ippy vs. ambient temperature T, 625 4 Voc = 3.30 go 25 <= ae 5 zo 3 E02 a 0.04 ~55 -10 35 80 125 Ambient temperature (C) Normalized supply current I vs. cycle frequency I/tae, I /twe b4 1.2 Voc = 3.3V y 1.2 = 25C g 0.8 = 06 S 4 04 0.2 0.6 G 20 40 60 80 Cycle frequency (MHz) Typical access time change Ata, vs, output capacitive loading 35 30 Vee = 3.3 ews = 20 & w 15 oS g & 10 GO w So 0 256 500 750 1000 Capacitance (pF) 7 Copyright 1998 Alliance Semiconductor. All rights reserved. Ny waviyAS7C3512 ds. AS7C3512 ordering information Package \ Access time 20 ns 25 ns Plastic DIP 300 mil AS7C3512-20PC AS7C3512-25PC Plastic SOJ, 300 mil AS7C3512-20JC AS7C35 12-25JC AS7C3512 part numbering system AS?C 3 $12 ~XX xX c . , . Package:P = PDIP 300 mil Commercial temperature range, Ah = Vis j S SRAM prefix 3 3.3 supply Device number Access time J = SO} 300 mil 0C to 70C 8 DID 1t-20015-A. . Copyright 1998 Alliance Semiconducter. All rights reserved.