TOSHIBA TC551001APL/AFL/AFTL/ATRL70L/85L/10L(LV) SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM Description The TC551001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated from a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating cur- rent of SMA/MHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2uA typically. The TC551001APL has three control inputs. Chip enable inputs (CET, CE2) allow for device selection and data retention control, while an output enabie input (OB) provides fast memory access. The TC5510Ci1 APL is suitable for use in microprocessor systems where high speed, low power, and battery backup are required. The TC551001APL-L(LY) operates and is characterized at both 3 and 5 volts. The TC551001APL is offered in a standard dual-in-line 32-pin plastic package, a small outline plastic package, and a thin small outline plastic package (forward type, reverse type). Features Pin Connection (Top View) Low power dissipation: 27.5mW/MHz (typ.) 32 PIN DIP & SOP 32 PIN TSOP Standby current: 4uA (max.) at Ta = 25C nec VW 320 Uf dt { t ) Single 5V | 1 Voo orward type reverse type , ane ov power supply ate 2 310) Ais ccess time (max.) Ai4G] 3 300 ce2 16 1 1 6 TC551001APL/AFL/AFTL/ATRL Ai2zQ 4 290) Rw a7 5 280) A13 -TOL(LV) | -B5L(LV) | -10L(LV) as6Oe6 270) as Access Time 70ns 85ns 100ns 457 260 a9 CET Ti 7 85) 100 ass 25) All E1 Access Time Ons ns ns a3Ula9 24] OE CE2 Access Time 70ns 85ns 100ns A2 C10 230) A10 GE Access Time 35ns 45ns 50ns ar dit 220) CET <= Ao (12 2100 1/08 Power down feature: CE1, CE2 17010113 20D 1/07 * Data retention supply voltage: 2.0 ~ 5.5V 1020] 14 3B 1/06 Inputs and outputs TTL campatibie 103) 15 O05 hy 32 32 177 GNoL 16 YP TO = TO Package TC551001APL - DIP32-P-600 TC551001 AFL : SOP32-P-525 TCS551001AFTL =: TSOP32-P-0820 TC551001ATRL =: TSOP32-P-0820A Pin Names AQ~A16 | Address Inputs R/AwW Read/Write Control Input OE Output Enable Input CET, CE2 | Chip Enable Inputs VO1 ~ 1/08 | Data Input/Output Vop Power (+5V) GND Ground NG No Connection PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PINNAME | Ay; | Ag | Ag | Aig | RW] CE2 | Ags | Vpn | NC | Age | Aya | Ato | Ay As As Ag PIN NO. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN NAME A3 Ao Ay Ao VO1 | VO2 | VO3 | GND | /o4 05 VO6 VO? vos | CET Ato OE TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. A-99TC551001APL/AFL/AFTU/ATRL-7OL/85L/10L(LV) Static RAM Block Diagram CE wee Ue |e owt e Hons GND AY = za lla MEMORY CELL Al2 8<| (85 ||8= ARRAY Ala sljso 512x 64x32 Al aSUsSusy (1048576) Al 2 we aw ea = SENSE AMP. a 3 $ Ki & z 2 lhe & 1/08 oz a_i we? AD ATA2 A3 AAS AG A10 OE R/AV CET CcE2 Operating Mode a __ - MoDE ane CH | cee | dE | Rw | 01-108 | POWER Read eek H L H Dout Ippo Write L H . L Din Ippo | Output Deselect L H H | H | HighzZ | Ippo Standby H . | . _| * High-Z | Ibps - ee ee a Hort Maximum Ratings SYMBOL ITEM | RATING UNIT Vop | Power Supply Voltage 0.3 -7.0 Vv Vin Input Voltage oe 7 0.3" ~ 7.0 Vv Vio | Inputand Output Voltage ss] -05~Vpp+05 | Vi Py |Power Dissipation 100.6" | Ww Tsocpea | Soldering Temperature *Time 26010 | Cesec Tstraq | Storage Temperature 55 ~ 150 C Topa | Operating Temperature Q~ 70 S| +4 -3.0V with a pulse width of 5Cns * SOP A-100 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Static RAM 1C551001APL/AFL/AFTL/ATRL-70L/85L/10L(LV) DC Recommended Operating Conditions SYMBOL PARAMETER MIN. | TYP. | MAX. | UNIT | Vpp__| Power Supply Voltage 4.5 5.0 5.5 Vin Input High Voltage 2.2 - Vpp + 0.3 V Vie Input Low Voltage -0.3 - 0.8 Vpy___| Data Retention Supply Voltage 2.0 - 5.5 DC Characteristics (Ta = 0 ~ 70C, Vpp = 5V+10%) SYMBOL PARAMETER TEST CONDITION MIN. | TYP. | MAX. | UNIT lu Input Leakage Current Vin =0~ Vop - - +1.0 pA CET = Viyq or CE2 = Vy or R/W = Vi, or l Output Leakage Current xe lH it IL - - +1.0 Lo P 9 OE = Vin, Vout = 9 ~ Vo nA low Output High Current Vou = 2.4V -1.0 - - mA lo. Output Low Current Voz = 0.4V 4.0 - - mA CET = Vy and CE2 = Viy Min. - - 70 | and RAW = Vin, ' oo01 lout =OmA cycle tps _ _ 20 Other Inputs = Vin/ViL Operating Current CE1 = 0.2V and Min. T - 60 mA CE2 = Vpp - 0.2V I RW = Vop - 0.2V ' pDoz lout = OMA cycle | tus - - 10 Other Inputs = Vpp - 0.2V/0.2V Ippsi CET = Vy or CE2 = Vi - - 3 mA Standby Current CET = Vpp - 0.2V or Ta =0~ 70C - - 30 lopsa" CE2 = 0.2V - WA Vp = 2.0V ~ 5.5V Ta= 25C ~ a 4 Note (1): If CE1 2 Vpp - 0.2V, the specified limits are quaranteed under the condition CE2 2 Viyy - 0.2V or CE2 s 0.2V. Capacitance* (Ta = 25C, f = 1MHz) SYMBOL PARAMETER TEST CONDITION MAX. | UNIT Cin Input Capacitance Vin = GND 10 c | Court | Output Capacitance Vout = GND 10 p *This parameter is periodically sampled and is not 100% tested. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. A-101TC551001 APL/AFL/AFTL/ATRL-70L/85L/10L(LV) Static RAM AC Characteristics (Ta = 0 ~ 70C, Vpp = 5V+10%) Read Cycle TC551001APL/AFL/AFTL/ATRL SYMBOL PARAMETER -7OL(LV) -85L (LV) -10L(LV} UNIT MIN. MAX. MIN. MAX. MIN. MAX. tac | Read Cycle Time 70 = 85 - 100 - tacc | Address Access Time - 70 - 85 - 100 tco1 | CET Access Time - | 70 - 85 - 100 tco2 | CE2 Access Time - 70 - 85 - 100 toe Output Enable to Output in Valid - 35 - 45 - 50 teoe | Chip Enable (CET CE2) to Output in Low-z 10 - 10 - 10 ~ ns toce | Output Enable to Output in Low-Z 5 - 7 4 - top | Chip Enable (CET. CE2) to Output in High-Z - 25 - 30 35 topo | Output Enable to Output in High-Z - 25 - 30 - 35 tou Output Data Hold ime 10 - 10 - 10 - Write Cycle _ ; _ TC551001 APL/AFL/AFTL/ATRL SYMBOL PARAMETER -7OL(LV) -B5L(LV) -1DL(LV) UNIT MIN. MAX. MIN. MAX. MIN. MAX. two | Write Cycle Time 70 - 85 - 100 - twp | Write Pulse Width 50 - 60 | - 60 = tcw | Chip Selection to End of Write 60 - 75 - 80 - tas Address Setup Time 0 - ~ 0 - twr Write Recovery Time 0 - 0 - 0 - ns toow . R/W to Output in High-Z - 25 - 300, 35 toew | RW to Output in Low-Z 5 - 5 | - | 5 - tps | Data Setup Time 30 - 35 5 - | 40 - | tp |DataHoldTime 0 - 0 - 0 - AC Test Conditions Input Pulse Levels 2.4V/0.6V | Input Pulse Rise and Fall Time 5ns : Input Timing Measurement Reference Levels 1.5V Output Timing Measurement Reference Levels 1.5V ~ i Output Load 1 TTL Gate and C, = 100pF A-102 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Static RAM 1TC551001APL/AFL/AFTL/ATRL-70L/85L/10L(LV) Timing Waveforms ADDRESSES x teor "Win |, = THON MLA Ww Dour c OUTPUT DATA VALID ee Write Cycle 1 (R/W Controlled Write) twe ADORESSES x x toow toew 0 YMA YM Lhd tos YUM: ED oom (EE TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. A-103TC551001APL/AFL/AFTL/ATRL-70L/85L/10L(LV) Static RAM Write Cycle 2 4) (CE1 Controlled Write) twe ADDRESSES xX xX tas t twe twr 2 tos t Diy Y/Y (5G Yy, DATA STABLE Wy Wy Write Cycle 3 (4) (CE2 Controlled Write) ADDRESSES Xx ; Y ce 7m A104 7@8HIBA AMERICA ELECTRONIC COMPONENTS, INC.Static RAM 1TC551001APL/AFL/AFTL/ATRL-70L/85L/10L(LV) Notes: 1. RW is high for read cycles. 2. if the CE1 low transition or CE2 high transition occurs coincident with or after the RW low transition, outputs remain in a high impedance state. 3. If the CE1 high transition or CE2 low transition occurs coincident with or prior to the R/W high transition, outputs remain in a high impedance state. 4. If OE is high during a write cycle, the outputs are in a high impedance state during this period. 5. The I/O may be in the output state during this time; therefore input signals of opposite phase must not be applied. TOSHIBA AMERICA ELECTAONIC COMPONENTS, INC. A-105TC551001APL/AFL/AFTL/ATRL-70L/85L/10L(LV) Static RAM Data Retention Characteristics (Ta = 0 ~ 70C) SYMBOL PARAMETER MIN. | TYP. MAX. UNIT Vpn | Data Retention Supply Voltage 2.0 - 5.5 Vv VbH = 3.0V - ~ 15* Ipps2_ | Standby Current Vou = 5 5V = = 30 HA tcpn | Chip Deselect to Data Retention Mode - - ns tr Recovery Time 5 - - ms * 3uA (max.) Ta = 0 ~ 40C CE Controlled Data Retention Mode Voo Voo EN OATA RETENTION MODE 4asv -- ~---AV~~ ee ~~ ee ee wo fpf ~-- be (2) (2) Va TT Voo- 0.2V ter / Teor te GND CE2 Controlled Data Retention Mode ) Vv, Voo _\F DATA RETENTION MODE S Vin Vv. om a 0.2V GND Notes: 1. In the CE1 controlled data retention mode, minimum standby current is achieved under the condition CE2 < 0.2V or CE2 2 Vpp - 0.2V. 2. If the Viy of CET is 2.2V in operation, during the period that the Vpp voltage is going down from 4.5V to 2.4V, Ipps1 current flows. 3. In the CE2 controlled data retention mode, minimum standby current is achieved under the condition CE2 < 0.2V. A-106 TOSHIBA AMERICA ELECTRONIC COMPONENTS, ING.Static RAM TC551001 APL/AFL/AFTL/ATRL-70L/85L/10L(LV) 3V Operation DC Recommended Operating Conditions SYMBOL PARAMETER MIN. | TYP. | MAX UNIT | Vpp___| Power Supply Voltage 27 3.0 3.3 | Vin Input High Voltage Vop - 0.2 - Vpp + 0.3 v Vit Input Low Voltage -0.3 = 0.2 DC Characteristics (Ta = 0 ~ 70C, Vpp = 3V10%) SYMBOL PARAMETER TEST CONDITION MIN. | TYP. | MAX. | UNIT Mu Input Leakage Current Vin =9 ~ Voo - - +1.0 HA CE1 = Vy, or CE2 = Vi_ or RAW = Vj, or i Output Leakage Current aa Iq i L - - +1.0 A Lo P 9 / OE = Vin, Vout = 9 ~ Yoo lou Output High Current Vou = Vpp - 0.2V -0.1 - - mA lon Output Low Current Voy = 0.2V 0.1 - - mA CE1 =0.2V Min. ~ - 20 and CE2 = Vpp - 0.2V . RW = Vop - 0.2V Ippo2 | Operating Current loyr = OMA leycle us _ _ 5 mA Other Inputs = Vop - 0.2V/0.2V CET = Vpp - 0.2V or Ta=0~70C | - ~ 20 Ippse'") | Standby Current DD LK A DDS2 C&2 = 0.2V Ta = 25C - 1 2 " Note (1): If CET 2 Vip - 0.2V, the specified limits are guaranteed under the condition CE2 2 Vpp - 0.2V or CE2 < 0.2V, Capacitance* (Ta = 25C, f = 1MHz) SYMBOL PARAMETER TEST CONDITION MAX. | UNIT Cin Input Capacitance Vin = GND 10 E Cour | Output Capacitance Vout = GND 10 P This parameter is periodically sarmpt:d and is not 100% tested. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. A-107TC551001APL/AFL/AFTL/ATRL-70L/85L/10L(LV) Static RAM 3V Operation AC Characteristics (Ta = 0 ~ 70C, Vpp = 3V+10%) Read Cycle SYMBOL PARAMETER MIN. MAX. UNIT tac Read Cycle Time 150 - tacc | Address Access Time - 150 tco1 | CET Access Time ~ 150 tcos | CEZAccessTime fo 450 tog Output Enable to Output in Valid - 75 tcoe | Chip Enabie (CET CE2) to Output in Low-Z 10 - ns toce | Output Enable to Output in Low-Z 5 - top _| Chip Enable (CET. CE2) to Output in High-Z - 50 topo _| Output Enable to Output in High-Z = | 60 ton __| Output Data Hold ime ff to Write Cycle _ SYMBOL PARAMETER | MIN. MAX. UNIT two | Write Cycle Time _ eel 150 | - twe | Write Pulse Width 100 - tew | Chip Selection to End of Write 120 - tag | Address Setup Time 0 | = twa Write Recovery 7 Time 0 - ns topw _ | R/W to Output in High-Z = 50 toew RAW to Output in twz <i~SstiSHT!t*WGS _ tos Data Setup Time ; 60 oe ton [Data Hold Time [ o- - AC Test Conditions Input Pulse Levels BT = 0.2/0.2 i Input Pulse Rise and Falitime 5ns _ Input Timing Measurement Reference Levels 1.5V Output Timing Measurement Reference Levels | 1.5V0O | Output Load CL= 100pF | A-108 TOSHIBA AMERICA ELECTRONIC COMPONENTS, ING.