ADVANCE 0.16m Process 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 18Mb SYNCBURSTTMSRAM MT58L1MY18P, MT58V1MV18P, MT58L512Y32P, MT58V512V32P, MT58L512Y36P, MT58V512V36P 3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O FEATURES 100-Pin TQFP1 * Fast clock and OE# access times * Single +3.3V 0.165V or 2.5V =/-0.125V power supply (VDD) * Separate +3.3V or +2.5V isolated output buffer * Supply (VDDQ) * SNOOZE MODE for reduced-power standby * Single-cycle deselect (Pentium(R) BSRAMcompatible) * Common data inputs and data outputs * Individual BYTE WRITE control and GLOBAL WRITE * Three chip enables for simple depth expansion and address pipelining * Clock-controlled and registered addresses, data I/ Os and control signals * Internally self-timed WRITE cycle * Burst control pin (interleaved or linear burst) * Automatic power-down for portable applications * Low capacitive bus loading * x18, x32, and x36 versions available OPTIONS 165-Ball FBGA2 1. JEDEC-Standard MS-025 BHA (LQFP). 2. JEDEC Standard MS-216 (Var. CAB-1) TQFP MARKING * Timing (Access/Cycle/MHz) 3.3V VDD, 3.3V or 2.5V I/O, and 2.5V VDD, 2.5V I/O 3.1ns/5ns/200 MHz -5 3.5ns/6ns/166 MHz -6 4.2ns/7.5ns/133 MHz -7.5 5ns/10ns/100 MHz -10 * Configurations 3.3V VDD, 3.3V or 2.5V I/O 1 Meg x 18 MT58L1MY18P 512K x 32 MT58L512Y32P 512K x 36 MT58L512Y36P 2.5V VDD, 2.5V I/O 1 Meg x 18 MT58V1MV18P 512K x 32 MT58V512V32P 512K x 36 MT58V512V36P 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev. A; Pub 6/02 PRODUCTS TQFP MARKING OPTIONS * Packages 100-pin TQFP (3-chip enable) 165-ball FBGA * Operating Temperature Range Commercial (+10C TJ 110C) T F* None *A Part Marking Guide for the FBGA devices can be found on Micron's Web site--http://www.micron.com/numberguide. Part Number Example: MT58L512Y36P-10 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM GENERAL DESCRIPTION The Micron(R) SyncBurstTM SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. Micron's 18Mb SyncBurst SRAMs integrate a 1 Meg x 18, 512K x 32, or 512K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#), and global write (GW#). Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#). 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa pins/balls and DQPa; BWb# controls DQb pins/balls and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa pins/ balls and DQPa; BWb# controls DQb pins/balls and DQPb; BWc# controls DQc pins/balls and DQPc; BWd# controls DQd pins/balls and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions. This device incorporates a single-cycle deselect feature during READ cycles. If the device is immediately deselected after a READ cycle, the output bus goes to a High-Z state tKQHZ nanoseconds after the rising edge of clock. The device is ideally suited for Pentium and PowerPC pipelined systems and systems that benefit from a very wide, high-speed data bus. The device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications. Please refer to Micron's Web site (www.micron.com/ sramds) for the latest data sheet. DUAL VOLTAGE I/O The 3.3V VDD device is tested for 3.3V and 2.5V I/O function. The 2.5V VDD device is tested for only 2.5V I/O function. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 1 MEG x 18 20 SA0, SA1, SAs 18 20 ADDRESS REGISTER 2 MODE 20 SA0-SA1 SA1' BINARY Q1 COUNTER AND LOGIC CLR Q0 ADV# CLK SA0' ADSC# ADSP# BYTE "b" WRITE REGISTER BWb# BYTE "a" WRITE REGISTER BWa# BYTE "b" WRITE DRIVER 9 BYTE "a" WRITE DRIVER 9 9 1 Meg x 9 x 2 MEMORY ARRAY 18 SENSE AMPS 18 OUTPUT REGISTERS 18 OUTPUT BUFFERS 18 E 9 DQs DQPa DQPb BWE# GW# 18 ENABLE REGISTER CE# CE2 CE2# PIPELINED ENABLE INPUT REGISTERS 2 OE# FUNCTIONAL BLOCK DIAGRAM 512K x 32/36 19 SA0, SA1, SAs ADDRESS REGISTER 17 19 19 SA0-SA1 MODE SA1' Q1 BINARY COUNTER SA0' CLR Q0 ADV# CLK ADSC# ADSP# BWd# BYTE "d" WRITE REGISTER 9 BYTE "d" WRITE DRIVER 9 BWc# BYTE "c" WRITE REGISTER 9 BYTE "c" WRITE DRIVER 9 BWb# BWa# BWE# GW# CE# CE2 CE2# OE# Note: 512K x 9 x 4 (x36) BYTE "b" WRITE REGISTER 9 BYTE "b" WRITE DRIVER 9 BYTE "a" WRITE REGISTER 9 BYTE "a" WRITE DRIVER 9 ENABLE REGISTER 512K x 8 x 4 (x32) 36 SENSE AMPS 36 OUTPUT REGISTERS 36 MEMORY ARRAY 36 PIPELINED ENABLE OUTPUT BUFFERS E 36 DQs DQPa DQPb DQPc DQPd INPUT REGISTERS 4 Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams for detailed information. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC PIN LAYOUT (TOP VIEW) 100-PIN TQFP (3-Chip Enable) SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NF/DQPb1 DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NF/DQPa1 NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC x18 SA SA SA SA SA SA SA SA SA VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) NF/DQPc1 DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NF/DQPd1 x32/x36 SA SA SA SA SA SA SA SA SA VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) Notes: 1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2. Pins 39 and 38 are reserved for address expansion; 36Mb and 72Mb, respectively. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM TQFP PIN DESCRIPTIONS SYMBOL TYPE SA0 SA1 SA BWa# BWb# BWc# BWd# Input BWE# GW# CLK CE# CE2# CE2 OE# (G#) ADV# ADSP# ADSC# MODE (LBO#) ZZ DQa DQb DQc DQd DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For the x32 and x36 versions, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only available on the x18 and x36 versions. Input Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. Input Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is the JEDEC-standard term for OE#. Input Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH. Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. Input Mode: This input selects the burst sequence. A LOW on this pin selects "linear burst." NC or HIGH on this pin selects "interleaved burst." Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE. Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. This pin has an internal pull-down and can be floating. Input/ SRAM Data I/Os: For the x18 version, Byte "a" is DQa pins; Byte "b" is DQb pins. For the x32 and Output x36 versions, Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge of CLK. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM TQFP PIN DESCRIPTIONS (Continued) SYMBOL TYPE DESCRIPTION NF/DQPa NF/DQPb NF/DQPc NF/DQPd NF/ I/O VDD VDDQ Supply Supply VSS DNU Supply - NC - No Function/Parity Data I/Os: On the x32 version, these pins are No Function (NF). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. No Function pins are internally connected to the die and have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM BALL LAYOUT (TOP VIEW) 165-BALL FBGA x18 x32/x36 10 11 BWE# ADSC# ADV# SA SA GW# OE# (G#) ADSP# SA NC VSS VSS VDDQ NC DQPa VSS VSS VDD VDDQ NC DQa VSS VSS VSS VDD VDDQ NC DQa VDD VSS VSS VSS VDD VDDQ NC DQa VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa VSS NC VDD VSS VSS VSS VDD NC NC ZZ DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQPb NC VDDQ VSS NC SA VSS VSS VDDQ NC NC NC NC SA SA TD1 SA1 TD0 SA SA SA SA MODE (LBO#) NC SA SA TMS SA0 TCK SA SA SA SA 1 2 3 4 5 6 NC SA CE# BWb# NC CE2# NC SA CE2 NC BWa# CLK NC NC VDDQ VSS VSS VSS NC DQb VDDQ VDD VSS NC DQb VDDQ VDD NC DQb VDDQ NC DQb VDD 7 8 9 A D E VSS VSS VDD VDDQ DQb DQb VSS VSS VSS VDD VDDQ DQb DQb VDD VSS VSS VSS VDD VDDQ DQb DQb VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb VSS NC VDD VSS VSS VSS VDD NC NC ZZ DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa NF/DQPd1 NC VDDQ VSS NC SA VSS VSS VDDQ NC NF/DQPa1 NC NC SA SA TD1 SA1 TD0 SA SA SA SA MODE (LBO#) NC SA SA TMS SA0 TCK SA SA SA SA CE2 BWd# BWa# CLK NF/DQPc1 NC VDDQ VSS VSS VSS DQc DQc VDDQ VDD VSS DQc DQc VDDQ VDD DQc DQc VDDQ DQc DQc VDD B C D E F G H J K L M N P R NF/DQPb1 SA M N P NC NC A L M N VDDQ CE2# K L M VSS BWc# BWb# J K L VSS CE# N P R P R R TOP VIEW Notes: 9 H J K NC SA 8 G H J SA NC 7 F G H GW# OE# (G#) ADSP# 6 E F G NC 5 D E F SA 4 C C D BWE# ADSC# ADV# 3 B B C 11 2 A A B 10 1 TOP VIEW 1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2. Pins 2R and 2P are reserved for address expansion; 36Mb and 72Mb, respectively. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM FBGA BALL DESCRIPTIONS SYMBOL TYPE SA0 SA1 SA BWa# BWb# BWc# BWd# Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Input BWE# Input GW# Input CLK Input CE# Input CE2# Input CE2 Input ZZ Input OE#(G#) Input ADV# Input ADSP# Input ADSC# Input MODE (LBO#) Input TMS TDI TCK DQa DQb DQc DQd Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOWfor a WRITE cycle and HIGH for a READ cycle. For the x18 version,BWa# controls DQa and DQPa balls; BWb# controls DQb and DQPb balls. For the x32 and x36 versions, BWa# controls DQa and DQPa balls; BWb# controls DQb and DQPb balls; BWc# controls DQcs and DQPc balls; BWd# controls DQd and DQPd balls. Parity is only available on the x18 and x36 versions. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is the JEDEC-standard term for OE#. Synchcronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling busrt access after the external address is loaded. A HIGH on ADV# effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is iniated. Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new extrnal address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. Mode: This input selects the burst sequence. A LOW on this ball selects "linear burst." NC or HIGH on this ball selects "interleaved burst." Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE. IEEE 1149.1 test inputs: JEDEC-standard 2.5V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit. Input/ Output DESCRIPTION SRAM Data I/Os: For the x18 version, Byte "a" is DQa balls; Byte "b" is DQb balls. For the x32 and x36 versions, Byte "a" is DQa balls; Byte "b" is DQb balls; Byte "c" is DQc balls; Byte "d" is DQd balls. Input data must meet setup and hold times around the rising edge of CLK. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM FBGA BALL DESCRIPTIONS (Continued) SYMBOL TYPE NF/DQPa NF/DQPb NF/DQPc NF/DQPd VDD VDDQ NF/ I/O Supply Supply VSS TDO NC Supply Output - DESCRIPTION No Function/Parity Data I/Os: On the x32 version, these pins are No Function (NF). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. IEEE 1149.1 test outputs: JEDEC-standard 2.5V I/O level. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18) Note: FUNCTION GW# BWE# BWa# BWb# READ READ WRITE Byte "a" WRITE Byte "b" WRITE All Bytes WRITE All Bytes H H H H H L H L L L L X X H L H L X X H H L L X Using BWE# and BWa# through BWd#, any one or more bytes may be written. PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36) Note: FUNCTION GW# BWE# BWa# BWb# BWc# BWd# READ READ WRITE Byte "a" WRITE All Bytes WRITE All Bytes H H H H L H L L L X X H L L X X H H L X X H H L X X H H L X Using BWE# and BWa# through BWd#, any one or more bytes may be written. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM TRUTH TABLE (Notes: 1-8) OPERATION DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Notes: ADDRESS USED CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE# CLK DQ None H X X L X L X X X L-H High-Z None L X L L L X X X X L-H High-Z None L H X L L X X X X L-H High-Z None L X L L H L X X X L-H High-Z None L H X L H L X X X L-H High-Z None X X X H X X X X X X High-Z External External External External External Next Next Next Next Next Next Current Current Current Current Current Current L L L L L X X H H X H X X H H X H L L L L L X X X X X X X X X X X X H H H H H X X X X X X X X X X X X L L L L L L L L L L L L L L L L L L L H H H H H X X H X H H X X H X X X L L L H H H H H H H H H H H H X X X X X L L L L L L H H H H H H X X L H H H H H H L L H H H H L L L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D 1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH. 3. BWa# enables WRITEs to DQa's and DQPa. BWb# enables WRITEs to DQb's and DQPb. BWc# enables WRITEs to DQc's and DQPc. BWd# enables WRITEs to DQd's and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version. 4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 3.3V VDD, ABSOLUTE MAXIMUM RATINGS* 2.5V VDD, ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS ..... -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS ....................................... -0.5V to +4.6V VIN (DQx) ....................................... -0.5V to VDDQ + 0.5V VIN (inputs) ....................................... -0.5V to VDD + 0.5V Storage Temperature (TQFP).................-55C to +150C Storage Temperature (FBGA).................-55C to +125C Junction Temperature** ....................................... +150C Short Circuit Output Current ...............................100mA Voltage on VDD Supply Relative to VSS .....-0.3V to +3.6V Voltage on VDDQ Supply Relative to VSS........................................-0.3V to +3.6V VIN (DQx) ....................................... -0.3V to VDDQ + 0.3V VIN (inputs) ....................................... -0.3V to VDD + 0.3V Storage Temperature (TQFP)................ -55C to +150C Storage Temperature (FBGA)................ -55C to +125C Junction Temperature** ....................................... +150C Short Circuit Output Current ...............................100mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information. 3.3V VDD, 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (+10C TJ 110C; VDD = + 3.3V 0.165V; VDDQ = + 3.3V 0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply Notes: CONDITIONS SYMBOL MIN MAX UNITS NOTES VIH VIL ILI ILO 2.0 -0.3 -1.0 -1.0 VDD + 0.3 0.8 1.0 1.0 V V A A 1, 2 1, 2 3 VOH VOL VDD VDDQ 2.4 - 3.135 3.135 - 0.4 3.465 3.465 V V V V 1, 4 1, 4 1 1, 5 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA 1. All voltages referenced to VSS (GND). 2. For 3.3V VDD: Overshoot: VIH +4.6V for t tKC/2 for I 20mA Undershoot: VIL -0.7V for t tKC/2 for I 20mA Power-up: VIH +3.6V and VDD 3.135V for t 200ms For 2.5V VDD: Overshoot: VIH +3.6V for t tKC/2 for I 20mA Undershoot: VIL -0.7V for t tKC/2 for I 20mA Power-up: VIH +2.65V and VDD 2.375V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 3.3V VDD, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (+10C TJ 110C; VDD = + 3.3V 0.165V; VDDQ = +2.5V 0.125V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply CONDITIONS SYMBOL MIN MAX UNITS NOTES Data bus (DQx) VIHQ 1.7 V 1, 2 Inputs VIH VIL ILI ILO 1.7 -0.3 -1.0 -1.0 VDDQ + 0.3 VDD + 0.3 0.7 1.0 1.0 V V A A 1, 2 1, 2 3 VOH VOH VOL VDD VDDQ 1.7 2.0 - 3.135 2.375 - - 0.7 3.465 2.625 V V V V V 1, 4 1, 4 1, 4 1 1 0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) IOH = -2.0mA IOH = -1.0mA IOL = 2.0mA 2.5V VDD, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (+10C TJ 110C; VDD = + 2.5V 0.125V; VDDQ = + 2.5V 0.125V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output Low Voltage CONDITIONS SYMBOL MIN MAX UNITS NOTES Data bus (DQx) Inputs VIHQ VIH VIL ILI ILO 1.7 1.7 -0.3 -1.0 -1.0 VDDQ + 0.3 VDD + 0.3 0.7 1.0 1.0 V V V A A 1, 2 1, 2 1, 2 3 VOH VOL VOL VDD VDDQ 2.0 - - 2.375 2.375 - 0.7 0.4 2.625 2.625 V V V V V 1, 4 1, 4 1, 4 1 1 0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) IOH = -1.0mA IOL = 2.0mA IOL = 1.0mA Supply Voltage Isolated Output Buffer Supply Notes: 1. All voltages referenced to VSS (GND). 2. For 3.3V VDD: Overshoot: VIH +4.6V for t tKC/2 for I 20mA Undershoot: VIL -0.7V for t tKC/2 for I 20mA Power-up: VIH +3.6V and VDD 3.135V for t 200ms For 2.5V VDD: Overshoot: VIH +3.6V for t tKC/2 for I 20mA Undershoot: VIL -0.7V for t tKC/2 for I 20mA Power-up: VIH +2.65V and VDD 2.375V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS SYMBOL TYP MAX UNITS NOTES TA = 25C; f = 1 MHz; VDD = 3.3V Ci Co 4.2 3.5 5 4 pF pF 1 Ca CCK 4 4.2 5 5 pF pF 1 1 1 FBGA CAPACITANCE DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance CONDITIONS SYMBOL TYP MAX UNITS NOTES TA= 25C; f = 1 MHz CI CO CCK 4 4 5 5 4.5 5.5 pF pF pF 1 1 1 TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS SYMBOL Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. TYP UNITS JA 46 C/W NOTES 1 JC 2.8 C/W 1 SYMBOL TYP UNITS NOTES JA 40 C/W 1 JC 9 C/W 1 JB 17 C/W 1 FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. Junction to Balls Notes: 1. This parameter is sampled. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 3.3V VDD IDD OPERATINGCONDITIONS AND MAXIMUM LIMITS (1 MEG x 18) (Note 1, unless otherwise noted) (+10C TJ 110C) MAX DESCRIPTION CONDITIONS Power Supply Current: Operating Power Supply Current: Idle Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open Device selected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDDQ - 0.2; Cycle time tKC (MIN) Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDDQ - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDDQ - 0.2; Cycle time tKC (MIN) ZZ VIH CMOS Standby Clock Running Snooze Mode SYM TYP -5 -6 -7.5 -10 UNITS NOTES IDD TBD 300 275 225 200 mA 1, 2, 3 IDD1 TBD 210 190 170 145 mA 2, 3, 4 TBD 30 30 30 30 mA 3, 4 ISB4 TBD 210 190 170 145 mA 3, 4 ISB2Z TBD 30 30 30 30 mA 4 ISB2 2.5V VDD, IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (1 MEG x 18) (Note 1, unless otherwise noted) (+10C TJ 110C) MAX DESCRIPTION CONDITIONS Power Supply Current: Operating Power Supply Current: Idle Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open Device selected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDDQ - 0.2; Cycle time tKC (MIN) Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDDQ - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDDQ - 0.2; Cycle time tKC (MIN) ZZ VIH CMOS Standby Clock Running Snooze Mode Notes: SYM TYP -5 -6 -7.5 -10 UNITS NOTES IDD TBD 290 250 210 180 mA 1, 2, 3 IDD1 TBD 195 170 150 130 mA 2, 3, 5 TBD 30 30 30 30 ISB4 TBD 195 170 150 130 mA 3, 5 ISB2Z TBD 30 30 30 30 mA 5 ISB2 mA 3, 5 1. VDDQ = +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ. 2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 3. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode). 4. Typical values are measured at 3.3V, 25C, and 10ns cycle time. 5. Typical values are measured at 2.5V, 25C, and 10ns cycle time. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 3.3V VDD, IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (512K X 32/36) (Note 1, unless otherwise noted) (+10C TJ 110C) MAX DESCRIPTION CONDITIONS Power Supply Current: Operating Power Supply Current: Idle Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open Device selected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDDQ - 0.2; Cycle time tKC (MIN) Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDDQ - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDDQ - 0.2; Cycle time tKC (MIN) ZZ VIH CMOS Standby Clock Running Snooze Mode SYM TYP -5 -6 -7.5 -10 UNITS NOTES IDD TBD 380 340 280 230 mA 1,2,3 IDD1 TBD 210 180 160 145 mA 2, 3, 4 TBD 30 30 30 30 mA 3, 4 ISB4 TBD 210 180 160 145 mA 3, 4 ISB2Z TBD 30 30 30 30 mA 4 ISB2 2.5 VDD IDD OPERATINGCONDITIONS AND MAXIMUM LIMITS (512K x 32/36) (Note 1, unless otherwise noted) (+10C TJ 110C) MAX DESCRIPTION CONDITIONS Power Supply Current: Operating Power Supply Current: Idle Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open Device selected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDDQ - 0.2; Cycle time tKC (MIN) Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDDQ - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDDQ - 0.2; Cycle time tKC (MIN) ZZ VIH CMOS Standby Clock Running Snooze Mode Notes: SYM TYP -5 -6 -7.5 -10 UNITS NOTES IDD TBD 360 310 260 210 mA 1,2,3 IDD1 TBD 190 165 140 120 mA 2, 3, 5 TBD 30 30 30 30 ISB4 TBD 190 165 140 120 mA 3, 5 ISB2Z TBD 30 30 30 30 mA 5 ISB2 mA 3, 5 1. VDDQ = +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ. 2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 3. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode). 4. Typical values are measured at 3.3V, 25C, and 10ns cycle time. 5. Typical values are measured at 2.5V, 25C, and 10ns cycle time. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (+10C TJ 110C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted) -5 DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in LowZ Clock to output in HighZ OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) Hold Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) Notes: SYM MIN t KC KF t KH t KL MAX MIN 3.1 NOTES ns MHz ns ns 2 2 ns ns ns 2 3, 4, 5, 6 5.0 ns 3, 4, 5, 6 5.0 ns ns ns 7 3, 4, 5, 6 3, 4, 5, 6 3.0 3.0 5.0 1.5 0 4.2 3.5 UNITS 100 4.0 3.5 MAX 10.0 1.5 0 4.0 OELZ tOEHZ 0 tAS ADSS 1.4 1.4 1.5 1.5 1.5 1.5 2.0 2.0 ns ns 8, 9 8, 9 t AAS 1.4 1.5 1.5 2.0 ns 8, 9 t WS 1.4 1.5 1.5 2.0 ns 8, 9 t tCES 1.4 1.4 1.5 1.5 1.5 1.5 2.0 2.0 ns ns 8, 9 8, 9 t AH ADSH 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 8, 9 8, 9 t AAH 0.4 0.5 0.5 0.5 ns 8, 9 t WH 0.4 0.5 0.5 0.5 ns 8, 9 t 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 8, 9 8, 9 t t DS DH tCEH 0 MIN 133 3.5 3.1 MAX 2.5 2.5 1.5 0 3.1 -10 7.5 166 2.3 2.3 1.0 0 tOEQ -7.5 6.0 2.0 2.0 tKQHZ t MIN 200 t KQ KQX t KQLZ MAX 5.0 f t -6 3.0 0 3.0 0 3.5 4.5 1. Test conditions as specified with the output loading shown in Figure 1 for +3.3V I/O (VDDQ = +3.3V 0.165V) and Figure 3 for 2.5V I/O (VDDQ = +2.5V 0.125V) unless otherwise noted. (All Figures shown following timing diagrams.) 2. If VDD = +3.3V, then VDDQ = +3.3V or +2.5V. If VDD = +2.5V, then VDDQ = +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ. 3. Measured as HIGH above VIH and LOW below VIL. 4. This parameter is measured with the output loading shown in Figure 2. (All Figures shown following timing diagrams.) 5. This parameter is sampled. 6. Transition is measured 500mV from steady state voltage. 7. Refer to Technical Note TN-58-09, "Synchronous SRAM Bus Contention Design Considerations," for a more thorough discussion on these parameters. 8. OE# is a "Don't Care" when a byte write enable is sampled LOW. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 9. A write cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times. A read cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup and hold times. 10. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times withstable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM READ TIMING3 t KC CLK tKH tKL tADSS tADSH ADSP# tADSS tADSH ADSC# tAS ADDRESS tAH A1 A2 tWS A3 Burst continued with new base address. tWH GW#, BWE#, BWa#-BWd# tCES Deselect cycle. tCEH CE# (NOTE 2) tAAS (NOTE 4) tAAH ADV# ADV# suspends burst. OE# (NOTE 3) t OEHZ t KQLZ Q High-Z Q(A1) tOEQ tKQ t OELZ tKQX Q(A2) t KQHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t KQ (NOTE 1) Single READ BURST READ Burst wraps around to its initial state. DON'T CARE Notes: UNDEFINED 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to be driven until after the following clock rising edge. 4. Outputs are disabled within one clock cycle after deselect. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM WRITE TIMING t KC CLK tKH tKL tADSS tADSH ADSP# ADSC# extends burst. tADSS tADSH tADSS tADSH ADSC# tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP# initiates burst. BWE#, BWa#-BWd# tWS tWS tWH tWH (NOTE 5) GW# tCES tCEH CE# (NOTE 2) tAAS tAAH ADV# ADV# suspends burst. (NOTE 4) OE# (NOTE 3) tDS D tDH D(A1) High-Z D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) tOEHZ (NOTE 1) Q BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON'T CARE Notes: UNDEFINED 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV# must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM READ/WRITE TIMING3 tKC CLK tKL tKH tADSS tADSH ADSP# ADSC# tAS ADDRESS A1 tAH A2 A3 BWE#, BWa#-BWd# (NOTE 4) tCES tWS tWH tDS tDH A4 A5 A6 D(A5) D(A6) tCEH CE# (NOTE 2) ADV# OE# tKQ D tOELZ High-Z tKQLZ Q High-Z Q(A1) Back-to-Back READs (NOTE 5) tOEHZ D(A3) (NOTE 1) Q(A4) Q(A2) Single WRITE Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs DON'T CARE Notes: UNDEFINED 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 3.3V VDD, 3.3V I/O AC TEST CONDITIONS 3.3V I/O Output Load Equivalents Input pulse levels ....................VIH = (VDD/2.2) + 1.5V ................................................... VIL = (VDD/2.2) - 1.5V Input rise and fall times......................................... 1ns Input timing reference levels ........................ VDD/2.2 Output reference levels................................VDDQ/2.2 Output load .................................. See Figures 1 and 2 Figure 1 Q Z O= 50 50 VT = 1.5V Figure 2 3.3V VDD, 2.5V I/O AC TEST CONDITIONS Input pulse levels ................VIH = (VDD/2.64) + 1.25V ............................................... VIL = (VDD/2.64) - 1.25V Input rise and fall times......................................... 1ns Input timing reference levels ...................... VDD/2.64 Output reference levels...................................VDDQ/2 Output load .................................. See Figures 3 and 4 +3.3V 317 Q 5pF 351 2.5V VDD, 2.5V I/O AC TEST CONDITIONS 2.5V I/O Output Load Equivalents Input pulse levels .....................VIH = (VDD/2) + 1.25V .................................................... VIL = (VDD/2) - 1.25V Input rise and fall times......................................... 1ns Input timing reference levels ........................... VDD/2 Output reference levels..................................... VDD/2 Output load .................................. See Figures 3 and 4 Figure 3 Q Z O= 50 50 VT = 1.25V LOAD DERATING CURVES Micron 1 Meg x 18, 512K x 32, and 512K x 36 SyncBurst SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. Figure 4 +2.5V 225 Q 225 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 22 5pF Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM SNOOZE MODE SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time ZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. t SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SNOOZE MODE ZZ active to input ignored CONDITIONS SYMBOL ZZ VIH MAX UNITS NOTES ISB2Z 30 tZZ 2(tKC) mA ns 1 ns 1 ns 1 ns 1 ZZ inactive to input sampled tRZZ ZZ active to snooze current tZZI tRZZI ZZ inactive to exit snooze current Notes: MIN 2(tKC) 2(tKC) 0 1. This parameter is sampled. Figure 5 SNOOZE MODE WAVEFORM CLK t ZZ ZZ I t RZZ t ZZI SUPPLY I ISB2Z t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON'T CARE 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) TEST ACCESS PORT (TAP) Test Clock (TCK) The SRAM incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure 6. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Figure 7.) Disabling the JTAG Feature These pins/balls can be left floating (unconnected), if the JTAG function is not to be implemented. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Figure 6 TAP Controller State Diagram 1 TEST-LOGIC RESET 0 RUN-TEST/ IDLE Test Data-Out (TDO) The TDO output ball is used to serially clock dataout from the registers. The output is active depending upon the current state of the TAP state machine. (See Figure 5.) The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Figure 7.) 0 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 1 0 1 CAPTURE-DR CAPTURE-IR 0 Figure 7 TAP Controller Block Diagram 0 SHIFT-DR 0 SHIFT-IR 1 0 0 1 EXIT1-DR 1 EXIT1-IR Bypass Register 1 2 1 0 0 0 PAUSE-DR 0 PAUSE-IR TDI 0 Selection Circuitry Instruction Register 31 30 29 . 1 0 1 EXIT2-DR 0 Identification Register x . 1 1 0 TDO . 2 1 0 EXIT2-IR 1 UPDATE-DR . Selection Circuitry . . . . 2 1 0 Boundary Scan Register* UPDATE-IR 1 0 TCK TMS Note: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 TAP CONTROLLER x = 75 for the x18 configuration, x = 75 for the x32 configuration, x = 75 for the x36 configuration. 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM Performing a TAP Reset to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK. Data is output on the TDO pin/ball on the falling edge of TCK. Identification (ID) Register The ID register is loaded with a vendor-specific, 32bit code during the Capture-DR state when the IDCODEcommand is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins/balls as shown in Figure 5. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the boardlevel serial test data path. TAP INSTRUCTION SET Overview Eight different instructions are possible with the threebit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 75-bit-long register, the x32 configuration has a 75-bit-long register, and the x18 configuration has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins/balls when the controller is moved 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 EXTEST EXTEST is a mandatory 1149.1 instruction which is tobe executed whenever the instruction register is loadedwith all 0s. EXTEST is not implemented in this 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. SRAM TAP controller, and therefore this device is not compliant to1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controller is in a ShiftDR state. It also places all SRAM outputs into a High-Z state. BYPASS SAMPLE/PRELOAD When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional pins/balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 Reserved These instruction are not implemented but are reserved for future use. Do not use these instructions. 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM TAP TIMING 1 2 Test Clock (TCK) 3 tTHTL tMVTH tTHMX tDVTH tTHDX t TLTH 4 5 6 tTHTH Test Mode Select (TMS) Test Data-In (TDI) tTLOV tTLOX Test Data-Out (TDO) DON'T CARE UNDEFINED TAP AC ELECTRICAL CHARACTERISTICS (Notes 1,2) (+10C TJ +110C; + 2.4V VDD + 2.6V) DESCRIPTION SYMBOL MIN MAX Clock Clock cycle time tTHTH 100 Clock frequency fTF Clock HIGH time tTHTL 40 ns Clock LOW time tTLTH 40 ns Output Times TCK LOW to TDO unknown tTLOX 0 ns TCK LOW to TDO valid t TDI valid to TCK HIGH tDVTH 10 ns TCK HIGH to TDI invalid tTHDX 10 ns Setup Times TMS setup tMVTH 10 ns Capture setup tCS 10 ns Hold Times TMS hold tTHMX 10 ns Capture hold tCH 10 ns ns 10 20 TLOV UNITS MHz ns Notes: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditons are specified using the load in Figure 7. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM TAP AC TEST CONDITIONS Figure 7 TAP AC Output Load Equivalent Input pulse levels ........................................... VSS to 2.5V Input rise and fall times ..............................................1ns Input timing reference levels.................................. 1.25V Output reference levels ........................................... 1.25V Test load termination supply voltage .................... 1.25V 1.25V 50 TDO Z O= 50 20pF 3.3V VDD, TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (+10C TJ +110C; +3.135V VDD +3.465V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage CONDITIONS 0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) IOLC = 100A IOLT = 2mA IOHC = -100A IOHT = -2mA SYMBOL MIN MAX UNITS NOTES VIH VIL ILI ILO 2.0 -0.3 -5.0 -5.0 VDD + 0.3 0.8 5.0 5.0 V V A A 1, 2 1, 2 0.7 0.8 V V V V 1 1 1 1 VOL1 VOL2 VOH1 VOH2 2.9 2.0 2.5V VDD, TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (+10C TJ +110C; +3.135V VDD +3.465V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Notes: CONDITIONS 0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) IOLC = 100A IOLT = 2mA IOHC = -100A IOHT = -2mA SYMBOL MIN MAX UNITS NOTES VIH VIL ILI ILO 1.7 -0.3 -5.0 -5.0 VDD + 0.3 0.7 5.0 5.0 V V A A 1, 2 1, 2 0.2 0.7 V V V V 1 1 1 1 VOL1 VOL2 VOH1 VOH2 2.1 1.7 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH (AC) VDD + 1.5V for t tKHKH/2 Undershoot:VIL (AC) -0.5V for t tKHKH/2 Power-up:VIH +2.6V and VDD 2.4V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD#, R/W#, etc.) may not have pulse widths less than tKHKL (MIN) or operate at frequencies exceeding fKF (MAX). 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM IDENTIFICATION REGISTER DEFINITIONS INSTRUCTION FIELD 512K X 18 xxxx REVISION NUMBER (31:28) DEVICE DEPTH (27:23) DEVICE WIDTH (22:18) MICRON DEVICE ID (17:12) MICRON JEDEC ID CODE (11:1) ID Register Presence Indicator (0) DESCRIPTION Reserved for version number. 00111 Defines depth of 512K or 1Mb words. 00011 Defines width of x18, x32, or x36 bits. xxxxxx Reserved for future use. 00000101100 1 Allows unique identification of SRAM vendor. Indicates the presence of an ID register. SCAN REGISTER SIZES REGISTER NAME Instruction Bypass ID Boundary Scan BIT SIZE x18: 75 3 1 32 x32: 75 x36: 75 INSTRUCTION CODES INSTRUCTION CODE EXTEST 000 IDCODE 001 SAMPLE Z 010 RESERVED SAMPLE/PRELOAD 011 100 RESERVED RESERVED BYPASS 101 110 111 DESCRIPTION Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 165-Ball FBGA Boundary Scan Order (x18) FBGA BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 SIGNAL NAME MODE (LB0#) SA SA SA SA SA SA SA SA SA ZZ NC NC NC NC NC DQa DQa DQa DQa DQa DQa DQa DQa DQa NC NC NC NC SA SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK NC NC CE2# 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 165-Ball FBGA Boundary Scan Order (x18) BALL ID 1R 6N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J 11G 11F 11E 11D 11C 10F 10E 10D 10G 11A 10A 10B 9A 9B 8A 8B 7A 7B 6B 11B 1A 6A FBGA BIT# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 30 SIGNAL NAME BWa# NC BWb# NC CE2 CE# SA SA NC NC NC NC NC NC DQb DQb DQb DQb DQb DQb DQb DQb DQb NC NC NC NC SA SA SA SA SA1 SA0 BALL ID 5B 5A 4B 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G 1J 1K 1L 1M 1N 2K 2L 2M 2J 3P 3R 4R 4P 6P 6R Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 165-Ball FBGA Boundary Scan Order (x32) FBGA BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 SIGNAL NAME MODE (LB0#) SA SA SA SA SA SA SA SA SA ZZ NF DQa DQa DQa DQa DQa DQa DQa DQa DQb DQb DQb DQb DQb DQb DQb DQb NF NF SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK NC NC 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 165-Ball FBGA Boundary Scan Order (x32) BALL ID 1R 6N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J 11G 11F 11E 11D 10G 10F 10E 10D 11C 11A 10A 10B 9A 9B 8A 8B 7A 7B 6B 11B 1A FBGA BIT# 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 31 SIGNAL NAME CE2# BWa# BWb# BWC# BWD# CE2 CE# SA SA NC NF DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd DQd DQd NF SA SA SA SA SA1 SA0 BALL ID 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G 1J 1K 1L 1M 2J 2K 2L 2M 1N 3P 3R 4R 4P 6P 6R Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 165-Ball FBGA Boundary Scan Order (x36) FBGA BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SIGNAL NAME MODE (LB0#) SA SA SA SA SA SA SA SA SA ZZ NF/DQPa DQa DQa DQa DQa DQa DQa DQa DQa DQb DQb DQb DQb DQb DQb DQb DQb NF/DQPb NC SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 165-Ball FBGA Boundary Scan Order (x36) BALL ID 1R 6N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J 11G 11F 11E 11D 10G 10F 10E 10D 11C 11A 10A 10B 9A 9B 8A 8B 7A 7B 6B FBGA BIT# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 32 SIGNAL NAME NC NC CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA NC NF/DQPc DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd DQd DQd NF/DQPd SA SA SA SA SA1 SA0 BALL ID 11B 1A 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G 1J 1K 1L 1M 2J 2K 2L 2M 1N 3P 3R 4R 4P 6P 6R Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) +0.10 -0.20 20.10 0.10 22.10 0.65 TYP 0.32 +0.06 -0.10 0.625 (TYP) SEE DETAIL A 14.00 0.10 16.00 0.20 PIN #1 ID 0.15 +0.03 -0.02 1.40 0.05 GAGE PLANE 1.60 MAX 0.10 0.10 +0.10 -0.05 0.60 0.15 1.00 TYP 0.10 0.60 0.15 DETAIL A Notes: MAX MIN 1. All dimensions in inches (millimeters) -------------- or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM 165-BALL FBGA 0.85 0.075 0.12 C SEATING PLANE C BALL A11 165X O 0.45 R BALL DIAMETER REFERS ST REFLOW CONDITION. THE EFLOW DIAMETER IS O 0.40 10.00 BALL A1 PIN A1 ID 1.00 TYP 1.20 MAX PIN A1 ID 7.50 0.05 14.00 15.00 0.10 7.00 0.05 1.00 TYP MOLD COMPOUND: EPOXY NOVOLAC 6.50 0.05 SUBSTRATE: PLASTIC LAMINATE 5.00 0.05 SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 3 SOLDER BALL PAD: O .33mm 13.00 0.10 Notes: MAX MIN 1. All dimensions in inches (millimeters) -------------- or typical where noted. DATA SHEET DESIGNATION Advance: This data sheet contains initial descriptions of products still under development. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc. 0.16m Process ADVANCE 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, SCD SYNCBURST SRAM REVISION HISTORY * Rev. A, Pub. 6 /02.........................................................................................................................................................6/02 (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. Pentium is a registered trademark of Intel Corporation. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM MT58L1MY18P1_16_A.fm - Rev A; Pub 6/02 35 (c)2002, Micron Technology Inc.