HD74HC Series Common Information
September 2000
Customer Service Division
Semiconductor & Integrated Circuits
Hitachi, Ltd.
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Outline of Hitachi High-Speed CMOS Logic
1
Outline of Hitachi High-Speed CMOS Logic
Features of High-Speed CMOS Logic
Hitachi’s HS-CMOS logics–the HD74HC series–and the HCT series based on the EIA/JEDEC
specification. Their specification are shown in the Maximum Ratings and the Electrical Characteristics
Tables. The HS-CMOS has the characteristics of both standard CMOS logic series and LS-TTL series.
The features of this logic are:
High-Speed equivalent to the LS-TTL’s
Capable of driving 10LS-TTL loads
(Capable of driving 15LS-TTL loads in bus drivers)
Maximum input current of ± 1 µA at 6 V power supply
Wide supply voltage range: HC series 2 to 6 V
HCT series 4.5 to 5.5 V
Wide noise margin
VCC assurance of Electrical Characteristics at 2.0, 4.5 and 6.0 V
Low Static Power Consumption 1/2 of EIA/JEDEC
Type Name of High-Speed CMOS Logic
The JEDEC has divided the HS-CMOS’s into two types: HC and HCT. The HC type has the CMOS logic
level for inputs and outputs with buffers. The HCT type has the TTL logic level for inputs and the outputs
have buffers.
The industry-standarized maximum ratings and recommended operating range are shown below. Limits for
the static characteristics are shown below (right): Table 1 is in the industry-standard and Table 2 is the
Hitachi specifications.
The Hitachi specifications is used throughout this data book. Additional specification are shown in the
individual data sheets. Switching characteristics are specified under the following conditions:
Input pulse voltage: + VCC
Load capacitance: 50 pF
Input pulse rise/fall time: 6 ns
Switching times measured from 50% point of input voltage to 50% point of output voltage
Three different supply voltages: 2.0, 4.5 and 6.0 V
Outline of Hitachi High-Speed CMOS Logic
2
Input Levels of Each Series Type (VCC = 5 V)
Input level
Type VIH VIL Remarks
HC series 3.5 V 1.5 V
HCT series 2.0 V 0.8 V TTL logic level for inputs
Type Name of HS-CMOS Logic
Package Code
(P : Plastic DIP,FP:Small outline package (EIAJ TYPE),
RP : Small outline package (JEDEC TYPE))
Individual device code
2 or 3-digit:same pin connection and function
with its corresponding device
in LS-TTL
4–digit:same pin connection and function
with the 14000B series CMOS)
Type code (HC,HCT)
HD74
Absolute Maximum Ratings (Voltages Referenced to GND)
Item Symbol Rating Unit
Supply voltage VCC –0.5 to +7 V
I/O voltage VIN, VOUT –0.5 to VCC +0.5 V
I/O diode current IIK, IOK ±20 mA
Output current IO±25 mA
VCC, GND current ICC, IGND ±50 mA
Power dissipation PT500 mW
Storage temperature Range Tstg –65 to +150 ˚C
Additional specification values are shown on the individual data sheets.
Outline of Hitachi High-Speed CMOS Logic
3
Recommended Operating Range
HD74HC
Item Symbol Rating Unit Condition
Supply voltage VCC 2 to 6 V
I/O voltage VIN, VOUT 0 to VCC V
Operating temperature Ta –40 to +85 ˚C
Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V
0 to 500 VCC = 4.5 V
0 to 400 VCC = 6.0 V
HD74HCT
Item Symbol Rating Unit Condition
Supply voltage VCC 4.5 to 5.5 V
I/O voltage VIN, VOUT 0 to VCC V
Operating temperature Ta –40 to +85 ˚C
Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V
0 to 500 VCC = 4.5 V
0 to 400 VCC = 6.0 V
HD74HC14, HC132
Item Symbol Rating Unit Condition
Input rise/fall time tr, tf 0 to unlimited ns VCC = 2.0 V
0 to unlimited VCC = 4.5 V
0 to unlimited VCC = 6.0 V
HD74HC123A, HC221, HC423A
Item Symbol Rating Unit Condition
A, B Input rise/fall time tr, tf 0 to unlimited ns VCC = 2.0 V
0 to unlimited VCC = 4.5 V
0 to unlimited VCC = 6.0 V
CLR Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V
0 to 500 VCC = 4.5 V
0 to 400 VCC = 6.0 V
Outline of Hitachi High-Speed CMOS Logic
4
HD74HC4538
Item Symbol Rating Unit Condition
A, B Input rise/fall time tr, tf 0 to unlimited ns VCC = 2.0 V
0 to unlimited VCC = 4.5 V
0 to unlimited VCC = 6.0 V
CD Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V
0 to 500 VCC = 4.5 V
0 to 400 VCC = 6.0 V
HD74HC540, HC541
Item Symbol Rating Unit Condition
A Input rise/fall time tr, tf 0 to unlimited ns VCC = 2.0 V
0 to unlimited VCC = 4.5 V
0 to unlimited VCC = 6.0 V
G Input rise/fall time tr, tf 0 to 1000 ns VCC = 2.0 V
0 to 500 VCC = 4.5 V
0 to 400 VCC = 6.0 V
Outline of Hitachi High-Speed CMOS Logic
5
Table 1 EIA/JEDEC Format for High-Speed CMOS Specifications
Limits
+25˚C –40 to
+85˚C
Parameters Symbol VCC(V) min max min max Unit Test Conditions
Input voltage HC Series VIH 2.0 1.5 1.5 V
4.5 3.15 3.15
6.0 4.2 4.2
HCT Series 4.5 to
5.5 2.0 2.0
HC Series VIL 2.0 0.3 0.3 V
4.5 0.9 0.9
6.0 1.2 1.2
HCT Series 4.5 to
5.5 0.8 0.8
Output HC Standard VOH 2.0 1.9 1.9 V Vin = VIH or VIL Iout = –20 µA
voltage Series type 4.5 4.4 4.4
6.0 5.9 5.9
4.5 3.98 3.84 Iout = –4.0 mA
6.0 5.48 5.34 Iout = –5.2 mA
Bus driver 2.0 1.9 1.9 Vin = VIH or VIL Iout = –20 µA
type 4.5 4.4 4.4
6.0 5.9 5.9
4.5 3.98 3.84 Iout = –6.0 mA
6.0 5.48 5.34 Iout = –7.8 mA
HCT Standard 4.5 4.4 4.4 Vin = VIH or VIL Iout = –20 µA
Series type 4.5 3.98 3.84 Iout = –4.0 mA
Bus driver 4.5 4.4 4.4 Vin = VIH or VIL Iout = –20 µA
type 4.5 3.98 3.84 Iout = –6.0 mA
HC Standard VOL 2.0 0.1 0.1 V Vin = VIH or VIL Iout = 20 µA
Series type 4.5 0.1 0.1
6.0 0.1 0.1
4.5 0.26 0.33 Iout = 4.0 mA
6.0 0.26 0.33 Iout = 5.2 mA
Bus driver 2.0 0.1 0.1 Vin = VIH or VIL Iout = 20 µA
type 4.5 0.1 0.1
6.0 0.1 0.1
Outline of Hitachi High-Speed CMOS Logic
6
Limits
+25˚C –40 to
+85˚C
Parameters Symbol VCC(V) min max min max Unit Test Conditions
Output HC Bus driver 4.5 0.26 0.33 V Vin = VIH or VIL Iout = 6.0 mA
voltage Series type 6.0 0.26 0.33 Iout = 7.8 mA
HCT Standard 4.5 0.1 0.1 Vin = VIH or VIL Iout = 20 µA
Series type 4.5 0.26 0.33 Iout = 4.0 mA
Bus driver 4.5 0.1 0.1 Vin = VIH or VIL Iout = 20 µA
type 4.5 0.26 0.33 Iout = 6.0 mA
Input leakage HC Series II6.0 ±0.1 ±1.0 µA Vin = VCC or GND
current HCT Series 5.5 ±0.1 ±1.0
Analog switch off- HC Series IS(off) 6.0 ±0.1 ±1.0 µA Vin = VIH or VIL
state current HCT Series 5.5 ±0.1 ±1.0 |VS| = VCC or VCC – VEE
3-state output off- HC Series IOZ 6.0 ±0.5 ±5.0 µA Vin = VIH or VIL
state current HCT Series 5.5 ±0.5 ±5.0 Vout = VCC or GND
Quiescent HC SSI ICC 6.0 2.0 20 µA Vin = VCC or GND
supply Series FF 6.0 4.0 40 Iout = 0 µA
current MSI 6.0 8.0 80
HCT SSI 5.5 2.0 20
Series FF 5.5 4.0 40
MSI 5.5 8.0 80
Outline of Hitachi High-Speed CMOS Logic
7
Table 2 Hitachi High-Speed CMOS Series Specifications
Limits
+25˚C –40 to
+85˚C
Parameters Symbol VCC(V) min max min max Uni t Test Conditions
Input voltage HC Series VIH 2.0 1.5 1.5 V
4.5 3.15 3.15
6.0 4.2 4.2
HCT Series 4.5 to
5.5 2.0 2.0
HC Series VIL 2.0 0.5 0.5 V
4.5 1.35 1.35
6.0 1.8 1.8
HCT Series 4.5 to
5.5 0.8 0.8
Output HC Standard VOH 2.0 1.9 1.9 V Vin = VIH or VIL IOH = –20 µA
voltage Series type 4.5 4.4 4.4
6.0 5.9 5.9
4.5 4.18 4.13 IOH = –4.0 mA
6.0 5.68 5.63 IOH = –5.2 mA
Bus driver 2.0 1.9 1.9 Vin = VIH or VIL IOH = –20 µA
type 4.5 4.4 4.4
6.0 5.9 5.9
4.5 4.18 4.13 IOH = –6.0 mA
6.0 5.68 5.63 IOH = –7.8 mA
HCT Standard 4.5 4.4 4.4 Vin = VIH or VIL IOH = –20 µA
Series type 4.5 4.18 4.13 IOH = –4.0 mA
Bus driver 4.5 4.4 4.4 Vin = VIH or VIL IOH = –20 µA
type 4.5 4.18 4.13 IOH = –6.0 mA
HC Standard VOL 2.0 0.1 0.1 V Vin = VIH or VIL IOL = 20 µA
Series type 4.5 0.1 0.1
6.0 0.1 0.1
4.5 0.26 0.33 V Vin = VIH or VIL IOL = 4.0 mA
6.0 0.26 0.33 IOL = 5.2 mA
Bus driver 2.0 0.1 0.1 Vin = VIH or VIL IOL = 20 µA
type 4.5 0.1 0.1
6.0 0.1 0.1
Outline of Hitachi High-Speed CMOS Logic
8
Limits
+25˚C –40 to
+85˚C
Parameters Symbol VCC(V) min max min max Uni t Test Conditions
Output HC Bus driver VOL 4.5 0.26 0.33 V Vin = VIH or VIL IOL = 6.0 mA
voltage Series type 6.0 0.26 0.33 IOL = 7.8 mA
HCT Standard 4.5 0.1 0.1 Vin = VIH or VIL IOL = 20 µA
Series type 4.5 0.26 0.33 IOL = 4.0 mA
Bus driver 4.5 0.1 0.1 Vin = VIH or VIL IOL = 20 µA
type 4.5 0.26 0.33 IOL = 6.0 mA
Input leakage HC Series II6.0 ±0.1 ±1.0 µA Vin = VCC or GND
current HCT Series 5.5 ±0.1 ±1.0
Analog Switch HC Series IS(off) 6.0 ±0.1 ±1.0 µA Vin = VIH or VIL
Off-state Current HCT Series 5.5 ±0.1 ±1.0 |VS| = VCC or VCC – VEE
3-state output Off- HC Series IOZ 6.0 ±0.5 ±5.0 µA Vin = VIH or VIL
state Current HCT Series 5.5 ±0.5 ±5.0 Vout = VCC or GND
Quiescent HC SSI ICC 6.0 1.0 10 µA Vin = VCC or GND
Supply Series FF 6.0 2.0 20 Iout = 0 µA
Current MSI 6.0 4.0 40
HCT SSI 5.5 1.0 10
Series FF 5.5 2.0 20
MSI 5.5 4.0 40
Outline of Hitachi High-Speed CMOS Logic
9
Symbols and Terms Defined for HD74HC Series
1. Explanation of Symbols Used in Electrical Characteristics and Recommended Operating
Conditions
1.1 DC characteristics
Symbol Term Description
VIH “H” level input voltage “H” level input voltage to ensure that a logic element
operates under some constraint.
VIL “L” level input voltage “L” level input voltage to ensure that a logic element
operates under some constraint.
VOL “L” level output voltage Output voltage in effect when, under the input condition for
bringing the output Low, the rated output current is allowed
to flow to the output terminal.
VOH “H” level output voltage Output voltage in effect when, under the input condition for
bringing the output High, the rated output current is allowed
to flow to the output terminal.
VT+Forward input threshold voltage Input voltage in effect when the operation of a logic element
varies as the input is allowed to go up from a voltage level
lower than the forward input threshold voltage VT-.
VT-Reverse input threshold voltage Input voltage in effect when the operation of a logic element
varies as the input is allowed to go up from a voltage level
lower than the reverse input threshold voltage VT+.
VHHysteresis voltage Differnce between forward input threshold voltage VT+ and
reverse threshold voltage VT-.
IOH “H” level output current Output current that flows out when, under the condition for
bringing the output High, the rated output voltage VOUT is
applied to the output terminal.
IOL “L” level output current Output current that flows out when, under the condition for
bringing the output High, the rated output voltage V
OU
T is
applied to the output terminal.
IIN Input leakage current Input current that flows in when the rated maximum input
voltage is applied to the input terminal.
IIH “H” level input current Input current that flows in when the rated “H” level voltage is
applied to the input.
IIL “L” level input current Input current that flows out when the rated “L” level voltage
is applied to the input.
IOZ Off-state output current (high
impedance) Current that flows to the 3-state output of an element under
the input condition for briging the output to High impedance.
Is(off) Analog switch off-state current Current that flows to the analog switch of an element under
the input condition for bringing the switch to off-state.
ICC Quiescent supply current Current that flows to the supply terminal (V
CC
) under the
rated input condition.
Outline of Hitachi High-Speed CMOS Logic
10
1.2 AC characteristics
Symbol Term Description
fmax Maximum clock frequency Maximum clock frequency that maintains the stable changes in
output logic level in the rated sequence under the I/O condition
allowing clock pulses to change the output state.
tTLH Rise (transient) time Rated time from “L” level to “H” level of a waveform during the
defined transient period changing from “L” level to “H” level.
tTHL Fall (transient) time Rated time from “H” level to “L” level of a waveform during the
defined transient period changing from “H” level to “L” level.
tPLH Output rise propagation delay
time Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the output
changing from “L” level to “H” level.
tPHL Output fall propagation delay
time Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the output
changing from “H” level to “L” level.
tHZ 3-state output disable time (“H”
level) Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the 3-state
output changing from “H” level to the high impedance state.
tLZ 3-state output disable time (“L”
level) Delay time between the rated voltatge levels of an I/O voltage
waveform under a defined load condition, with the 3-state
output changing from “L” level to the high impedance state
tZH 3-state output enable time (“H”
level) Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the 3-state
output changing from the high impedance state to “H” level.
tZL 3-state output enable time (“L”
level) Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the 3-state
output changing from the high impedance state to “L” level.
twPulse width Duration of time between the rated levels from a leading edge
to a trailing edge of a pulse waveform.
thHold time Time in which to hold date at the specified input terminal after
a change at another related input terminal (e.g., clock input).
tsu Setup time Time in which to set up and keep data at the specified input
terminal before a change at another related input terminal
(e.g., clock input).
trm Removal time Time period between the time when data at the specified input
terminal is released and the time when another related input
terminal (e.g., clock input) can be changed.
Cin Input capacitance Capacitance between GND terminal and an input terminal to
which 0 V is applied.
Outline of Hitachi High-Speed CMOS Logic
11
2. Explanation of Symbols Used in Function Table
Symbol Description
H High level (in steady state; noted "H" or “H” level in sentences)
L Low level (in steady state; noted "L" or “L” level in sentences)
Transition from L level to H level
Transition from H level to L level
X Either H or L
Z 3-state output off (high impedance)
a·····h Input level of steady state for each of inputs A-H
Q0Q level immediately before the indicated input condition is established
Q0Complement of Q
QnQ level immediately before the latest active change ( or ) occurs
Single H level pulse
Single L level pulse
TOGGLE Each output is changed to the complement of the preceding state by an active input
change ( or )
Measuring Method of AC Characteristics
Loading Circuit
Output Output Output
Measuring
point Measuring
point
Measuring
point
VCC
CL
S1
RL
RL
VCC
RL
CL
CL
(a) CMOS output (b) Open drain output (c) 3-state output
Notes: 1. CL includes the floating capacitance of probe and jig.
2. RL = 1 k (except for a particular specification)
Outline of Hitachi High-Speed CMOS Logic
12
Waveforms (Mutual relationship of waveforms)
Pulse Width (TW)
74HC Series
VCC
VCC
tr = 6ns tf = 6ns
tf = 6ns tr = 6ns
90% 90%
90% 90%
50% 50%
10% 10%
50% 50%
10% 10%
tw
tw
GND
GND
H-level Pulse
L-level Pulse
74HCT Series
3.0V
3.0V
tr = 6ns tf = 6ns
tf = 6ns tr = 6ns
2.7V 2.7V
2.7V 2.7V
1.3V 1.3V
0.3V 0.3V
1.3V 1.3V
0.3V 0.3V
tw
tw
GND
GND
H-level Pulse
L-level Pulse
Outline of Hitachi High-Speed CMOS Logic
13
Setup Time and Hold Time
74HC Series
50%
50%
90%
10%
50%
50%
50%
trVCC
GND
VOH
VOL
VOH
VOL
tsu th
tsu th
Clock or Latch
Enable Input *1
Positive
Data
Input
Negative
Data
Input
74HCT Series
1.3V
1.3V
90%
10%
1.3V
1.3V
1.3V
tr3.0V
GND
3.0V
GND
3.0V
GND
tsu th
tsu th
Clock or Latch
Enable Input *1
Positive
Data
Input
Negative
Data
Input
Note: Waveform for negative edge sensitive circuits will be inverted.
Outline of Hitachi High-Speed CMOS Logic
14
Removal Time
74HC Series
50%
90%
90%
50%
10%
50%
10%
10%
90% tr
VCC
GND
VCC
GND
VCC
GND
Clock
Input *1
Active Low
Clear or
Enable
Active
High Clear or
Enable
tf
trem
tr
trem
74HCT Series
1.3V
90%
90%
1.3V
10%
1.3V
10%
10%
90% tr
3.0V
GND
3.0V
GND
3.0V
GND
Clock
Input *1
Active Low
Clear or
Enable
Active
High Clear or
Enable
tf
trem
tr
Note: Waveform for negative edge sensitive circuits will be inverted.
Outline of Hitachi High-Speed CMOS Logic
15
Waveforms (Mutual relationship of waveforms)
Propagation Delay Time, Output Rise Time and Output Fall time
74HC Series
90%
50%
10%
90%
50%
10%
90%
90% 90%
50%
50% 50%
10%
90%
50%
10%
10% 10%
tr = 6ns tf = 6ns
tTLH
tTLH
tTHL
tTHL
tPHL
tPLH
tPLH
tPHL
VCC
GND
VOH
VOL
VOH
VOL
Input
Same-phase Output
Inverse-phase Output
Outline of Hitachi High-Speed CMOS Logic
16
74 HCT Series
90%
1.3V
10%
2.7V
1.3V
0.3V
90%
90% 90%
1.3V
1.3V 1.3V
10%
2.7V
1.3V
0.3V
10% 10%
tr = 6ns tf = 6ns
tTLH
tTLH
tTHL
tTHL
tPHL
tPLH
tPLH
tPHL
3.0V
GND
VOH
VOL
VOH
VOL
Input
Same-phase Output
Inverse-phase Output
Outline of Hitachi High-Speed CMOS Logic
17
Waveforms (Mutual relationship of waveforms)
Three-state Output, Enable Time and Disable Time
74HC Series
10%
10%
50%
90%
10%
50%
90%
90%
tLZ
tHZ
S1 : VCC
S1 : VCC
S1 : GNDS1 : GND
tZL
tZH 50%
50%
tf = 6ns tr = 6ns
Output Control
(L-level Enable)
Waveform 1
Waveform 2
VCC
GND
VOH
VOL
VOH
VOL
74HCT Series
10%
0.3V
1.3V
2.7V
0.3V
1.3V
2.7V
90%
tLZ
tHZ
S1 : VCC
S1 : VCC
S1 : GND
S1 : GND
tZL
tZH 1.3V
1.3V
tf = 6ns tr = 6ns
Output Control
(L-level Enable)
Waveform 1
Waveform 2
3.0V
GND
VOH
VOL
VOH
VOL
Notes: 1. Waveform 1 is an output under the internal condition like “L” except for the output disabled by the
output control.
2. Waveform 2 is an output under the internal condition like “H” except for the output disabled by the
output control.
Precautions in System Design
18
Precautions in System Design
In the system design, the problems to be considered are described in the following items:
1. Transfer Characteristics
Since the transfer characteristics of gate circuit varies with the number of working inputs, care must be
taken to the noise margin. In the multiple input NOR gate, the P channel MOS is connected to VCC in
series and the N channel MOS is connected to GND in parallel. In the NAND gate, the connection is
reverse. The output voltage VOUT in the transition area becomes a value obtained by distributing the supply
voltage at a split ratio according to the ON resistance of P channel MOS and N channel MOS. In the
multiple input NOR and NAND gates, the fall of transfer characteristic, that is, VIN(voltage noise margin)
that enters in the transition area changes according to the number of inputs as shown in Figure 1.
Number of inputs
1234
Vin
Vout
Number of inputs
1234
Vin
Vout
Figure 1
As seen from the above, it becomes clear that:
In the NOR gate, “0” level noise margin VNL decreases, and “1” level noise margin VNH increases
according to the number of working inputs.
In the NAND gate, the noise margins are fully reversed.
Precautions in System Design
19
2. Output Impedance
The output impedance of CMOS logic gate is influenced by the circuit configuration, the number of
working inputs, logical state and supply voltage. There are two regions of output impedance depending on
the operation:
Constant impedance area in which P and N channel MOS’ operate in the nonsaturated state.
Constant current area in which P and N channel MOS’ operate in the pinch-off state.
In designing a system including an interface circuit, the above must be considered.
3. Output Short-Circuit
Because no protective circuitry is provided to limit the output current, an output inadvertently shorted to
VCC or GND on the HS-CMOS logic IC is limited to the current value determined by the pinch-off effect of
the P-channel MOS and N-channel MOS for the output. Notice that such output short-circuit current, if
allowed to flow for a long time, could result in increased power dissipation or in a melted wire due to
excessive current density through metalization or other performance failures. For operating stability and
reliability, the maximum output current should remain within the maximum rating.
4. Unused Inputs
As shown in Figure 2, unused inputs must be:
(1) Directly connected to VCC for NAND gate circuits.
(2) Directly connected to GND for NOR gate circuits.
(3) Connected to VCC or GND through a proper resistor (10 kor 100 k.).
This is required because the extremely high input impedance of CMOS logic makes it subject to noise.
This noise causes the output logic level to be unstable. Furthermore, in some cases, if a gate is not used or
a flip-flop is not used, both p-channel MOS and n-channel MOS may conduct, causing ICC to flow.
VCC VCC VCC
100 k
100 kGND
GND
Vout
Vout
Vin
Vin
Figure 2 Examples of Handling Unused Inputs
Precautions in System Design
20
5. Input Impedance
Since all the input protective diodes are biased reversely in the ordinary operations, the input impedance of
CMOS logic IC is extremely high. When converted into a leak current, it is about several tens (pA) at a
temperature of 25˚C or about one (nA) even at 100˚C. Thus, the matching for operating the CMOS logic
IC has only to be considered at a voltage level. In the actual interface to other IC’s, however, remember
that fan-out is limited according to a capacitance value because inputs measured in capacity.
6. Parallel Connection of Gate Circuits
If it is necessary to increase source or sinking current, the same type gate circuits can be connected in
parallel as shown in Figure 3.
IOS0
IOS0
IOS1
IOS1
IOS1
IOS1
Increase of
source current Increase of
sinking current Increase of
sinking current
Figure 3 Examples of Parallel Connection
The switching speed improved at the same time. The source and sinking current capacities also increase in
proportion to the number of inputs.
7. Wired OR Connection
The wired OR connection is unrecommendable and shall not be used in CMOS logic IC’s. The reason is
that if the two gate outputs are connected with A = B = 0 and C = D = 1 as shown in Figure 4, the output
voltage is a value with which the supply voltage is divided by each of the resistance values of active P and
N channel MOS’, on an about half level (VCC - GND).
A
B
C
D
Y
Figure 4 Wired OR Connection
Precautions in System Design
21
8. Input Capacitance
In the CMOS logic IC, there is capacitance between the input and the GND. In addition to the major
capacitance between the gate and the substrate, the capacitance of package, leads and input protection
circuit are also included. The change input capacitance depending on the input voltage results mainly from
the capacitance between the gate and the substrate. This input capacitance has an advantage of temporarily
storing date in it by opening/closing the transmission gate. On the other hand, however, remember that the
input capacitance may slow down switching speed of mutually connected gate and also may increase the
power dissipation. The input capacitance is usually about 5 (pF) as specified in the standard.
9. Output Capacitance
The whole output capacitance of CMOS logic IC is the sum of the drain capacitance of output MOS and the
external load capacitance. It may be considered that the former is about 10 (pF) per output. The
propagation delay time increases linealy in proportion to the increase of external load capacitance as
described previously. The power dissipation also increases according to it. Especially, be careful in
attaching a large capacity of around 1 (1µF) outside.
The peak current at the gate transition, as described previously, is limited by the output characteristics of P
and N channel MOS’. In the buffer circuit, the peak current may increase (to 100 mA or more).
Pay sufficient attention to the fact that the rise of temperature in the chip may cause metal migration on the
metal wiring layer. If the peak current for gate circuit is set to about 50 mA and the one for buffer circuit is
set to about 100 mA, no consideration is required.
Precautions in System Design
22
10. Features of 3-state Output Circuit
In a system that requires bus configuration, the 3-state output element is brought from the necessity to place
unnecessary circuits in the high output impedance state through control input to operate necessary circuit
selectively when tow or more circuit is connected to one bus line. Figure 5 shows the typical 3-state
circuit. When the Disable input of control terminal is at “1” level, the output is at low impedance by the
switch operation. When at “0” level, the output is at extremely high impedance of 104 (M) at a room
temperature. Remember that the number of 3-state elements connectable to one bus line is limited by the
switching speed and supply voltage.
Disable
In
VCC
Out
GND
Figure 5 3-state Output Circuit
Precautions in System Design
23
11. Static Power Dissipation
In the CMOS logic IC, the P channel MOS and N channel MOS are mutually connected each other.
Therefore, either P channel or N channel is cut off in the input potential level static state. There is no path
in which the current from the power supply flows. Actually, the reverse bias leak current in all the P-N
junction in the chip including parasitic P-N junction flows only. The supply current in this state is referred
to as static current consumption, and the power dissipation as static power dissipation. The static current
consumption is a total of leak currents, and its values are extremely small as listed in Table 1. Thus, the
static current consumption is almost proportional to the supply voltage and increases exponentially in
proportion to temperature.
Table 1
Static Current Consumption ICC(max)
Type VCC +25˚C –40 to +85˚C
HC series SSI 6.0 V 1.0 µA 10 µA
FF 2.0 µA 20 µA
MSI 4.0 µA 40 µA
HCT series SSI 5.5 V 1.0 µA 10 µA
FF 2.0 µA 20 µA
MSI 4.0 µA 40 µA
12. Dynamic Power Dissipation
Assuming that the square pulse waves (tr = tf = 0) as shown in Figure 7 are applied to the input of the
inverter shown in Figure 6, the output steps from “0” level to “1” level in response to the input fall from
“1” level to “0” level.
VCC
Vout
Vin
CL
GND
ICC(P)
ICC(N)
Figure 6 Inveter circuit
Precautions in System Design
24
T
Vin
Vout
ICC(P)
ICC(N)
Figure 7 Operating Voltage and current of inverter circuit
Actually, VOUT is not converted into square waveforms. The reason is that the sum total CL of the outputs
such as external load capacitance and drain capacitance are inverted by charging them from 0 to VCC. For
charging, supply current ICC(P) flows through the active P channel MOS from VCC. Contrary to this, when
the input goes from “0” level to “1” level, CL discharges and ICC(N) flows into GND through the N channel
MOS. The supply current caused by the charge/discharge is dynamic current dissipation, and the power
dissipation is dynamic power dissipation. If the average power dissipation is taken as PT, it is obtained
theoritically as follows:
The power dissipation when ICC(P) flows into the P channel MOS in Figure 6 is ICC(P) (VCC - VOUT). If an
average is taken by the one cycle of input pulse, the average power dissipation PTP of P channel MOS is:
P = 1/T I (V - V ) dtTP CC(P) CC OUT
0
T
ICC(P) = CL · d(VCC - VOUT)/dt
In the same manner, the average power dissipation of N channel MOS is:
P = 1/T I (V - GND) dtTN CC(N) OUT
0
T
ICC(N) = CL · d(VOUT - GND)/dt
Thus, the average dynamic power dissipation PT is:
PT = PTP + PTN
= 1/T · CL · VCC2
= f · CL · VCC2
f : Input pulse frequency
It is clear that the dynamic power dissipation varies with the frequency, load capacitance and supply
voltage.
Figure 8 shows the aspect.
Precautions in System Design
25
Power Dissipation PT (mW)
Operating frequency f (Hz)
1 k 10 k 100 k 1 M 10 M 100 M
0.0001
0.001
0.01
0.1
1.0
10
100
CL = 150 pF
CL = 50 pF
CL = 15 pF
CL = OPEN
Figure 8 Power Dissipation VS. Operating Frequency
This relation shows a case where the square wave input with tr = tf = 0 is assumed. In an actual case, the
input pulse is considered a trapezoidal waveform. Thus, remember that the transition state in which both P
channel MOS and N channel MOS are simultaneously activate and DC current flows from VCC into GND
during this time. If input is used at an intermediate level, such as crystal oscillator circuit and a linear
amplifier, and if the circuits such as a differentiation circuit, an integration circuit and an oscillation circuit
process gentle waveforms, pay attention to the increase of power dissipation.
13. Caution of Supply Voltage
To decouple noises, the capacitance of 0.01 to 0.1 (µF) should be attached externally between VCC and
GND.
14. Caution of Fan-out
The number of fan-outs of CMOS logic IC is virtually unlimited in terms of DC. The reason is that the
input current is the P-N junction leak current of input protection circuit at most and its value is actually
approximate to 0 because the input is connected to the gate electrodes and insulated from the substrate.
Therefore, the number of fan-outs is not a problem in terms of DC. In AC, there is a slightly different
circumstance. Since the input has a capacity of about 5 (pF), the output capacitance increases if the input is
connected to the output. If the input capacitance is taken as 5 (pF), for example, the whole load
capacitance CL (pF) at the time the number of fan-outs is n and load capacitance is CO (pF) is:
CL = 5 • n + CO (pF)
On the other hand, the propagation delay time increases in proportion to the output load capacitance CL.
The operating speed decreases according to the number of inputs (fan-outs) connected to the output.
Therefore, remember that the number of fan-outs is fairly limited if a high-speed operation is required.
Precautions in System Design
26
15. Cautions on Actual Operation
(1) The rise time and fall time of input waveforms should be 500 ns or less. Since the voltage gain is very
high near the threshold, the slightest ripples on the input voltage may cause the output to produce a
corresponding waveform, making the output operation unstable.
(2) The power line should be sufficiently filtered for the device. The input threshold voltage of the IC
varies with the supply voltage. A ripple on the power line may change the input threshold, causing the
same malfunction as noted in (1) above.
(3) Beware of a ringing (waveform distortion). Because the switching from “1” level to “0” level on vice
versa is very fast, the load capacitance plus the wiring inductance may cause a ringing. Care should be
taken to arrange the circuit configuration, PCB layout and wiring appropriately.
Application Note
27
Application Note
1. Input Protection Circuit
An Si-gate process is applied to Hitachi’s high-speed CMOS logic ICs.They have a thinner gate oxide
compared to conventional Al-gate CMOS logic ICs and are composed into finer patterns.
Therefore, an input protection circuit is necessary for the gate to be protected from surges at the input pins.
Since Al-gate CMOS logic ICs use a diffusion resistor as the input protection resistor (as shown in Figure
1a), input over-current flows directly to the power supply and the destruction of the protection diode may
occur.
On the other hand, using polysilicone as its input protection resistor (shown in Figure 1b), high-speed
CMOS logic ICs take the role of a current limiter to counter input over voltage.
GND
Poly-Si
resistor
Input
Input
VCC
GND
VCC
GND
GND
P well
P well
(a) Al-gate CMOS logic
(b) Si-gate CMOS logic
N+diffusion
resistor
N+
P+diffusion
resistor P+diffusion
resistor
P+
Poly-Si
resistor
Input Internal logic circuit
Input Internal logic circuit
N+diffusion
resistor
Internal
logic
circuit
Internal
logic
circuit
N sub VCC
N sub VCC
Figure 1 Input Protection Deevice and Equivalent Circuit
Application Note
28
2. Electric Static Discharge Immunity (ESD Immunity)
ESD immunity is evaluated by the capacitor discharge method shown in the test circuit of Figure 2. The
capacitor is 200 pF, accounting for the electrostatic capacitance of human bodies. Figure 3 shows an
example of ESD immunity of integrated circuits for each products series.
The ESD for high-speed CMOS logic is over ±200 V, which is the same level or better than LS-TTL.
C = 200 pF
Test Pin
GND
Figure 2 ESD Immunity Test Circuit
0 200 400100 300 500
Applied voltage (V)
1
2
10
20
30
40
50
60
70
80
90
95
3
4
5
Accumulated failure rate
HD74HC/HCT Series (HS-CMOS)
HD74S Series (S-TTL)
HD74LS Series (LS-TTL)
HD14000B Series (CMOS Logic)
HD17000 Series (industrial linear)
8-bit microcomputer (CMOS)
256k DRAM (NMOS)
Figure 3 ESD Immunity for Each Series
Application Note
29
3. Latch-Up
3.1 Latch-up
Latch-up is an inevitable phenomenon occurring from the basical structure of CMOS logic ICs.
Since CMOS has PMOS and NMOS on one chip, NPN and PNP transistors are made. These two types of
transistors are combined into a PNPN structure, in which a parasitic thyristor is formed (see Figure 4).
If excessive noise is applied to the input or output pins when the IC is operating, the parasitic thyristor will
turn on and the abnormal current will flow through the power supply pin to ground.
If the power supply is turned off, the IC will be restored to its normal state, however, the internal AI wiring
of the IC may melt thus causing the IC to be destroyed.
There are countermeasures to prevent latch-up as listed below
(1) Separate PMOS from NMOS.
(2) Shut down electrical paths between PNP and NPN transistors which form parasitic thyristors by its
layout pattern.
(3) Isolate each MOS transistor with an insulator to prevent the formation of parasitic thyristors.
Hitachi’s high-speed CMOS logic utilizes method (2)
VCC
VCC
In
Out
N-sub
(a) Parasitic PNP, NPN transistor (b) Equivalent circuit
R1
R1
R2
Q1Q2Q2
Q1
γB2
γB1
P+P+P+
N+N+
P+
Figure 4 Parasitic Thyristor