Outline of Hitachi High-Speed CMOS Logic
10
1.2 AC characteristics
Symbol Term Description
fmax Maximum clock frequency Maximum clock frequency that maintains the stable changes in
output logic level in the rated sequence under the I/O condition
allowing clock pulses to change the output state.
tTLH Rise (transient) time Rated time from “L” level to “H” level of a waveform during the
defined transient period changing from “L” level to “H” level.
tTHL Fall (transient) time Rated time from “H” level to “L” level of a waveform during the
defined transient period changing from “H” level to “L” level.
tPLH Output rise propagation delay
time Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the output
changing from “L” level to “H” level.
tPHL Output fall propagation delay
time Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the output
changing from “H” level to “L” level.
tHZ 3-state output disable time (“H”
level) Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the 3-state
output changing from “H” level to the high impedance state.
tLZ 3-state output disable time (“L”
level) Delay time between the rated voltatge levels of an I/O voltage
waveform under a defined load condition, with the 3-state
output changing from “L” level to the high impedance state
tZH 3-state output enable time (“H”
level) Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the 3-state
output changing from the high impedance state to “H” level.
tZL 3-state output enable time (“L”
level) Delay time between the rated voltage levels of an I/O voltage
waveform under a defined load condition, with the 3-state
output changing from the high impedance state to “L” level.
twPulse width Duration of time between the rated levels from a leading edge
to a trailing edge of a pulse waveform.
thHold time Time in which to hold date at the specified input terminal after
a change at another related input terminal (e.g., clock input).
tsu Setup time Time in which to set up and keep data at the specified input
terminal before a change at another related input terminal
(e.g., clock input).
trm Removal time Time period between the time when data at the specified input
terminal is released and the time when another related input
terminal (e.g., clock input) can be changed.
Cin Input capacitance Capacitance between GND terminal and an input terminal to
which 0 V is applied.