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P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
32M-BIT SINGLE VOLTAGE 3V ONLY
UNIFORM SECTOR FLASH MEMORY
FEATURES
GENERAL FEA TURES
• Single P ower Supply Operatio n
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
• Configuration
- 4,194,304 x 8 / 2,097,152 x 16 switchable
• Secto r structure
- 64KB(32KW) x 64
• Sector Protection/Chip Unprotect
- Pro vides sector gro up protect function to prevent pro-
gram o r erase o peratio n in the pro tected sector gro up
- Pro vides chip unprotect function to allow code changes
- Provides tempo rary sector g ro up unprotect function
for code changes in previously protected sector groups
• Secured Silico n Sector
- Provides a 128-word OTP area for permanent, se-
cure identificatio n
- Can be pro grammed and lo cked at f actory or by cus-
tomer
• Latch-up pro tected to 250mA fro m -1V to VCC + 1V
• Low VCC write inhibit is equal to o r less than 1.5V
• Compatible with JEDEC standard
- Pin-out and software compatible to single power sup-
ply Flash
PERFORMANCE
• High Performance
- F ast access time: 70R/90ns
- Page read time: 25ns
- Sector erase time: 0.5s (typ .)
- 4 wo rd/8 byte page read buffer
- 16 wo rd/ 32 byte write buff er: reduces pro gramming
time for multiple-wo rd/byte updates
• Low Power Consumption
- Active read current: 18mA(typ.)
- Active write current: 20mA(typ.)
- Standby current: 20uA(typ.)
• Minimum 100,000 erase/pro gram cycle
• 20-years data retentio n
SOFTW ARE FEA TURES
• Suppo rt Co mmo n Flash Interf ace (CFI)
- Flash device parameters stored on the device and
provide the host system to access.
• Program Suspend/Pro gram Resume
- Suspend program o peratio n to read other secto rs
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data/pro-
gram o ther secto rs
• Status Reply
- Data# po lling & To ggle bits pro vide detectio n o f pro-
gram and erase operation completion
HARDWARE FEATURES
• Ready/Busy (RY/BY#) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal
state machine to read mode
• WP#/ACC input
- Write pro tect (WP#) functio n allows pro tection high-
est or lowest sector, regardless of sector protection
settings
- ACC (high voltage) accelerates programming time
for higher throughput during system
PACKAGE
• 56-pin TSOP
•All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
The MX29LV320M H/L is a 32-mega bit Flash memory
organized as 4M bytes of 8 bits or 2M words of 16 bits.
MXIC's Flash memo ries offer the mo st cost-effective and
reliable read/write no n-v o latile random access memo ry.
The MX29LV320M H/L is pac kaged in 56-pin TSOP. It is
designed to be repro grammed and erased in system o r in
standard EPROM pro grammers.
The standard MX29LV320M H/L offers access time as
fast as 70ns, allowing o peration of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV320M H/L has separate chip enable
(CE#) and o utput enable (OE#) co ntrols.
MXIC's Flash memo ries augment EPROM functio nality
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MX29LV320M H/L
with in-circuit electrical erasure and progr amming. The
MX29LV320M H/L uses a command register to manage
this functio nality.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and pro gram cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
cycling. The MX29LV320M H/L uses a 2.7V to 3.6V
VCC supply to perfor m the High Reliability Erase and
auto Pro gram/Erase algo rithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
AUTOMATIC PROGRAMMING
The MX29LV320M H/L is byte/word/page programmable
using the A uto matic Programming algo rithm. The A uto-
matic Programming algor ithm makes the exter nal sys-
tem do no t need to have time out sequence nor to verify
the data pro grammed.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to D ATA# polling and a status bit to ggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm. The
Automatic Erase algor ithm automatically programs the
entire array prio r to electrical erase. The timing and veri-
ficatio n o f electrical erase are co ntrolled internally within
the device.
AUTOMATIC SECTOR ERASE
The MX29L V320M H/L is secto r(s) erasable using MXIC's
Auto Sector Erase algo rithm. Sector erase mo des allow
secto rs of the array to be erased in o ne erase cycle. The
Automatic Sector Erase algo rithm automatically programs
the specified secto r(s) prio r to electrical erase. The tim-
ing and verification of electrical erase are controlled inter-
nally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard micro processor write timings. The device will auto-
matically pre-progr am and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the co mmand register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched o n the rising edge o f WE# .
MXIC's Flash technology combines years of EPROM
e xperience to produce the highest le v els of quality, reli-
ability, and cost effectiveness. The MX29LV320M H/L
electrically erases all bits simultaneously using Fowler-
No rdheim tunneling. The bytes are pro grammed b y us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
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MX29LV320M H/L
PIN CONFIGURATION
56 TSOP
NC
NC
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
NC
A16
BYTE#
VSS
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
V
CC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
VSS
CE#
A0
NC
VIO
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
MX29LV320M H/L
(Normal Type)
SYMBOL PIN NAME
A0~A20 Address Input
Q0~Q14 Data Inputs/Outputs
Q15/A-1 Q15(Word Mode)/LSB addr(Byte Mode)
CE# Chip Enable Input
WE# Write Enable Input
OE# Output Enable Input
RESET# Hardware Reset Pin, Active Low
WP#/ACC Hardware Write Protect/Programming
Acceleration input
RY/BY# Read/Busy Output
BYTE# Selects 8 bit or 16 bit mode
VCC +3.0V single power supply
VI/O Output Buffer P ower (This input sho uld
be tied directly to VCC 2.7V~3.6V)
GND Device Gro und
N C Pin Not Connected Internally
PIN DESCRIPTION LOGIC SYMBOL
16 or 8
Q0-Q15
(A-1)
RY/BY#
A0-A20
CE#
OE#
WE#
RESET#
WP#/ACC
BYTE#
VI/O
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MX29LV320M H/L
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15(A-1)
A0-A20
CE#
OE#
WE#
WP#
BYTE#
RESET#
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MX29LV320M H/L
Sector Sector Address Sector Size (x8) (x16)
A20-A15 (Kbytes/Kwords) Address Range Address Range
SA0 000000 64/32 000000-0FFFF 000000-07FFF
SA1 000001 64/32 010000-1FFFF 008000-0FFFF
SA2 000010 64/32 020000-2FFFF 010000-17FFF
SA3 000011 64/32 030000-3FFFF 018000-1FFFF
SA4 000100 64/32 040000-4FFFF 020000-27FFF
SA5 000101 64/32 050000-5FFFF 028000-2FFFF
SA6 000110 64/32 060000-6FFFF 030000-37FFF
SA7 000111 64/32 070000-7FFFF 038000-3FFFF
SA8 001000 64/32 080000-8FFFF 040000-47FFF
SA9 001001 64/32 090000-9FFFF 048000-4FFFF
SA10 001010 64/32 0A0000-AFFFF 050000-57FFF
SA11 001011 64/32 0B0000-BFFFF 058000-5FFFF
SA12 001100 64/32 0C0000-CFFFF 060000-67FFF
SA13 001101 64/32 0D0000-DFFFF 068000-6FFFF
SA14 001110 64/32 0E0000-EFFFF 070000-77FFF
SA15 001111 64/32 0F0000-FFFFF 078000-7FFFF
SA16 010000 64/32 100000-0FFFF 080000-87FFF
SA17 010001 64/32 110000-1FFFF 088000-8FFFF
SA18 010010 64/32 120000-2FFFF 090000-97FFF
SA19 010011 64/32 130000-3FFFF 098000-9FFFF
SA20 010100 64/32 140000-4FFFF 0A0000-A7FFF
SA21 010101 64/32 150000-5FFFF 0A8000-AFFFF
SA22 010110 64/32 160000-6FFFF 0B0000-B7FFF
SA23 010111 64/32 170000-7FFFF 0B8000-BFFFF
SA24 011000 64/32 180000-8FFFF 0C0000-C7FFF
SA25 011001 64/32 190000-9FFFF 0C8000-CFFFF
SA26 011010 64/32 1A0000-AFFFF 0D0000-D7FFF
SA27 011011 64/32 1B0000-BFFFF 0D8000-DFFFF
SA28 011100 64/32 1C0000-CFFFF 0E0000-E7FFF
SA29 011101 64/32 1D0000-DFFFF 0E8000-EFFFF
SA30 011110 64/32 1E0000-EFFFF 0F0000-F7FFF
SA31 011111 64/32 1F0000-FFFFF 0F8000-FFFFF
MX29LV320M H/L SECTOR ADDRESS TABLE
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MX29LV320M H/L
Sector Sector Address Sector Size (x8) (x16)
A20-A15 (Kbytes/Kwords) Address Range Address Range
SA32 100000 64/32 200000-0FFFF 100000-07FFF
SA33 100001 64/32 210000-1FFFF 108000-0FFFF
SA34 100010 64/32 220000-2FFFF 110000-17FFF
SA35 100011 64/32 230000-3FFFF 118000-1FFFF
SA36 100100 64/32 240000-4FFFF 120000-27FFF
SA37 100101 64/32 250000-5FFFF 128000-2FFFF
SA38 100110 64/32 260000-6FFFF 130000-37FFF
SA39 100111 64/32 270000-7FFFF 138000-3FFFF
SA40 101000 64/32 280000-8FFFF 140000-47FFF
SA41 101001 64/32 290000-9FFFF 148000-4FFFF
SA42 101010 64/32 2A0000-AFFFF 150000-57FFF
SA43 101011 64/32 2B0000-BFFFF 158000-5FFFF
SA44 101100 64/32 2C0000-CFFFF 160000-67FFF
SA45 101101 64/32 2D0000-DFFFF 168000-6FFFF
SA46 101110 64/32 2E0000-EFFFF 170000-77FFF
SA47 101111 64/32 2F0000-FFFFF 178000-7FFFF
SA48 110000 64/32 300000-0FFFF 180000-87FFF
SA49 110001 64/32 310000-1FFFF 188000-8FFFF
SA50 110010 64/32 320000-2FFFF 190000-97FFF
SA51 110011 64/32 330000-3FFFF 198000-9FFFF
SA52 110100 64/32 340000-4FFFF 1A0000-A7FFF
SA53 110101 64/32 350000-5FFFF 1A8000-AFFFF
SA54 110110 64/32 360000-6FFFF 1B0000-B7FFF
SA55 110111 64/32 370000-7FFFF 1B8000-BFFFF
SA56 111000 64/32 380000-8FFFF 1C0000-C7FFF
SA57 111001 64/32 390000-9FFFF 1C8000-CFFFF
SA58 111010 64/32 3A0000-AFFFF 1D0000-D7FFF
SA59 111011 64/32 3B0000-BFFFF 1D8000-DFFFF
SA60 111100 64/32 3C0000-CFFFF 1E0000-E7FFF
SA61 111101 64/32 3D0000-DFFFF 1E8000-EFFFF
SA62 111110 64/32 3E0000-EFFFF 1F0000-F7FFF
SA63 111111 64/32 3F0000-FFFFF 1F8000-FFFFF
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MX29LV320M H/L
MX29LV320M H/L Sector Group Protection Address Table
Sector Group A20-A12
SA0 000000
SA1 000001
SA2 000010
SA3 000011
SA4-SA7 0001xx
SA8-SA11 0010xx
SA12-SA15 0011xx
SA16-SA19 0100xx
SA20-SA23 0101xx
SA24-SA27 0110xx
SA28-SA31 0111xx
SA32-SA35 1000xx
SA36-SA39 1001xx
SA40-SA43 1010xx
SA44-SA47 1011xx
SA48-SA51 1100xx
SA52-SA55 1101xx
SA56-SA59 1110xx
SA60 111100
SA61 111101
SA62 111110
SA63 111111
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MX29LV320M H/L
Q8~Q15
Operation CE# OE# WE# RE- WP# ACC Address Q0~Q7 Word Byte
SET# Mode Mode
Read L L H H X X AIN DOUT DOUT Q8-Q14=
High Z
Q15=A-1
Write (Program/Erase) L H L H (Note 3) X AIN ( N ote 4) (Note 4 Q8-Q14=
High Z
Q15=A-1
Accelerated Program L H L H (Note 3) VHH AIN (N ote 4) (Note 4) Q8-Q14=
High Z
Q15=A-1
Standby VCC±X X VCC±X H X High-Z High-Z High-Z
0.3V 0.3V
Output Disable L H H H X X X High-Z High-Z High-Z
Reset X X X L X X X High-Z High-Z High-Z
Sector Group Protect L H L VID H X Sector Addresses, (Note 4) X X
(Note 2) A6=L,A3=L, A2=L,
A1=H,A0=L
Chip unprotect L H L VID H X Sector Addresses, (Note 4) X X
(Note 2) A6=H, A3=L, A2=L,
A1=H, A0=L
Temporary Sector X X X VID HX A
IN (Note 4) (Note 4) High-Z
Group Unprotect
Legend:
L=Logic LO W=VIL, H=Logic High=VIH, VID=12.0±0.5V, VHH=12.0±0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN,
DOUT=Data OUT
Notes:
1. Address are A20:A0 in wo rd mo de; A20:A-1 in b yte mo de. Secto r addresses are A20:A15 in bo th mo des.
2 . The secto r gro up protect and chip unprotect functions may also be implemented via pro gramming equipment. See
the "Secto r Group Protection and Chip Unpro tect" section.
3. If WP#=VIL, the first sectors remain protected. If WP#=VIH, the highest or lowest sector protection depends on
whether they were last protected o r unpro tect using the metho d described in "Sector/ Sector Blo ck Pro tectio n and
Unprotect".
4. DIN or DOUT as required by co mmand sequence, Data# po lling o r secto r protect algo rithm (see Figure 15).
Table 1. BUS OPERATION (1)
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MX29LV320M H/L
Table 2. AUTOSELECT CODES (High Voltage Method)
A20 A14 A8 A5 A3 Q8 to Q15
Description CE# OE# WE# to to A9 to A6 to to A1 A0 Word Byte Q7 t o Q 0
A15 A10 A7 A4 A2 Mode Mode
Manufacturer ID L L H X X VID X L X L L L 00 X C2h
Cycle 1 L L H 22 X 7Eh
Cycle 2 L L H X X VID X L X H H L 2 2 X 1D h
Cycle 3 H H H 22 X 00h
Sector Group 01h (protected),
Protection L L H SA X VID X L X L H L X X
Verification 00h (unprotected)
Secured Silicon 98h
Sector Indicator (factor y locked),
Bit (Q7), WP# L L H X X VID X L X L H H X X
protects highest 18h
address sector (not factory locked)
Secured Silicon 88h
Sector Indicator (factor y locked),
Bit (Q7), WP# L L H X X VID X L X L H H X X
protects lowest 08h
address sector (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.
29LV320MH/L
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MX29LV320M H/L
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates arra y data to the o utput pins . WE# should re-
main at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
micro processor read cycles that assert valid address o n
the device address inputs produce valid data on the de-
vice data outputs . The device remains enab led f or read
access until the command register contents are altered.
PAGE MODE READ
The MX29LV320M H/L offers "fast page mode read" func-
tion. This mode provides faster read access speed for
random locations within a page. The page size of the
device is 4 words/8 bytes. The appropriate page is se-
lected by the higher address bits A0~A1(W ord Mode)/A-
1~A1(Byte Mo de) This is an asynchro no us operation; the
microprocessor supplies the specific word location.
The system perfo rmance could be enhanced by initiating
1 normal read and 3 fast page read (f or word mo de A0-
A1) or 7 fast page read (for byte mode A-1~A1). When
CE# is deasserted and reasserted f or a subsequent ac-
cess, the access time is tACC or tCE. Fast page mode
accesses are obtained by keeping the "read-page ad-
dresses" constant and changing the "intra-read page"
addresses.
WRITING COMMANDS/COMMAND SE-
QUENCES
To program data to the device or erase secto rs of memory ,
the system must drive WE# and CE# to VIL, and OE# to
VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table indicates the address
space that each sector occupies. A "sector address"
co nsists of the address bits required to uniquely select a
sector. The "Writing specific address and data commands
o r sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences. Writing incorrect address and data values o r
writing them in the improper sequence resets the device
to reading array data. Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the Automatic Select command
sequence, the device enters the Automatic Select mode.
The system can then read Automatic Select codes from
the internal register (which is separate from the memory
array) on Q7-Q0. Standard read cycle timings apply in
this mode. Refer to the Automatic Select Mode and Au-
tomatic Select Command Sequence section for more
information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
WRITE BUFFER
Write Buffer Programming allows the system to write a
maximum of 16 words/32 bytes in one programming op-
eratio n. This results in faster eff ective pro gramming time
than the standard programming algorithms. See "Write
Buffer" for more information.
ACCELERATED PROGRAM OPERATION
The device offers accelerated program operations through
the ACC function. This is one of two functions provided
by the ACC pin. This function is primarily intended to
allow faster manufacturing thro ughput at the facto ry.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors, and
uses the higher voltage on the pin to reduce the time
required for pro g r am operations . The system would use
a two-cycle program command sequence as required by
the Unlo ck Bypass mo de . Remo ving VHH fro m the A CC
pin must not be at VHH for operations other than accel-
erated programming, or device damage may result.
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MX29LV320M H/L
STANDBY MODE
When using bo th pins o f CE# and RESET#, the de vice
enter CMOS Standby with bo th pins held at VCC ± 0.3V.
If CE# and RESET# are held at VIH, but not within the
range o f VCC ± 0.3V, the device will still be in the standby
mo de, but the standby current will be larger . During Auto
Algorithm operation, VCC active current (ICC2) is required
even CE# = "H" until the operation is completed. The
device can be read with standard access time (tCE) from
either of these standby modes, before it is ready to read
data.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device en-
ergy co nsumption. The device auto matically enables this
mode when address remain stab le f or tACC+30ns . The
auto matic sleep mo de is independent o f the CE#, WE#,
and OE# control signals. Standard address access tim-
ings pro vide new data when addresses are changed. While
in sleep mode, output data is latched and always avail-
able to the system. ICC4 in the DC Characteristics table
represents the automatic sleep mode current specifica-
tion.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output
fro m the devices are disabled. This will cause the output
pins to be in a high impedance state.
RESET# OPERATION
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin
is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The
device also resets the internal state machine to reading
arra y data. The operatio n that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at VSS±0.3V, the device draw s
CMOS standby current (ICC4). If RESET# is held at VIL
but not within VSS±0.3V, the standby current will be
greater.
The RESET# pin may be tied to system reset circuitry.
A system reset wo uld that also reset the Flash memo ry,
enabling the system to read the boot-up firmware from
the Flash memo ry.
If RESET# is asserted during a program or erase
o peratio n, the R Y/BY# pin remains a "0" (busy) until the
internal reset operation is complete, which requires a time
o f tREADY (during Embedded Algorithms). The system
can thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is completed within a time of
tREAD Y (no t during Embedded Algorithms). The system
can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 3 for the timing diagram.
SECTOR GROUP PROTECT OPERATION
The MX29LV320M H/L features hardw are sector group
protection. This feature will disable both program and
erase operations for these sector group protected. In
this device, a sector group consists of four adjacent sec-
tors which are protected or unprotected at the same time.
To activate this mo de, the pro gramming equipment must
f orce VID on address pin A9 and control pin OE#, (sug-
gest VID = 12V) A6 = VIL and CE# = VIL. (see Table 2)
Programming of the protection circuitry begins on the
falling edge of the WE# pulse and is terminated on the
rising edge. Please refer to sector group protect algo-
rithm and waveform.
MX29LV320M H/L also pro vides another method. Which
requires VID on the RESET# only. This method can be
implemented either in-system or via programming equip-
ment. This method uses standard microprocessor bus
cycle timing.
To verify pro gramming o f the protection circuitry , the pro-
gramming equipment must fo rce VID o n address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=1, it will produce a logical "1" code at device output
Q0 fo r a pro tected secto r . Otherwise the device will pro-
duce 00H for the unprotected sector. In this mode, the
addresses, except for A1, are don't care. Address loca-
tions with A1 = VIL are reser ved to read manu facturer
and device codes. (Read Silicon ID)
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MX29LV320M H/L
It is also possible to determine if the group is protected
in the system by writing a Read Silicon ID command.
P erfo rming a read o peration with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
CHIP UNPROTECT OPERATION
The MX29LV320M H/L also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code. It is recommended to protect all sectors before
activating chip unprotect mode.
To activate this mo de, the programming equipment must
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH. (see Table 2) Refer to chip unprotect algorithm and
wavefo rm fo r the chip unprotect algo rithm. The unprotect
mechanism begins o n the falling edge o f the WE# pulse
and is terminated on the rising edge.
MX29LV320M H/L also pro vides another method. Which
requires VID on the RESET# only. This method can be
implemented either in-system or via programming equip-
ment. This method uses standard microprocessor bus
cycle timing.
It is also possible to determine if the chip is unprotect in
the system by writing the Read Silicon ID command.
P erfo rming a read o peration with A1=VIH, it will produce
00H at data o utputs (Q0-Q7) for an unprotect sector . It is
noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
WRITE PROTECT (WP#)
The write protect function provides a hardware method
to pro tect secto r witho ut using VID.
If the system asserts VIL on the WP# pin, the device
disables program and erase functions in the first
(MX29LV320MH) or last (MX29LV320ML) sector inde-
pendently of whether those sectors were protected or
unprotect using the method described in Sector/Sector
Gro up Protection and Chip Unprotect".
If the system asserts VIH on the WP# pin, the device
reverts to whether the first (MX29LV320MH) or last
(MX29LV320ML) secto r were last set to be protected o r
unprotect. That is, sector protection or unprotection for
these two sectors depends on whether they were last
protected or unprotect using the method described in
"Secto r/Sector Group Protection and Chip Unprotect".
No te that the WP# pin must no t be left floating o r unco n-
nected; inconsistent behavior of the device may result.
TEMPORARY SECTOR GROUP UNPROTECT
OPERATION
This feature allows temporary unprotect of previously
pro tected secto r to change data in-system. The Tempo-
rary Sector Unprotect mode is activated by setting the
RESET# pin to VID(11.5V -12.5V). During this mode, for-
merly protected sectors can be programmed or erased
as unprotect sector. Once VID is remove from the RE-
SET# pin, all the previously protected sectors are pro-
tected again.
SILICON ID READ OPERATION
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage. How e ver , m ultiplexing high v o ltage onto
address lines is not generally desired system design prac-
tice.
MX29LV320M H/L pro vides hardware metho d to access
the silico n ID read operation. Which metho d requires VID
on A9 pin, VIL on CE#, OE#, A6, and A1 pins. Which
apply VIL on A0 pin, the device will o utput MXIC's manu-
facture code of which apply VIH on A0 pin, the device will
o utput MX29LV320M H/L device co de.
VERIFY SECTOR GROUP PROTECT STATUS
OPERATION
MX29LV320M H/L pro vides hardware metho d fo r secto r
group protect status verify. Which method requires VID
on A9 pin, VIH on WE# and A1 pins, VIL on CE#, OE#,
A6, and A0 pins, and secto r address on A16 to A21 pins.
Which the identified sector is protected, the device will
o utput 01H. Which the identified sector is no t pro tect, the
de vice will o utput 00H.
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MX29LV320M H/L
DATA PROTECTION
The MX29LV320M H/L is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically re-
sets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences. The device also
inco rporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down tran-
sition or system noise.
SECURED SILICON SECTOR
The MX29LV320M H/L features a OTP memory region
where the system may access through a command se-
quence to create a permanent part identification as so
called Electronic Serial Number (ESN) in the device.
Once this region is programmed, any further modifica-
tio n on the regio n is impossible. The secured silicon sec-
tor is a 128 words in length, and uses a Secured Silicon
Sector Indicator Bit (Q7) to indicate whether or not the
Secured Silicon Sector is locked when shipped from the
factory. This bit is permanently set at the factory and
cannot be changed, which prevent duplication of a fac-
tory locked part. This ensures the security of the ESN
once the product is shipped to the field.
The MX29LV320M H/L offers the device with Secured
Silicon Sector either factory locked or customer lock-
able. The facto ry-locked versio n is always pro tected when
shipped from the factory , and has the Secured Silicon
Sector Indicator Bit permanently set to a "1". The cus-
tomer-lockable version is shipped with the Secured Sili-
con Sector unprotected, allowing customers to utilize that
sector in any form they prefer. The customer-lockable
version has the secured sector Indicator Bit permanently
set to a "0". Theref ore, the Secured Silico n Sector Indi-
cator Bit pre vents customer , lo c kable de vice from being
used to replace devices that are factory locked.
The system access the Secured Silicon Sector through
a command sequence (refer to "Enter Secured Silicon/
Exit Secured Silico n Secto r co mmand Sequence). After
the system has written the Enter Secured Silicon Secto r
command sequence, it may read the Secured Silicon
Sector by using the address normally occupied by the
first secto r SA0. Once entry the Secured Silico n Secto r
the o peration o f boot sectors is disabled but the o peratio n
of main sectors is as normally. This mode of operation
continues until the system issues the Exit Secured Sili-
con Sector command sequence, or until power is remo ved
from the device. On power-up, or following a hardware
reset, the de vice re v erts to sending co mmand to secto r
SA0.
Secured Silicon ESN factory Customer
Sector address locked lockable
range
000000h-000007h ESN Determined by
000008h-00007Fh Unavailable Customer
FACTORY LOCKED:Secured Silicon Sector
Programmed and Protected At the Factory
In device with an ESN, the Secured Silicon Sector is
protected when the device is shipped from the factor y.
The Secured Silicon Sector cannot be modified in any
wa y . A facto ry lock ed device has an 8-wo rd rando m ESN
at address 000000h-000007h.
CUSTOMER LOCKABLE:Secured Silicon
Sector NOT Programmed or Protected At the
Factory
As an alternative to the factory-locked version, the device
may be ordered such that the customer may program
and protect the 128-word Secured Silicon Sector.
Programming and protecting the Secured Silicon Sector
must be used with caution since, once protected, there
is no procedure available for unprotected the Secured
Silicon Sector area and none of the bits in the Secured
Silicon Sector memory space can be modified in any
way.
The Secured Silicon Sector area can be protected using
one of the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 15, except
that RESET# may be at either VIH o r VID. This allows in-
system protection of the Secured Silicon Sector without
raising any device pin to a high voltage. Note that method
is o nly applicab le to the Secured Silico n Secto r.
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MX29LV320M H/L
Write the three-cycle Enter Secured Silicon Sector Region
co mmand sequence, and then alternate method of sector
pro tection described in the :Secto r Group Protection and
Unprotect" section.
Once the Secured Silicon Sector is programmed, locked
and verified, the system must write the Exit Secured
Silicon Sector Region command sequence to return to
reading and writing the remainder of the arra y .
LOW VCC WRITE INHIBIT
When VCC is less than VLKO the device does not ac-
cept any write cycles. This protects data during VCC
pow er-up and pow er-down. The co mmand register and
all internal program/erase circuits are disabled, and the
de vice resets. Subsequent writes are igno red until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional write
when VCC is greater than VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns (typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH o r WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
POWER-UP SEQUENCE
The MX29LV320M H/L powers up in the Read o nly mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
POWER-UP WRITE INHIBIT
If WE#=CE#=VIL and OE#=VIH during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to the read mode on power-up.
POWER SUPPLY DE COUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND .
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MX29LV320M H/L
TABLE 3. MX29LV320M H/L COMMAND DEFINITIONS
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Command Bus Cycle Cycle Cycle Cycle Cycle Cycle
Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA R D
Reset (Note 6) 1 XXX F0
Automatic Select (Note 7)
Manufacturer ID Word 4 555 AA 2AA 55 555 90 X00 C2H
Byte 4 AAA AA 555 55 AAA 90 X00 C2H
Device ID Word 4 555 AA 2AA 55 555 90 X01 ID1 X0E ID2 X0 F ID3
(Note 8) Byte 4 AAA AA 555 55 AAA 90 X02 ID1 X1C ID2 X1E ID3
Secured Sector Fact- Word 4 555 AA 2AA 55 555 90 X03 see
ory Protect (Note 9) Byte 4 AAA AA 555 55 AAA 90 X06 Note 9
Sector Group Protect Word 4 555 AA 2AA 55 555 90 (SA)X02 XX00/
Verify (Note 10) Byte 4 AAA AA 555 55 AAA 90 (SA)X04 XX01
Enter Secured Silicon Word 3 555 AA 2AA 55 555 88
Sector Byte 3 AAA AA 555 55 AAA 88
Exit Secured Silicon Word 4 555 AA 2AA 55 555 9 0 XXX 00
Sector Byte 4 AAA AA 555 55 AAA 90 XXX 00
Program Word 4 555 AA 2AA 55 555 A0 PA PD
Byte 4 AAA AA 555 55 AAA A0 PA PD
Write to Buffer (Note 11) Word 6 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD
Byte 6 AAA AA 555 55 SA 25 SA BC PA PD WBL PD
Program Buffer to Flash Word 1 SA 29
Byte 1 SA 29
Write to Buffer Abort Word 3 555 AA 2AA 55 555 F0
Reset (Note 12) Byte 3 AAA AA 5 5 5 5 5 AAA F0
Chip Erase Word 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Sector Erase Word 6 5 55 AA 2AA 5 5 55 5 8 0 5 5 5 AA 2AA 5 5 SA 3 0
Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30
Program/Erase Suspend (Note 13) 1 XXX B0
Program/Erase Resume (Note 14) 1 XXX 30
CFI Query (Note 15) Word 1 55 98
Byte 1 AA 98
SOFTWARE COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mo de . Table 3 defines the v alid register co mmand
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Either of the two
reset command sequences will reset the device (when
applicable).
All addresses are latched on the f alling edge of WE# or
CE#, whichever happens later. All data are latched on
rising edge o f WE# or CE#, whichev er happens first.
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MX29LV320M H/L
Notes:
1. See Table 1 f or descriptio ns of bus o peratio ns.
2. All values are in hexadecimal.
3. Except when reading arra y o r auto matic select data, all bus cycles are write o peratio n.
4. Address bits are do n't care f or unloc k and co mmand cycles , e xcept when PA o r SA is required.
5. No unlo ck o r command cycles required when device is in read mo de.
6. The Reset co mmand is required to return to the read mo de when the device is in the auto matic select mo de or if
Q5 goes high.
7. The f ourth cycle of the auto matic select command sequence is a read cycle.
8. The de vice ID must be read in three cycles. The data is 01h f or to p bo ot and 00h f o r botto m bo o t.
9. If WP# protects the highest address sectors, the data is 98h for factory locked and 18h for not factory locked. If
WP# pro tects the lo west address sectors, the data is 88h f or f actory lo c k ed and 08h f or no t f actor loc k ed.
10 . The data is 00h f o r an unpro tected secto r/secto r b lo c k and 01h fo r a pro tected secto r/sector blo c k.
1 1. The to tal number of cycles in the co mmand sequence is determined by the number o f w o rds written to the write
buff er . The maximum number o f cycles in the co mmand sequence is 21(W o rd Mode) / 37(Byte Mode).
1 2. Co mmand sequence resets device fo r next command after aborted write-to-buffer operatio n.
13. The system may read and program functions in non-erasing secto rs, o r enter the automatic select mo de, when in
the erase Suspend mo de. The Erase Suspend co mmand is valid o nly during a secto r erase o peration.
14 . The Erase Resume co mmand is valid o nly during the Erase Suspend mo de.
15 . Co mmand is v alid when de vice is ready to read arra y data or when de vice is in auto matic select mode.
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address o f the memo ry lo catio n to be pro grammed.
Addresses are latched o n the f alling edge o f the WE# o r
CE# pulse, whichever happen later .
DDI=Data of device identifier
C2H for manufacture code
PD=Data to be programmed at location PA. Data is
latched o n the rising edge o f WE# or CE# pulse .
SA=Address of the sector to be erase or verified (in
autoselect mode).
Address bits A21-A12 uniquely select any sector.
WBL=Write Buffer Location. Address must be within the
same write buff er page as PA.
WC=Word Count. Number of write buffer locations to load
minus 1.
BC=Byte Count. Number of write buffer locations to load
minus 1.
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MX29LV320M H/L
READING ARRAY DATA
The device is automatically set to reading array data
after device power-up. No commands are required to re-
trieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. Af-
ter completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See Erase Suspend/Erase
Resume Commands for more information on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if Q5 goes high, or
while in the automatic select mode. See the "Reset Com-
mand" section, next.
RESET COMMAND
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don't care for
this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, howev er, the de vice igno res
reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase Sus-
pend mode). Once programming begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the se-
quence cycles in an SILICON ID READ command se-
quence. Once in the SILICON ID READ mode, the reset
command must be written to return to reading array data
(also applies to SILICON ID READ during Erase Sus-
pend).
If Q5 goes high during a program or erase operation,
writing the reset command returns the device to reading
array data (also applies during Erase Suspend).
SILICON ID READ COMMAND SEQUENCE
The SILICON ID READ command sequence allows the
host system to access the manufacturer and devices
codes, and determine whether or not a sector is pro-
tected. Table 2 shows the address and data requirements.
This method is an alternative to that shown in Table 1,
which is intended for PROM programmers and requires
VID on address bit A9.
The SILICON ID READ command sequence is initiated
by writing two unlock cycles, followed by the SILICON
ID READ command. The device then enters the SILI-
CON ID READ mode, and the system may read at any
address any number of times, without initiating another
command sequence. A read cycle at address XX00h
retrieves the manufacturer code. A read cycle at address
XX01h returns the device code. A read cycle containing
a sector address (SA) and the address 02h returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Table fo r valid secto r addresses.
The system must write the reset command to exit the
automatic select mode and return to reading array data.
BYTE/WORD PROGRAM COMMAND SE-
QUENCE
The command sequence requires four bus cycles, and
is initiated by writing two unlock write cycles, followed
b y the pro gram set-up co mmand. The pro gram address
and data are written next, which in turn initiate the Em-
bedded Program algorithm. The system is not required
to provide fur ther controls or timings. The device auto-
matically generates the program pulses and verifies the
programmed cell margin. Table 3 shows the address and
data requirements for the byte program command se-
quence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status o f the pro gr am o peratio n by using Q7, Q6, o r R Y/
BY#. See "Write Operation Status" for information on
these status bits.
Any commands written to the device during the Embed-
ded Program Algorithm are ignored. Note that a hard-
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MX29LV320M H/L
ware reset immediately terminates the programming o p-
eration. The Byte/Word Program command sequence
should be reinitiated once the device has reset to read-
ing arra y data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the op-
eration and set Q5 to "1", or cause the Data# Polling
algorithm to indicate the operation was successful. How-
ever, a succeeding read will show that the data is still
"0". Only erase operations can convert a "0" to a "1".
Write Buffer Programming
Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming op-
eratio n. This results in faster effective pro gramming time
than the standard programming algorithms. The Write
Buffer Programming command sequence is initiated by
first writing two unlo c k cycles. This is f o llow ed by a third
write cycle containing the Write Buffer Load command
written at the Sector Address in which programming will
occur. The fourth cycle writes the sector address and
the number of word locations, minus one, to be pro-
grammed. For example, if the system will program 6
unique address locations, then 05h should be written to
the device. This tells the device how many write buffer
addresses will be loaded with data and therefore when to
expect the Program Buffer to Flash command. The num-
ber of locations to program cannot exceed the size of
the write buff er or the operation will abort.
The fifth cycle writes the first address location and data
to be pro grammed. The write-buff er-page is selected by
address bits AMAX-4. All subsequent address/data pairs
must f all within the selected-write-buffer-page. The sys-
tem then writes the remaining address/data pairs into
the write buffer. Write b uffer locations may be loaded in
any o rder.
The write-buffer-page address must be the same for all
address/data pairs loaded into the write buffer. (This
means Write Buff er Progr amming canno t be perfo rmed
acro ss multiple write-buffer pages. This also means that
Write Buffer Programming cannot be performed across
multiple sectors. If the system attempts to load program-
ming data outside of the selected write-buffer page, the
operation will abort.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operatio n. The ho st sys-
tem must therefore account for loading a write-buffer lo-
catio n more than once. The counter decrements for each
data load operation, not for each unique write-buffer-ad-
dress location. Note also that if an address location is
loaded more than o nce into the buffer, the final data loaded
for that address will be programmed.
Once the specified number of write buffer locations have
been loaded, the system must then write the Program
Buffer to Flash command at the sector address. Any
other address and data combination aborts the Write
Buffer Programming operation. The device then begins
programming. Data polling should be used while monitor-
ing the last address lo catio n lo aded into the write buffer.
Q7, Q6, Q5, and Q1 should be monitored to determine
the de vice status during Write Buffer Pro g ramming.
The write-buffer programming operation can be suspended
using the standard program suspend/resume commands.
Upon successful co mpletion of the Write Buffer Pro gram-
ming operation, the device is ready to execute the next
command.
The Write Buffer Pro gramming Sequence can be aborted
in the following ways:
•Load a value that is greater than the page buffer size
during the Number of Locations to Program step.
•Write to an address in a sector different than the one
specified during the Write-Buffer-Lo ad co mmand.
•Write an Address/Data pair to a different write-buffer-
page than the one selected by the Starting Address
during the write buffer data loading stage of the op-
eration.
•Write data other than the Confirm Command after the
specified number of data load cycles.
The abo rt condition is indicated by Q1 = 1, Q7 = DATA#
(for the last address location loaded), Q6 = toggle, and
Q5=0. A Write-to-Buffer-Abort Reset command sequence
must be written to reset the device for the next opera-
tion. Note that the full 3-cycle Write-to-Buffer-Abort Re-
set command sequence is required when using Wr ite-
Buffer-Programming features in Unlock Bypass mode.
Program Suspend/Program Resume Command
Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Wr ite to Buffer
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MX29LV320M H/L
programming o peration so that data can be read from any
non-suspended sector. When the Program Suspend co m-
mand is written during a pro g ramming process, the de-
vice halts the progr am operation within 15us maximum
(5 us typical) and updates the status bits. Addresses are
not required when writing the Program Suspend com-
mand.
After the programming operation has been suspended,
the system can read array data from any non-suspended
sector. The Program Suspend command may also be
issued during a programming operation while an erase is
suspended. In this case, data may be read from any
addresses not in Erase Suspend or Program Suspend. If
a read is needed from the Secured Silicon Sector area
(One-time Program area), then user must use the proper
co mmand sequences to enter and e xit this regio n.
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes
as required. When the device exits the auto select mode,
the device reverts to the Program Suspend mode, and
is ready for another valid operation. See Autoselect Com-
mand Sequence for more information.
After the Program Resume command is written, the de-
vice reverts to programming. The system can determine
the status of the program operation using the Q7 or Q6
status bits, just as in the standard program operation.
See Write Operation Status f o r more informatio n.
SETUP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two
"unloc k" write cycles. These are f ollow ed b y writing the
"set-up" co mmand 80H. Two mo re "unlock" write cycles
are then followed by the chip erase command 10H, or
the sector erase command 30H.
The MX29LV320M H/L contains a Silicon-ID-Read op-
eration to supplement traditional PROM programming
methodo logy . The o peration is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code. A read
cycle with A1=VIL, A0=VIH returns the device code .
AUTOMATIC CHIP/SECTOR ERASE COM-
MAND
The device does not require the system to preprogram
prio r to erase. The A uto matic Er ase algo rithm auto mati-
cally pre-program and verifies the entire memory for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations. Table 3 shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Automatic
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates
the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading
arra y data, to ensure data integrity.
The system can determine the status of the erase op-
eratio n by using Q7, Q6, Q2, o r RY/BY#. See "Write Op-
eratio n Status" fo r info rmation on these status bits. When
the Automatic Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 10 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to Figure 9 for tim-
ing diagrams.
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MX29LV320M H/L
SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system is not required to provide any
control or timing during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector erase
is a six-bus cycle operation. There are two "unlo ck" write
cycles. These are followed by writing the set-up com-
mand 80H. Two mo re "unlo c k" write cycles are then f o l-
lowed by the sector erase command 30H. The sector
address is latched on the falling edge of WE# or CE#,
whichever happens later , while the command (data) is
latched on the rising edge of WE# or CE#, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE# or
CE#, whichever happens later . Each successive secto r
load cycle started by the falling edge of WE# or CE#,
whichever happens later must begin within 50us from
the rising edge of the preceding WE# or CE#, whiche ver
happens first. Otherwise, the loading period ends and
internal auto sector erase cycle starts. (Monitor Q3 to
determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.
ERASE SUSPEND
This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Secto r Erase operatio n. When the Erase Suspend com-
mand is issued during the sector erase operation, the
device requires a maximum 20us to suspend the sector
erase operation. However, When the Erase Suspend co m-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation. After this command has
been executed, the command register will initiate erase
suspend mode. The state machine will retur n to read
mo de auto matically after suspend is ready . At this time,
state machine only allows the command register to re-
spond to the Erase Resume, program data to, or read
data from any sector not selected for erasure.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended blocks.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing.
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MX29LV320M H/L
Table 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description Address h Address h Data h
(x16) (x8)
Query-unique ASCII string "QRY" 1 0 20 0051
11 22 0052
12 24 0059
Primary vendor command set and control interface ID code 1 3 2 6 0002
14 28 0000
Address for primary algorithm extended query table 1 5 2A 0040
16 2C 0000
Alternate vendor command set and control interface ID code (none) 1 7 2E 0000
18 30 0000
Address for secondary algorithm extended query table (none) 19 3 2 0000
1A 34 0000
Table 4-2. CFI Mode: System Interface Data Values
Description Address h Address h Data h
(x16) (x8)
VCC supply, minimum (2.7V) 1B 3 6 0027
VCC supply, maximum (3.6V) 1 C 3 8 0036
VPP supply, minimum (none) 1 D 3A 0000
VPP supply, maximum (none) 1E 3C 0000
Typical timeout for single word/byte write (2N us) 1F 3E 0007
Typical timeout for maximum size buffer write (2N us) 2 0 4 0 0007
Typical timeout for individual block erase (2N ms) 2 1 42 000A
Typical timeout for full chip erase (2N ms) 2 2 4 4 0000
Maximum timeout for single word/byte write times (2N X Typ) 23 46 0001
Maximum timeout for maximum size buffer write times (2N X Typ) 24 48 0005
Maximum timeout for individual block erase times (2N X Typ) 25 4A 0004
Maximum timeout for full chip erase times (not supported) 2 6 4 C 0000
QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX29L V320M H/L is capable of o perating in the CFI mode.
This mode all the host system to determine the manu-
facturer of the device such as operating parameters and
co nfiguration. T wo commands are required in CFI mode.
Query command of CFI mode is placed first, then the
Reset co mmand exits CFI mo de. These are described in
Table 4.
The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Standby mo de, and Read ID mo de; howe ver, it is ignored
otherwise.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, or read ID mode.
The command is valid only when the device is in the CFI
mode.
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MX29LV320M H/L
Description Address h Address h Data h
(x16) (x8)
Device size (2n bytes) 27 4E 0016
Flash device interface code 2 8 5 0 0002
29 52 0000
Maximum number of bytes in multi-byte write = 2n2A 54 0005
2B 56 0000
Number of erase block regions (01h=uniform device; 02h=boot device) 2C 58 0001
Erase block region 1 information 2 D 5A 003F
[2E,2D] = # of blocks in region -1 2E 5C 0000
[30, 2F] = size in multiples of 256-bytes 2F 5E 0000
30 60 0001
31 62 0000
Erase Block Region 2 Information (refer to CFI publication 100) 3 2 6 4 0000
33 66 0000
34 68 0000
35 6A 0000
Erase Block Region 3 Information (refer to CFI publication 100) 3 6 6 C 0000
37 6E 0000
38 70 0000
39 72 0000
Erase Block Region 4 Information (refer to CFI publication 100) 3A 7 4 0000
3B 76 0000
3C 78 0000
Table 4-3. CFI Mode: Device Geometry Data Values
23
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MX29LV320M H/L
Description Address h Address h Data h
(x16) (x8)
Query-unique ASCII string "PRI" 4 0 8 0 0050
41 82 0052
42 84 0049
Major version number, ASCII 4 3 8 6 0031
Minor version number, ASCII 4 4 8 8 0033
Address sensitive unlock (0=required, 1= not required) 4 5 8A 0000
Erase suspend (2= to read and write) 4 6 8 C 0002
Sector protect (N= # of sectors/group) 4 7 8E 0001
Temporary sector unprotect (1=supported) 48 90 0001
Sector protect/unprotect scheme 49 92 0004
Simultaneous R/W operation (0=not supported) 4A 94 0000
Burst mode type (0=not supported) 4B 96 0000
Page mode type (1=4 word page) 4 C 98 0001
ACC (Acceleration) Supply Minimum 4Dh 9A 00B5
00h=Not Supported, D7-D4: Volt, D3-D0:100mV
ACC (Acceleration) Supply Maximum 4Eh 9 C 00C5
00h=Not Supported, D7-D4: Volt, D3-D0:100mV
Top/Bottom Boot Sector Flag 4 F h 9 E 0004/
02h=Bottom Boot Device, 03h=Top Boot Device 0005
04h=uniform sectors bottom WP# protect,
05h=uniform sectors top WP# protect
Program Suspend 50h A0 0001
00h=Not Supported, 01h=Supported
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
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MX29LV320M H/L
Table 5. Write Operation Status
WRITE OPERATION STATUS
The device provides several bits to determine the status
of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY#.
Table 5 and the fo llowing subsectio ns describe the func-
tions of these bits. Q7, RY/BY#, and Q6 each offer a
method for determining whether a program or erase op-
eration is complete or in progress. These three bits are
discussed first.
Status Q7 Q6 Q5 Q3 Q2 Q1 RY/BY#
Byte/Word Program in Auto Program Algorithm Q7# To ggle 0 N/A No 0 0
Toggle
Auto Erase Algorithm 0 To ggle 0 1 Toggle N/A 0
Erase Suspend Read 1 N o 0 N/A To ggle N/A 1
Erase (Erase Suspended Sector) Toggle
Suspended Erase Suspend Read Data Data Data Data Data Data 1
Mode (Non-Erase Suspended Sector)
Erase Suspend Program Q7# To ggle 0 N/A N/A N/A 0
Program-Suspended Read Invalid (not allowed) 1
Program (Program-Suspended Sector)
Suspend Program-Suspended Read Data 1
(Non-Program-Suspended Sector)
Write-to-Buffer Busy Q7# Toggle 0 N/A N/A 0 0
Abort Q7# Toggle 0 N/A N/A 1 0
Notes:
1. Q5 s witches to "1" when an W o rd/Byte Program, Erase, or Write-to-Buffer operatio n has e xceeded the maximum
timing limits. Refer to the section on Q5 for more information.
2. Q7 and Q2 require a valid address when reading status inf ormation. Refer to the appro priate subsection fo r further
details.
3. The Data# Polling algorithm sho uld be used to mo nitor the last lo aded write-buff er address lo cation.
4. Q1 s witches to "1" when the de vice has aborted the write-to-buff er operatio n.
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MX29LV320M H/L
Q7: Data# P olling
The Data# Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend. Data#
P olling is valid after the rising edge of the final WE# pulse
in the program or erase command sequence.
During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to pro g ramming dur-
ing Erase Suspend. When the Auto matic Pro gram algo-
rithm is complete, the device outputs the datum pro-
gr ammed to Q7. The system must provide the pro g ram
address to read valid status information on Q7. If a pro-
gram address falls within a protected secto r, Data# Poll-
ing on Q7 is active for approximately 1 us, then the de-
vice returns to reading array data.
During the Auto matic Erase algorithm, Data# Polling pro-
duces a "0" o n Q7. When the Auto matic Erase algorithm
is complete, or if the device enters the Erase Suspend
mo de, Data# Polling produces a "1" on Q7. This is analo-
gous to the complement/true datum output described for
the Automatic Program algorithm: the erase function
changes all the bits in a sector to "1" prior to this, the
device outputs the "complement," or "0". The system
must provide an address within any of the sectors se-
lected for erasure to read valid status info rmation o n Q7.
After an erase command sequence is written, if all sec-
to rs selected f o r erasing are pro tected, Data# P olling o n
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output Enable
(OE#) is asserted low.
Q6:Toggle BIT I
To ggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge o f the final WE# or CE#, whichev er
happens first pulse in the command sequence (prior to
the program or erase operation), and during the sector
time-out.
During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
co ntro l the read cycles. When the operatio n is co mplete,
Q6 stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles for
100us and returns to reading array data. If not all se-
lected sectors are protected, the Automatic Erase algo-
rithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Auto-
matic Erase algo rithm is in progress), Q6 toggling. When
the device enters the Erase Suspend mode, Q6 stops
toggling. Ho wev er, the system must also use Q2 to de-
termine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program com-
mand sequence is written, then returns to reading array
data.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.
Table 5 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "To ggle Bit II" on Q2, when used with Q6, indicates
whether a par ticular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge o f the final WE# o r CE#, whiche ver
happens first pulse in the command sequence.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
26
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus , both status bits
are required for sectors and mode information. Refer to
Table 5 to co mpare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is to ggling. Typically , the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
co mpleted the program o r erase operatio n. The system
can read array data on Q7-Q0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase opera-
tion. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previo us paragraph. Alternatively ,
it may choose to perform other system tasks. In this
case, the system must start at the beginning of the al-
gorithm when it returns to determine the status of the
operation.
Q5:Program/Erase Timing
Q5 will indicate if the program or erase time has exceeded
the specified limits (internal pulse count). Under these
co nditio ns Q5 will pro duce a "1". This time-o ut conditio n
indicates that the program or erase cycle was not suc-
cessfully completed. Data# Polling and Toggle Bit are
the only operating functions of the device under this con-
dition.
If this time-out condition occurs during secto r er ase op-
eration, it specifies that a particular sector is bad and it
may not be reused. However , other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program o r erase command sequence. This
allows the system to continue to use the other active
sectors in the device.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.
If this time-out condition occurs during the byte/word pro-
gramming operation, it specifies that the entire sector
containing that byte is bad and this sector may not be
reused, (other sectors are still functional and can be re-
used).
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Au-
tomatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops toggling.
Once the Device has exceeded timing limits, the Q5 bit
will indicate a "1". Please note that this is not a device
failure condition since the device was incorrectly used.
The Q5 failure condition may appear if the system tries
to program a to a "1" location that is previously pro-
grammed to "0". Only an erase operation can change a
"0" back to a "1". Under this condition, the device halts
the operation, and when the operation has exceeded the
timing limits, Q5 produces a "1".
Q3:Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is co mplete. Data# P olling
and T o ggle Bit are valid after the initial sector erase com-
mand sequence.
If Data# Polling or the Toggle Bit indicates the device
has been written with a valid erase command, Q3 may
be used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data# Po lling or
27
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Toggle Bit. If Q3 is low ("0"), the device will accept addi-
tional secto r er ase co mmands. To insure the co mmand
has been accepted, the system software should check
the status of Q3 prior to and following each subsequent
sector erase command. If Q3 were high on the second
status check, the command may not have been accepted.
If the time between additional erase commands from the
system can be less than 50us, the system need not to
monitor Q3.
Q1: Write-to-Buffer Abort
Q1 indicates whether a Write-to-Buffer operation was
abo rted. Under these conditions Q1 pro duces a "1". The
system must issue the Write-to-Buffer-Abort-Reset co m-
mand sequence to return the device to reading array data.
See Write Buff er sectio n f o r mo re details.
RY/BY#:READY/BUSY OUTPUT
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress
or complete. The RY/BY# status is valid after the rising
edge o f the final WE# pulse in the co mmand sequence.
Since RY/BY# is an open-drain output, se v eral RY/BY#
pins can be tied together in parallel with a pull-up resistor
to VCC .
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device
is ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.
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MX29LV320M H/L
ABSOLUTE MAXIMUM RATINGS
Storage T emperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient T emperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Vo ltage with Respect to Gro und
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-
mum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may over-
shoot to VCC +2.0 V for periods up to 20ns.
2. Minimum DC input voltage on pins A9, OE#, and
RESET# is -0.5 V. During vo ltage transitions, A9, OE#,
and RESET# may overshoot VSS to -2.0 V for peri-
ods of up to 20 ns. Maximum DC input voltage on pin
A9 is +12.5 V which ma y o v ersho o t to 14.0 V f o r peri-
ods up to 20 ns.
3. No more than one output may be sho rted to gro und at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
OPERATING RATINGS
Commercial (C) Devices
Ambient Temperature (TA ) . . . . . . . . . . . . . 0 °C to +70°C
Industrial (I) Devices
Ambient Temperature (TA ). . . . . . . . . . . -40 °C to +85°C
VCC Supply Voltages
VCC for full voltage range. . . . . .. . . . . . +2.7 V to 3.6 V
VCC for regulated voltage range. . . . . . . +3.0 V to 3.6 V
Operating ranges define tho se limits between which the
functio nality o f the de vice is guaranteed.
29
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Notes:
1. On the WP#/ACC pin only, the maximum input lo ad current when WP# = VIL is ± 5.0uA.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC =
3.0V.
4 . ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns.
6. Not 100% tested.
7. A9=12.5V when T A=0°C to 85°C, A9=12V when when TA=-40°C to 0°C.
DC CHARACTERISTICS TA=-40°°
°°
°C to 85°°
°°
°C, VCC=2.7V~3.6V (TA=0°°
°°
°C to 70°°
°°
°C, VCC=3.0V~3.6V
for 70R)
Para-
meter Description T est Conditions Min. Typ. Max. Unit
I LI Input Load Current (Note 1) VIN = VSS to VCC , ±1.0 uA
VCC = VCC max
I LIT A9 Input Leakage Current VCC=VCC max; A9 = 12.5V 3 5 uA
I LO Output Leakage Current VOUT = VSS to VCC , ±1.0 uA
VCC= VCC max
ICC1 VCC Initial Read Current CE#= VIL, 10 MHz 3 5 5 0 mA
(No tes 2,3) OE# = VIH 5 MHz 1 8 2 5 mA
1 MHz 5 2 0 mA
ICC2 VCC Intra-Page Read CE#= VIL , 10 MHz 5 2 0 mA
Current (Notes 2,3) OE# = VIH 40 MHz 10 40 mA
ICC3 VCC Active Write Current CE#= VIL , OE# = VIH 50 60 mA
(Notes 2,4,6) WE#=VIL
ICC4 VCC Standby Current CE#,RESET#=VCC±0.3V 20 50 uA
(Note 2) WP#=VIH
ICC5 VCC Reset Current RESET#=VSS±0.3V 20 50 uA
(Note 2) WP#=VIH
ICC6 Automatic Sleep Mo de VIL = V SS ± 0.3 V, 20 50 u A
(No tes 2,5) VIH = VCC ± 0.3 V,
WP#=VIH
VIL Input Low V oltage -0.5 0.8 V
VIH Input High V oltage 0.7xVCC VCC+0.5 V
VH H Voltage f or ACC Program VCC = 2.7V ~ 3.6V 11.5 12.0 12.5 V
Acceleration
VID V oltage for A utoselect and VCC = 3.0 V ± 10% 11.5 12.0 12.5 V
Temporary Secto r Unprotect
V OL Output Low V o ltage IOL= 4.0mA,VCC=VCC min 0.45 V
V OH1 Output High V oltage IOH=-2.0mA,VCC=VCC min 0.85VCC V
V OH2 IOH=-100uA,VCC=VCC min VCC-0.4 V
VLKO Low VCC Lock-Out Voltage 2.3 2.5 V
(Note 4)
30
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MX29LV320M H/L
SWITCHING TEST CIRCUITS
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Do n't Care, Any Change P ermitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State(High Z)
KEY TO SWITCHING WAVEFORMS
SWITCHING TEST WAVEFORMS
TEST SPECIFICATIONS
Test Condition All Speeds Unit
Output Load 1 TTL gate
Output Load Capacitance, CL 3 0 pF
(including jig capacitance)
Input Rise and F all Times 5 ns
Input Pulse Levels 0.0-3.0 V
Input timing measurement 1.5 V
reference levels
Output timing measurement 1.5 V
reference levels
DEVICE UNDER
TEST
DIODES=IN3064
OR EQUIVALENT
CL 6.2K ohm
2.7K ohm 3.3V
1.5V 1.5V
Measurement Level
3.0V
0.0V OUTPUT
INPUT
31
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
AC CHARACTERISTICS
Read-Only Operations TA=-40 °°
°°
°C to 85°°
°°
°C, VCC=2.7V~3.6V (TA=0°°
°°
°C to 70°°
°°
°C, VCC=3.0V~3.6V f or
70R)
Parameter Speed Options
Std. Description Test Setup 70R 90 Unit
tRC Read Cycle Time (Note 1) Min 70 9 0 ns
tACC Address to Output Delay CE#, OE#=VIL Max 7 0 9 0 ns
tCE Chip Enable to Output Delay OE#=VIL Max 7 0 9 0 ns
tPA C C P age Access Time Max 2 5 2 5 ns
tOE Output Enable to Output Delay Max 3 5 3 5 ns
tDF Chip Enab le to Output High Z (Note 1) Max 1 6 ns
tD F Output Enable to Output High Z (Note 1) Max 1 6 ns
tO H Output Ho ld Time From Address, CE# Min 0 ns
o r OE#, whiche v er Occurs First
Read Min 35 ns
tOEH Output Enable Ho ld Time To ggle and Min 10 ns
(No te 1) Data# Polling
Notes:
1. Not 100% tested.
2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE for test specifications.
32
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 1. READ TIMING WAVEFORMS
Addresses
CE#
OE#
tACC
WE#
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
0V
VIH
VIL
VOH
VOL
HIGH Z HIGH Z
D ATA V alid
tOE
tOEH tDF
tCE
tRH
tRH
tRC
Outputs
RESET#
RY/BY#
tOH
ADD V alid
Figure 2. PAGE READ TIMING WAVEFORMS
Same Page
A2-A21
(A-1), A0~A2
CE#
OE#
Output
tACC
tPACC tPACC tPACC
Qa Qb Qc Qd
33
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MX29LV320M H/L
Figure 3. RESET# TIMING WAVEFORM
AC CHARACTERISTICS
Parameter Description Test Setup All Speed OptionsUnit
tREAD Y1 RESET# PIN Low (During Automatic Algorithms) MAX 2 0 us
to Read o r Write (See No te)
tREADY2 RESET# PIN Low (NOT During Auto matic Algo rithms) MAX 5 00 ns
to Read o r Write (See No te)
tRP RESET# Pulse Width (NOT During Automatic Algorithms) MIN 5 00 ns
tRH RESET# High Time Befo re Read (See No te) MIN 5 0 ns
tRB R Y/BY# Reco very Time(to CE#, OE# go low) MI N 0 ns
tRPD RESET# Low to Standby Mode MIN 2 0 us
Note:Not 100% tested
tRH
tRB
tReady1
tRP
tRP
tReady2
RY/BY#
CE#, OE#
RESET#
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
RY/BY#
CE#, OE#
RESET#
34
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
AC CHARACTERISTICS
Erase and Program Operations TA=-40°°
°°
°C to 85°°
°°
°C, VCC=2.7V~3.6V (TA=0°°
°°
°C to 70°°
°°
°C, VCC=
3.0V~3.6V for 70R)
Parameter Speed Options
Std. Description 70R 90 Unit
tWC Write Cycle Time (Note 1) Min 7 0 90 ns
tAS Address Setup Time Min 0 ns
tASO Address Setup Time to OE# low during to ggle bit po lling Mi n 1 5 ns
tAH Address Hold Time Min 4 5 ns
tAHT Address Ho ld Time F ro m CE# or OE# high during toggle Min 0 ns
bit po lling
tDS Data Setup Time Min 3 5 ns
tDH Data Ho ld Time Min 0 ns
tCEPH CE# High During Toggle Bit Polling Min 20 ns
tOEPH Output Enable High during to ggle bit polling Min 2 0 ns
tGHWL Read Reco very Time Befo re Write Min 0 ns
(OE# High to WE# Low)
tGHEL Read Reco very Time Befo re Write Min 0 ns
tCS CE# Setup Time Min 0 ns
tCH CE# Hold Time Min 0 ns
tWP Write Pulse Width Min 3 5 ns
tWPH Write Pulse Width High Min 3 0 ns
Write Buffer Pro gram Operatio n (No tes 2,3) Typ 240 us
Single Word/Byte Program Byte Typ 60 us
tWHWH1 Operatio n (Notes 2,5) W ord Typ 60 us
Accelerated Single Wo rd/Byte Byte Typ 54 us
Programming Operation (Notes 2,5) Wo rd Typ 54 us
tWHWH2 Sector Erase Operatio n (Note 2) Typ 0.5 sec
tVCS VCC Setup Time (Note 1) Min 5 0 us
tRB Write Reco very Time fro m RY/BY# Min 0 ns
tBUSY Pro gram/Erase V alid to RY/BY# Dela y Min 7 0 9 0 ns
tVHH VHH Rise and F all Time (No te 1) Min 250 ns
tPOLL Program Valid Befo re Status Po lling (No te 6) Max 4 us
Notes:
1. No t 100% tested.
2. See the "Erase And Pro gramming P erfo rmance" section fo r mo re info rmatio n.
3. Fo r 1-16 wo rds/1-32 bytes pro grammed.
4. Effectiv e write buffer specification is based upo n a 16-word/32-byte write buffer o peratio n.
5. Wo rd/Byte programming specificatio n is based upon a single wo rd/byte programming o peration not utilizing the write
buffer.
6. When using the pro gram suspend/resume feature, if the suspend co mmand is issued within tPOLL, tPOLL must be
fully re-applied upo n resuming the programming o peration. If the suspend command is issued after tPOLL, tPOLL is
no t required again prio r to reading the status bits upon resuming.
35
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MX29LV320M H/L
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC PROGRAM TIMING WAVEFORMS
Figure 5. ACCELERATED PROGRAM TIMING DIAGRAM
ACC
tVHH
VHH
VIL or VIH VIL or VIH
tVHH
tWC
Address
OE#
CE#
A0h
XXXh PA
PD Status DOUT
PA PA
Note :
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
tAS
tAH
tCH
tWP
tDS tDH
tWHWH1
Read Status Data (last two cycle)Program Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
tVCS
WE#
Data
RY/BY#
VCC
36
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Program Data/Address
Write Data A0H Address 555H
YES
Verify Word Ok ?
YES
Auto Program Completed
Data Poll
from system
Increment
Address
Last Address ?
No
No
37
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MX29LV320M H/L
Figure 7. WRITE BUFFER PROGRAMMING ALGORITHM FLOWCHART
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
2. Q7 may change simultaneously with Q5.
Therefore, Q7 should be verified.
3. If this flowchart location was reached because Q5=
"1" then the device FAILED. If this flowchart location
was reached because Q1="1", then the Write to
Buffer operation was ABORTED. In either case, the
proper reset command must be written before the
device can begin another operation. If Q1=1, write
the Write-Buffer-Programming-Abort-Reset com-
mand. If Q5=1, write the Reset command.
4. See Table 3 for command sequences required for
write buffer programming.
Write "Write to Buffer"
command and
Sector Address
Write number of addresses
to program minus 1(WC)
and Sector Address
Part of "Write to Buffer"
Command Sequence
Write program buffer
to flash sector address
Read Q7~Q0 at Last
Loaded Address
Read Q7~Q0 with address
= Last Loaded Address
FAIL or ABORT PASS
Write first address/data
Write next address/data pair
Write to a different
sector address
Write to buffer ABORTED.
Must write "Write-to-buffer
Abort Reset" command sequence
to return to read mode.
WC = WC - 1
WC = 0 ?
Abort Write to
Buffer Operation ?
Q7 = Data ?
Q5 = 1 ?
Q1 = 1 ?
Q7 and Q15 = Data ?
Yes
Yes
Yes
Yes
Yes
Yes
(Note 2)
(Note 1)
(Note 3)
No
No
No
No
No
No
38
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MX29LV320M H/L
Figure 8. PROGRAM SUSPEND/RESUME FLOWCHART
Program Operation
or Write-to-Buffer
Sequence in Progress
Write address/data
XXXh/B0h
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and Secured Sector
read operations are also allowed
Data cannot be read from erase-or
program-suspended sectors
Write Program Resume
Command Sequence
Read data as
required
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Wait 15us
Done reading ?
No
Yes
39
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 9. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM
tWC
Address
OE#
CE#
55h
2AAh SA
30h In
Progress Complete
VA VA
Note :
1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
tAS
tAH
555h for chip erase
tCH
tWP
tDS tDH
tWHWH2
Read Status Data Erase Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
10 for Chip Erase
tVCS
WE#
Data
RY/BY#
VCC
40
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 10. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
YES
Write Data 10H Address 555H
Write Data 55H Address 2AAH
DATA = FFh ?
YES
Auto Erase Completed
Data Poll
from system
No
41
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
Write Data 30H Sector Address
Write Data 55H Address 2AAH
Auto Sector Erase Completed
Data Poll from System
YES
NO
Data=FFh?
Last Sector
to Erase ?
NO
YES
42
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 12. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
Toggle Bit checking Q6
not toggled
ERASE SUSPEND
YES
NO
Write Data 30H
Continue Erase
Reading or
Programming End
Read Array or
Program
Another
Erase Suspend ? NO
YES
YES
NO
ERASE RESUME
43
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter Speed Options
Std. Description 70R 90 Unit
tWC Write Cycle Time (No te 1) Min 7 0 9 0 ns
tAS Address Setup Time Min 0 ns
tAH Address Hold Time Min 4 5 ns
tDS Data Setup Time Min 3 5 ns
tDH Data Ho ld Time Min 0 ns
tGHEL Read Reco very Time Befo re Write Min 0 ns
(OE# High to WE# Low)
tWS WE# Setup Time Min 0 ns
tWH WE# Hold Time Min 0 ns
tCP CE# Pulse Width Min 3 5 ns
tCPH CE# Pulse Width High Min 2 5 ns
Write Buffer Pro gram Operation (Notes 2,3) Typ 240 us
Single Word/Byte Program Byte Typ 60 us
tWHWH1 Operatio n (Notes 2,5) W o rd Typ 60 us
Accelerated Single Wo rd/Byte Byte Typ 54 us
Pro gramming Operatio n (Notes 2,5) W o rd Typ 54 us
tWHWH2 Sector Erase Operatio n (Note 2) Typ 0.5 sec
tRH RESET HIGH Time Before Write (Note 1) Min 50 ns
tPOLL Program Valid Befo re Status Polling (Note 6) Max 4 us
Notes:
1. Not 100% tested.
2. See the "Erase And Pro gramming P erfo rmance" section fo r mo re info rmation.
3. Fo r 1-16 wo rds/1-32 bytes pro grammed.
4. Effective write buffer specificatio n is based upo n a 16-wo rd/32-byte write buffer operatio n.
5. Wo rd/Byte programming specificatio n is based upon a single word/byte pro gramming o peration no t utilizing the write
buffer.
6. When using the pro gram suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be
fully re-applied upon resuming the programming o peration. If the suspend command is issued after tPOLL, tPOLL is
no t required again prio r to reading the status bits upon resuming.
TA=-40°°
°°
°C to 85°°
°°
°C, VCC=2.7V~3.6V (TA=0°°
°°
°C to 70°°
°°
°C, VCC=3.0V~3.6V for 70R)
44
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 13. CE# CONTROLLED PROGRAM TIMING WAVEFORM
tWC
tWH
tGHEL
tWHWH1 or 2
tCP
Address
WE#
OE#
CE#
Data Q7
PA
Data# Polling
DOUT
RESET#
RY/BY#
NOTES:
1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2.Figure indicates the last two bus cycles of the command sequence.
tAH
tAS
PA for program
SA for sector erase
555 for chip erase
tRH
tDH
tDS
tWS
A0 for program
55 for erase
tCPH
tBUSY
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
45
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
SECTOR GROUP PROTECT/CHIP UNPROTECT
Figure 14. Sector Group Protect / Chip Unprotect Waveform (RESET# Control)
Note: For sector group protect A6=0, A1=1, A0=0. For chip unprotect A6=1, A1=1, A0=0
Sector Group Protect:150us
Chip Unprotect:15ms
1us
VID
VIH
Data
SA, A6
A1, A0
CE#
WE#
OE#
Valid* Valid*
Status
Valid*
Sector Group Protect or Chip Unprotect
40h60h60h
Verify
RESET#
46
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 15. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH
RESET#=VID
START
PLSCNT=1
RESET#=VID
Wait 1us
Set up sector address
Sector Protect:
Write 60h to sector
address with
A6=0, A1=1, A0=0
Wait 150us
Verify Sector Protect:
Write 40h to sector
address with
A6=0, A1=1, A0=0
Read from
sector address
with
A6=0, A1=1, A0=0
Reset
PLSCNT=1
Remove VID from RESET#
Write reset command
Sector Protect
Algorithm
Chip Unprotect
Algorithm
Sector Protect complete Remove VID from RESET#
Write reset command
Sector Unprotect complete
Device failed
Temporary Sector
Unprotect Mode
Increment PLSCNT
Increment PLSCNT
First Write
Cycle=60h?
Set up first sector address
Protect all sectors:
The indicated portion of
the sector protect algorithm
must be performed
for all unprotected sectors
prior to issuing the first
sector unprotect address
Sector Unprotect:
Write 60h to sector
address with
A6=1, A1=1, A0=0
Wait 15 ms
Verify Sector Unprotect:
Write 40h to sector
address with
A6=1, A1=1, A0=0
Read from
sector address
with
A6=1, A1=1, A0=0
Data=01h?
PLSCNT=25?
Device failed
START
PLSCNT=1
RESET#=VID
Wait 1us
First Write
Cycle=60h?
All sectors
protected?
Data=00h?
PLSCNT=1000?
Last sector
verified?
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
YesYes
Yes
No
No
No
No
No
No
Protect another
sector?
Reset
PLSCNT=1
Temporary Sector
Unprotect Mode
47
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 16. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE# Control)
Parameter Description Test Setup All Speed Options Unit
tVLHT Voltage transition time Min. 4 u s
tWPP1 Write pulse width for sector group protect Min. 1 00 ns
tOESP OE# setup time to WE# active Min. 4 us
AC CHARACTERISTICS
tOE
Data
OE#
WE#
12V
3V
12V
3V
CE#
A9
A1
A6
tOESP
tWPP 1
tVLHT
tVLHT
tVLHT
Verify
01H F0H
A21-A16 Sector Address
48
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 17. SECTOR GROUP PROTECTION ALGORITHM (A9, OE# Control)
START
Set Up Sector Addr
PLSCNT=1
Sector Protection
Complete
Data=01H?
Yes
.
OE#=VID, A9=VID, CE#=VIL
A6=VIL
Activate WE# Pulse
Time Out 150us
Set WE#=VIH, CE#=OE#=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
Protect Another
Sector?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=32?
Yes
No
No
49
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control)
tOE
Data
OE#
WE#
12V
3V
12V
3V
CE#
A9
A1
tOESP
tWPP 2
tVLHT
tVLHT
tVLHT
Verify
00H
A6
F0H
50
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 19. CHIP UNPROTECT FLOWCHART (A9, OE# Control)
START
Protect All Sectors
PLSCNT=1
Chip Unprotect
Complete
Data=00H?
Yes
Set OE#=A9=VID
CE#=VIL, A6=1
Activate WE# Pulse
Time Out 15ms
Set OE#=CE#=VIL
A9=VID, A1=1
Set Up First Sector Addr
All sectors have
been verified?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=1000?
No
Increment
PLSCNT
No
Read Data from Device
Yes
Yes
No
Increment
Sector Addr
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
51
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 20. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS
AC CHARACTERISTICS
Parameter Description Test All Speed Options Unit
Setup
tVI DR VID Rise and Fall Time (see Note) M in 5 0 0 ns
tRSP RESET# Setup Time for T emporary Sector Unprotect Min 4 us
tRRB RESET# Ho ld Time fro m R Y/BY# High f o r Tempor ary Min 4 us
Sector Group Unprotect
RESET#
CE#
WE#
RY/BY#
tVIDR
12V
0 or 3V VIL or VIH
tRSP
tVIDR
Program or Erase Command Sequence
tRRB
52
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 21. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART
Start
RESET# = VID (Note 1)
Perform Erase or Program Operation
RESET# = VIH
Temporary Sector Unprotect Completed(Note 2)
Operation Completed
2. All previously protected sectors are protected again.
Notes : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
53
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 22. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART
START
Enter Secured Silicon Sector
Data = 01h ?
No
Yes
Wait 1us
First Wait Cycle Data=60h
Second Wait Cycle Data=60h
A6=0, A1=1, A0=0
Wait 300us
Write Reset CommandDevice Failed
Secured Sector Protect Complete
54
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 23. SILICON ID READ TIMING WAVEFORM
tACC
tCE
tACC
tOE
tOH tOH
tDF
DATA OUT
Manufacturer ID Device ID
Cycle 1
Device ID
Cycle 2
Device ID
Cycle 3
VID
VIH
VIL
ADD
A9
ADD
CE#
A1
OE#
WE#
ADD
A0
DATA OUT DATA OUT DATA OUT
DATA
Q0-Q15
VCC 3V
VIH
VIL
VIH
VIL
VIH
VIL
A2
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tACC tACC
tOH tOH
55
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
WRITE OPERATION STATUS
Figure 24. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Note :
VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.
tDF
tCE
tCH
tOE
tOEH
tACC
tRC
tOH
Address
CE#
OE#
WE#
Q7
Q0-Q6
RY/BY#
tBUSY
Status Data Status Data
Status Data Complement True Valid Data
VAVAVA
High Z
High Z
Valid DataTrue
56
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 25. DATA# POLLING ALGORITHM
Notes:
1.VA=valid address f o r pro gramming.
2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
Read Q7~Q0
Add.=VA(1)
Read Q7~Q0
Add.=VA
Start
Q7 = Data ?
Q5 = 1 ?
Q7 = Data ?
FAIL Pass
No
No
(2)
No
Yes
Yes
Yes
57
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 26. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Note :
VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
tDF
tCE
tCH
tOE
tOEH
tACC
tRC
tOH
Address
CE#
OE#
WE#
Q6/Q2
RY/BY#
tDH
Valid Status
Valid Status
(first read)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
VA
Valid Data
58
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
START
Read Q7~Q0
Read Q7~Q0
YES
NO
Toggle Bit Q6
=Toggle?
Q5=1?
YES
NO
(Note 1)
Read Q7~Q0 Twice (Note 1,2)
Toggle Bit Q6=
Toggle?
Program/Erase Operation Not
Complete, Write Reset Command
YES
Program/Erase Operation Complete
Figure 27. TOGGLE BIT ALGORITHM
Note:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
59
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Figure 28. Q6 versus Q2
NOTES:
The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
WE#
Enter Embedded
Erasing Erase
Suspend Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase Suspend
Read Erase
Erase
Resume
Erase
Complete
Erase
Q6
Q2
60
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
MIN. MAX.
Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V
Input Voltage with respect to GND on all I/O pins -1.0V VCC + 1.0V
Current -100mA +100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
LATCH-UP CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE (1)
Notes:
1. Typical prog ram and erase times assume the f ollowing co nditions: 25°C , 3.0V VCC . Programming specificatio ns
assume checkbo ard data pattern.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and
including 100,000 program/erase cycles.
3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the
write buffer .
4 . For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer
operation.
6 . In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7 . System-level overhead is the time required to execute the command sequence(s) for the program command. See
Tables 3 for further information o n co mmand definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
Parameter Min Unit
Minimum Pattern Data Retention Time 2 0 Years
DATA RETENTION
PARAMETER Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0. 5 2 sec Excludes 00h
programming
Chip Erase Time 3 2 64 sec prior to erasure
Note 6
Total Write Buffer Program Time (Note 4) 2 40 us Excludes
Total Accelerated Effective Write Buffer 2 0 0 u s system level
Program Time (Note 4) overhead
Chip Program Time 31.5 sec Note 7
61
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
Parameter Symbol Parameter Description Te st Set TYP MAX UNIT
CIN Input Capacitance VIN=0 TSOP 6 7.5 pF
CSP 4.2 5.0 pF
COUT Output Capacitance VOUT=0 TSOP 8.5 12 pF
CSP 5.4 6.5 pF
CIN2 Control Pin Capacitance VIN=0 TSOP 7.5 9 pF
CSP 3.9 4.7 pF
TSOP PIN AND BGA PACKAGE CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. T est conditions T A=25°C , f=1.0MHz
62
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
ORDERING INFORMATION
PART NO. ACCESS TIME Ball Pitch/ PACKAGE Remark
(ns) Ball size
MX29LV320MHTC-70R 70 56 Pin TSOP
(Normal Type)
MX29LV320MHTC-90 90 56 Pin TSOP
(Normal Type)
MX29LV320MLTC-70R 70 56 Pin TSOP
(Normal Type)
MX29LV320MLTC-90 90 56 Pin TSOP
(Normal Type)
MX29LV320MHTI-90 90 56 Pin TSOP
(Normal Type)
MX29LV320MLTI-90 90 56 Pin TSOP
(Normal Type)
MX29LV320MHTC-90G 90 56 Pin TSOP PB-free
(Normal Type)
MX29LV32 0MLTC -90G 90 56 Pin TSOP PB-free
(Normal Type)
MX29LV320MHTI-90G 90 56 Pin TSOP PB-free
(Normal Type)
MX29LV320MLTI-90G 90 56 Pin TSOP PB-free
(Normal Type)
63
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
PART NAME DESCRIPTION
MX 29 LV 90M T T C G
OPTION:
G: Lead-free package
R: Restricted VCC (3.0V~3.6V)
Q: Restricted VCC (3.0V~3.6V) with Lead-free package
blank: normal
SPEED:
70: 70ns
90: 90ns
10:100ns
TEMPERATURE RANGE:
C: Commercial (0˚C to 70˚C)
I: Industrial (-40˚C to 85˚C)
PACKAGE:
M: SOP
T: TSOP
X: FBGA (CSP)
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
H: Uniform with Highest Sector H/W Protect
L: Uniform with Lowest Sector H/W Protect
U: Uniform Sector
REVISION:
M: NBit Technology
DENSITY & MODE:
033/320/321: 32Mb, Page Mode Flash Device
065/640/641: 64Mb, Page Mode Flash Device
128/129: 128Mb, Page Mode Flash Device
LV/GL: 3V standard
LA: 3V Security
TYPE:
DEVICE:
29:Flash
XB - 0.3mm Ball
XE - 0.4mm Ball
XC - 1.0mm Ball
640
64
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
PACKAGE INFORMATION
65
P/N:PM1136 REV. 1.1, AUG. 11, 2005
MX29LV320M H/L
REVISION HISTORY
Revision No. Description Page Date
1. 0 1. Removed "Advanced Information" on title P1 MAR/22/2005
1. 1 1. Added description about Pb-free device is RoHS compliant P1 AUG/11/2005
2. Added no te 7 f o r ILIT parameter in DC Characteristics table P 29
3. Added comments into performance table P6 0
4. Added Part Name Description P6 3
MX29LV320M H/L
MACRONIX INTERNATIONAL CO., LTD .
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-755-834-335-79
FAX:+86-755-834-380-78
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
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TEL:+81-6-4807-5460
FAX:+81-6-4807-5461
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TEL:+65-6346-5505
FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
