CY7C1354CV25
CY7C1356CV25
9-Mbit (256K × 36/512K × 18)
Pipelined SRAM with NoBL™ Architecture
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05537 Rev. *S Revised April 5, 2019
9-Mbit (256K × 36/512K × 1 8) Pipelined SR AM with NoB L™ Architecture
Features
■Pin-compatible with and functionally equivalent to ZBT™
■Supports 250 MHz bus operations with zero wait states
■Available speed grades are 250, 200, and 166 MHz
■Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■Fully registered (inputs and outputs) for pipelined operation
■Byte write capability
■Single 2.5 V power supply (VDD)
■Fast clock-to-output times
❐2.8 ns (for 250-MHz device)
■Clock enable (CEN) pin to suspend operation
■Synchronous self-timed writes
■Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package and 165-ball FBGA
package
■IEEE 1149.1 JTAG-compatible boundary scan
■Burst capability – linear or interleaved burst order
■“ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1354CV25/CY7C1356CV25[1] are 2.5V,
256K × 36/512K × 18 synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The
CY7C1354CV25/CY7C1356CV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1354CV25/CY7C1356CV25 are pin-compatible with and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354CV25 and BWa–BWb for
CY7C1356CV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description 250 MHz 200 MHz 166 MHz Unit
Maximum access time 2.8 3.2 3.5 ns
Maximum operating current 250 220 180 mA
Maximum CMOS standby current 40 40 40 mA
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 2 of 35
Logic Block Diagram – CY7C1354CV25
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1 WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC A0'
A1'
D1
D0 Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 3 of 35
Logic Block Diagram – CY7C1356CV25
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1 WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC A0'
A1'
D1
D0 Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
ZZ Sleep
Control
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 4 of 35
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ................................................. 9
Burst Write Accesses ................................................ 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ...............................10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................10
Truth Table ...................................................................... 11
Partial Truth Table for Read/Write ................................ 12
Partial Truth Table for Read/Write ................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ...............................17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent .........................17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Exit Order ............................................. 19
Boundary Scan Exit Order ............................................. 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC® Solutions ...................................................... 35
Cypress Developer Community ................................. 35
Technical Support ..................................................... 35
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 5 of 35
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
A
A
A
A
A1
A0
VSS
VDD
A
A
A
A
A
A
VDDQ
VSS
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
DQa
DQa
VDDQ
VSS
DQa
DQa
VSS
VDDQ
VDDQ
VSS
DQc
DQc
VSS
VDDQ
DQc
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
VSS
VDDQ
A
A
CE1
CE2
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
NC(18M)
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV/LD
ZZ
CY7C1354CV25
A
A
A
A
A1
A0
VSS
VDD
A
A
A
A
A
A
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
VDD
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
NC(18M)
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
ADV/LD
ZZ
MODE
CY7C1356CV25
BWd
MODE
BWc
DQc
DQc
DQc
DQc
DQPc
DQd
DQd
DQd
DQPb
DQb
DQa
DQa
DQa
DQa
DQPa
DQb
DQb
(256K × 36) (512K × 18)
BWb
NC
NC
NC
DQc
NC
NC(288M)
NC(144M)
NC(72M)
NC(36M)
NC(288M)
NC(144M)
NC(72M)
NC(36M)
DQPd
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 6 of 35
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout
Pin Configurations (continued)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DQa
VDDQ
NC/576M
NC/1G
DQc
DQd
DQc
DQd
AA AANC/18M VDDQ
CE2A
VDDQ
VDDQ
VDDQ
VDDQ
NC/144M
NC
A
DQc
DQc
DQd
DQd
TMS
VDD
A
NC/72M
DQPd
A
A
ADV/LD ACE
3NC
VDD AANC
VSS VSS
NC DQPb
DQb
DQb
DQa
DQb
DQb
DQa
DQa
NCTDI TDO VDDQ
TCK
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
MODE
CE1VSS
OE VSS VDDQ
BWcA
VSS
WE
VDDQ
VDD NC VDD
VSS
CLK
NC BWa
CEN VSS VDDQ
VSS
ZZ
NC/288M
A
A
A1
A0 VSS
VDD NC
CY7C1354CV25 (256K × 36)
DQPcDQb
A NC/36M
DQcDQb
DQc
DQc
DQc
DQb
DQb
DQa
DQa
DQa
DQa
DQPa
DQd
DQd
DQd
DQd
BWd
BWb
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC/36M
DQa
VDDQ
NC/576M
NC/1G
NCDQb
DQb
DQb
DQb
AA AANC/18M VDDQ
CE2A
NC
VDDQ
NC
VDDQ
VDDQ
VDDQ
NC
NC
NC/144M
NC/72M
A
DQb
DQb
DQb
DQb
NC
NC
NC
NC
TMS
VDD
A
A
DQPb
A
A
ADV/LD ACE3NC
VDD AANC
VSS VSS
NC NCDQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
NCTDI TDO VDDQ
TCK
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
CE1VSS NC
OE VSS VDDQ
BWbAV
SS NC
VSS
WE NC
VDDQ
VDD NC VDD
NCVSS
CLK
NC NC
BWa
CEN VSS NC VDDQ
VSS NC
ZZ
NC/288M
A
A
A
A1
A0 VSS NC
VDD NC
CY7C1356CV25 (512K × 18)
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 7 of 35
Figure 3. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
Pin Configurations (continued)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
DQPc
DQc
DQPd
NC
DQd
ACE1BWb CE3
BWcCEN
CE2
DQc
DQd
DQd
MODE
NC
DQc
DQc
DQd
DQd
DQd
NC/36M
NC/72M
VDDQ
BWdBWaCLK WE
VSS VSS VSS VSS
VDDQ VSS
VDD VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD VSS
VDD VSS VSS
VDDQ VDD
VSS
VDD
VSS
VDD VSS VSS
VSS
VDD
VDD VSS
VDD VSS VSS
NC
TCKA0
VSS
TDI
A
A
DQcVSS
DQcVSS
DQc
DQc
NC
VSS
VSS
VSS
VSS
NC
VSS
A1
DQd
DQd
NC/144M
NC
VDDQ
VSS
TMS
891011
NC/288M
AAADV/LD NC
OE NC/18M ANC
VSS VDDQ NC DQPb
VDDQ
VDD DQb
DQb
DQb
NC
DQb
NC
DQa
DQa
VDD VDDQ
VDD VDDQ DQb
VDD
NC
VDD
DQa
VDD VDDQ DQa
VDDQ
VDD
VDD VDDQ
VDD VDDQ DQa
VDDQ
AA
VSS
A
A
A
DQb
DQb
DQb
ZZ
DQa
DQa
DQPa
DQa
A
VDDQ
A
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
NC
NC
DQPb
NC
DQb
ACE1CE3
BWbCEN
CE2
NC
DQb
DQb
MODE
NC
DQb
DQb
NC
NC
NC
NC/36M
NC/72M
VDDQ
BWaCLK WE
VSS VSS VSS VSS
VDDQ VSS
VDD VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD VSS
VDD VSS VSS
VDDQ VDD
VSS
VDD
VSS
VDD VSS VSS
VSS
VDD
VDD VSS
VDD VSS VSS
NC
TCKA0
VSS
TDI
A
A
DQbVSS
NC VSS
DQb
NC
NC
VSS
VSS
VSS
VSS
NC
VSS
A1
DQb
NC
NC/144M
NC
VDDQ
VSS
TMS
891011
NC/288M
AA
ADV/LD A
OE NC/18M ANC
VSS VDDQ NC DQPa
VDDQ
VDD NC
DQa
DQa
NC
NC
NC
DQa
NC
VDD VDDQ
VDD VDDQ DQa
VDD
NC
VDD
NCVDD VDDQ DQa
VDDQ
VDD
VDD VDDQ
VDD VDDQ NC
VDDQ
AA
VSS
A
A
A
DQa
NC
NC
ZZ
DQa
NC
NC
DQa
A
VDDQ
A
CY7C1356CV25 (512K × 18)
CY7C1354CV25 (256K × 36)
A
A
NC
NC
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 8 of 35
Pin Definitions
Pin Name I/O Type Pin Description
A0, A1, A Input-
synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
BWa, BWb,
BWc, BWd
Input-
synchronous
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE Input-
synchronous
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
ADV/LD Input-
synchronous
Advance/load input used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
CLK Input-
clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1Input-
synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device.
CE2Input-
synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select/deselect the device.
CE3Input-
synchronous
Chip enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
OE Input-
asynchronous
Output enable, active LOW. Combined with the synchronous logic block inside the device to control
the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN Input-
synchronous
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
DQSI/O-
synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
addresses during the previous clock rise of the read cycle. The direction of the pins is controlled by OE
and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPXI/O-
synchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ[a:d]. During write
sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE will default HIGH, to an interleaved burst order.
TDO JTAG serial
output
synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
TDI JTAG serial
input
synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
TMS Test mode
select
synchronous
This pin controls the test access port state machine. Sampled on the rising edge of TCK.
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 9 of 35
Functional Overview
The CY7C1354CV25/CY7C1356CV25 are
synchronous-pipelined burst NoBL SRAMs designed specifically
to eliminate wait states during write/read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 2.8 ns
(250-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[d:a] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.8 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will tri-state following the next clock rise.
Burst Read Accesses
The CY7C1354CV25/CY7C1356CV25 have an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in Single Read Accesses.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst mode,
a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will wrap
around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal burst counter regardless of the state
of chip enables inputs or WE. WE is latched at the beginning of
a burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to A0–A16 is loaded into
the address register. The write signals are latched into the
control logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b for
TCK JTAG-clock Clock input to the JTAG circuitry.
VDD Power supply Power supply inputs to the core of the device.
VDDQ I/O power
supply
Power supply for the I/O circuitry.
VSS Ground Ground for the device. Should be connected to ground of the system.
NC – No connects. This pin is not connected to the die.
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M 288M,
576M, and 1G densities.
ZZ Input-
asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Pin Definitions (continued)
Pin Name I/O Type Pin Description
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 10 of 35
CY7C1356CV25). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b for
CY7C1356CV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into the
device and the Write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1354CV25 and BWa,b for CY7C1356CV25)
signals. The CY7C1354CV25/CY7C1356CV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE) with the selected
byte write select (BW
) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1354CV25/CY7C1356CV25 are common I/O
devices, data should not be driven into the device while the
outputs are active. The output enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b for
CY7C1356CV25) inputs. Doing so will tri-state the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1354CV25 and DQa,b/DQPa,b for CY7C1356CV25) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1354CV25/CY7C1356CV25 has an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load the
initial address, as described in Single Write Accesses on page 9.
When ADV/LD is driven HIGH on the subsequent clock rise, the
chip enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. The correct BW (BWa,b,c,d
for CY7C1354CV25 and BWa,b for CY7C1356CV25) inputs must
be driven in each cycle of the burst write in order to write the
correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
IDDZZ Sleep mode standby current ZZ VDD 0.2 V – 50 mA
tZZS Device operation to ZZ ZZ VDD 0.2 V – 2tCYC ns
tZZREC ZZ recovery time ZZ 0.2 V 2tCYC –ns
tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns
tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 11 of 35
Truth Table
The truth table for CY7C1354CV25/CY7C1356CV25 follows. [2, 3, 4, 5, 6, 7, 8]
Operation Address used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect cycle None H L L X X X L L–H Tri-state
Continue deselect cycle None X L H X X X L L–H Tri-state
Read cycle (begin burst) External L L L H X L L L–H Data out (Q)
Read cycle (continue burst) Next X L H X X L L L–H Data out (Q)
NOP/dummy read (begin burst) External L L L H X H L L–H Tri-state
Dummy read (continue burst) Next X L H X X H L L–H Tri-state
Write cycle (begin burst) External L L L L L X L L–H Data in (D)
Write cycle (continue burst) Next X L H X L X L L–H Data in (D)
NOP/write abort (begin burst) None L L L L H X L L–H Tri-state
Write abort (continue burst) Next X L H X H X L L–H Tri-state
Ignore clock edge (stall) Current X L X X X X H L–H –
Sleep mode None XH X XXXX X Tri-state
Notes
2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = Valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE and BWX. See Write Cycle Description table for details.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is
inactive or when the device is deselected, and DQs = data when OE is active.
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 12 of 35
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1354CV25 follows. [9, 10, 11, 12]
Function (CY7C1354CV25) WE BWdBWcBWbBWa
Read H X X X X
Write– no bytes written L H H H H
Write byte a–(DQa and DQPa)LHHHL
Write byte b – (DQb and DQPb)LHHLH
Write bytes b, a L H H L L
Write byte c –(DQc and DQPc)LHLHH
Write bytes c, a L H L H L
Write bytes c, b L H L L H
Write bytes c, b, a L H L L L
Write byte d –(DQd and DQPd)LLHHH
Write bytes d, a L L H H L
Write bytes d, b L L H L H
Write bytes d, b, a L L H L L
Write bytes d, c L L L H H
Write bytes d, c, a L L L H L
Write bytes d, c, b L L L L H
Write all bytes LLLLL
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1356CV25 follows. [9, 10, 11, 12]
Function (CY7C1356CV25) WE BWbBWa
Read H x x
Write – no bytes written L H H
Write byte a (DQa and DQPa)LHL
Write byte b – (DQb and DQPb)LLH
Write both bytes L L L
Notes
9. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
10. Write is defined by WE and BWX. See Write Cycle Description table for details.
11. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
12. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 13 of 35
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354CV25/CY7C1356CV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package only.
The TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5 V I/O logic levels.
The CY7C1354CV25/CY7C1356CV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used.
The ball is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction.
It is also loaded with the IDCODE instruction if the controller is
placed in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Exit Order on page 19 and Boundary Scan
Exit Order on page 20 show the order in which the bits are
connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 18.
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 14 of 35
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK# captured in the boundary
scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 15 of 35
TAP Controller State Diagram
The TAP Controller State Diagram follows. [13]
Note
13. The 0/1 next to each state represents the value of TMS at the rising edge of the TCK.
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 16 of 35
TAP Controller Block Diagram
TAP Timing
Bypass Register
0
Instruction Register
012
Identification Register
012293031 ...
Boundary Scan Register
012..x ...
Selection
Circuitry
Selection
Circuitry
TCK
TMS TAP CONTROLLER
TDI TDO
tTL
Test Clock
(TCK)
123456
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE UNDEFINED
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 17 of 35
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .................. ........1.25 V
2.5 V TAP AC Output Load Equivalent
TAP AC Switching Characteristics
Over the Operating Range
Parameter [14, 15] Description Min Max Unit
Clock
tTCYC TCK clock cycle time 50 –ns
tTF TCK clock frequency –20 MHz
tTH TCK clock HIGH time 20 –ns
tTL TCK clock LOW time 20 –ns
Output Times
tTDOV TCK clock LOW to TDO valid –10 ns
tTDOX TCK clock LOW to TDO invalid 0 – ns
Set-up Times
tTMSS TMS set-up to TCK clock rise 5 – ns
tTDIS TDI set-up to TCK clock rise 5 – ns
tCS Capture set-up to TCK rise 5 – ns
Hold Times
tTMSH TMS hold after TCK clock rise 5 – ns
tTDIH TDI hold after clock rise 5 – ns
tCH Capture hold after clock rise 5 – ns
TDO
1.25V
20pF
Z = 50Ω
O
50Ω
Notes
14. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
15. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 18 of 35
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [16] Description Test Conditions Min Max Unit
VOH1 Output HIGH voltage IOH = –1.0 mA, VDDQ = 2.5 V 2.0 – V
VOH2 Output HIGH voltage IOH = –100 µA, VDDQ = 2.5 V 2.1 – V
VOL1 Output LOW voltage IOL = 8.0 mA, VDDQ = 2.5 V – 0.4 V
VOL2 Output LOW voltage IOL = 100 µA VDDQ = 2.5 V – 0.2 V
VIH Input HIGH voltage VDDQ = 2.5 V 1.7 VDD + 0.3 V
VIL Input LOW voltage VDDQ = 2.5 V –0.3 0.7 V
IXInput Load current GND < VIN < VDDQ –5 5 µA
Identification Register Definitions
Instruction Field CY7C1354CV25 CY7C1356CV25 Description
Revision number (31:29) 000 000 Reserved for version number.
Cypress device ID (28:12) 01011001000100110 01011001000010110 Reserved for future use.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.
ID register presence (0) 1 1 Indicate the presence of an ID register.
Scan Register Sizes
Register Name Bit Size (× 36) Bit Size (× 18)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary scan order (119-ball BGA package) 69 69
Boundary scan order (165-ball FBGA package) 69 69
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input/output ring contents. Places the boundary scan register between the TDI
and TDO. Forces all SRAM outputs to high Z state.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the input/output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input/output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Note
16. All voltages referenced to VSS (GND).
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 19 of 35
Boundary Scan Exit Order
(256K × 36)
Bit # 119-ball ID 165-ball ID
1K4 B6
2H4 B7
3M4 A7
4F4 B8
5B4 A8
6G4 A9
7C3 B10
8B3 A10
9D6 C11
10 H7 E10
11 G6 F10
12 E6 G10
13 D7 D10
14 E7 D11
15 F6 E11
16 G7 F11
17 H6 G11
18 T7 H11
19 K7 J10
20 L6 K10
21 N6 L10
22 P7 M10
23 N7 J11
24 M6 K11
25 L7 L11
26 K6 M11
27 P6 N11
28 T4 R11
29 A3 R10
30 C5 P10
31 B5 R9
32 A5 P9
33 C6 R8
34 A6 P8
35 P4 R6
36 N4 P6
37 R6 R4
38 T5 P4
39 T3 R3
40 R2 P3
41 R3 R1
42 P2 N1
43 P1 L2
44 L2 K2
45 K1 J2
46 N2 M2
47 N1 M1
48 M2 L1
49 L1 K1
50 K2 J1
51 Not Bonded (Preset to 1) Not Bonded (Preset to 1)
52 H1 G2
53 G2 F2
54 E2 E2
55 D1 D2
56 H2 G1
57 G1 F1
58 F2 E1
59 E1 D1
60 D2 C1
61 C2 B2
62 A2 A2
63 E4 A3
64 B2 B3
65 L3 B4
66 G3 A4
67 G5 A5
68 L5 B5
69 B6 A6
Boundary Scan Exit Order (continued)
(256K × 36)
Bit # 119-ball ID 165-ball ID
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 20 of 35
Boundary Scan Exit Order
(512K × 18)
Bit # 119-ball ID 165-ball ID
1K4 B6
2H4 B7
3M4 A7
4F4 B8
5B4 A8
6G4 A9
7C3 B10
8B3 A10
9T2 A11
10 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
11 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
12 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
13 D6 C11
14 E7 D11
15 F6 E11
16 G7 F11
17 H6 G11
18 T7 H11
19 K7 J10
20 L6 K10
21 N6 L10
22 P7 M10
23 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
24 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
25 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
26 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
27 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
28 T6 R11
29 A3 R10
30 C5 P10
31 B5 R9
32 A5 P9
33 C6 R8
34 A6 P8
35 P4 R6
36 N4 P6
37 R6 R4
38 T5 P4
39 T3 R3
40 R2 P3
41 R3 R1
42 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
43 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
44 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
45 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
46 P2 N1
47 N1 M1
48 M2 L1
49 L1 K1
50 K2 J1
51 Not Bonded (Preset to 1) Not Bonded (Preset to 1)
52 H1 G2
53 G2 F2
54 E2 E2
55 D1 D2
56 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
57 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
58 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
59 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
60 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
61 C2 B2
62 A2 A2
63 E4 A3
64 B2 B3
65 Not Bonded (Preset to 0) Not Bonded (Preset to 0)
66 G3 Not Bonded (Preset to 0)
67 Not Bonded (Preset to 0) A4
68 L5 B5
69 B6 A6
69 B6 A6
69 B6 A6
68 L5 B5
69 B6 A6
66 G3 Not Bonded (Preset to 0)
67 Not Bonded (Preset to 0) A4
68 L5 B5
69 B6 A6
Boundary Scan Exit Order (continued)
(512K × 18)
Bit # 119-ball ID 165-ball ID
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Document Number: 38-05537 Rev. *S Page 21 of 35
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +3.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Operating Range
Range Ambient Temperature VDD/VDDQ
Commercial 0 °C to +70 °C 2.5 V ± 5%
Industrial –40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter [17, 18] Description Test Conditions Min Max Unit
VDD Power supply voltage 2.375 2.625 V
VDDQ I/O supply voltage for 2.5 V I/O 2.375 VDD V
VOH Output HIGH voltage for 2.5 V I/O, IOH = 1.0 mA 2.0 – V
VOL Output LOW voltage for 2.5 V I/O, IOL= 1.0 mA – 0.4 V
VIH Input HIGH voltage for 2.5 V I/O 1.7 VDD + 0.3 V V
VIL Input LOW voltage [17] for 2.5 V I/O –0.3 0.7 V
IXInput leakage current except ZZ
and MODE
GND VI VDDQ –5 5 A
Input current of MODE Input = VSS –30 – A
Input = VDD –5A
Input current of ZZ Input = VSS –5 – A
Input = VDD –30A
IOZ Output leakage current GND VI VDDQ, output disabled –5 5 A
IDD VDD operating supply VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
–250mA
5-ns cycle,
200 MHz
–220mA
6-ns cycle,
166 MHz
–180mA
ISB1 Automatic CE power-down
current — TTL inputs
Max VDD, device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
–130mA
5-ns cycle,
200 MHz
–120mA
6-ns cycle,
166 MHz
–110mA
ISB2 Automatic CE power-down
current — CMOS inputs
Max VDD, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V,
f = 0
All speed
grades
–40mA
Notes
17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
18. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ VDD.
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Document Number: 38-05537 Rev. *S Page 22 of 35
ISB3 Automatic CE power-down
current — CMOS inputs
Max VDD, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
–120mA
5-ns cycle,
200 MHz
–110mA
6-ns cycle,
166 MHz
–100mA
ISB4 Automatic CE power-down
current — TTL inputs
Max VDD, device deselected,
VIN VIH or VIN VIL, f = 0
All speed
grades
–40mA
Electrical Characteristics (continued)
Over the Operating Range
Parameter [17, 18] Description Test Conditions Min Max Unit
Capacitance
Parameter [19] Description Test Conditions 100-pin TQFP
Max
119-ball BGA
Max
165-ball FBGA
Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz,
VDD = 2.5 V, VDDQ = 2.5 V
555pF
CCLK Clock input capacitance 5 5 5 pF
CI/O Input/output capacitance 5 7 7 pF
Thermal Resistance
Parameter [19] Description Test Conditions 100-pin TQFP
Package
119-ball BGA
Package
165-ball FBGA
Package Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
29.41 34.1 16.8 °C/W
JC Thermal resistance
(junction to case)
6.13 14 3.0 °C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
OUTPUT
R = 1667
R = 1538
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
VT = 1.25 V
2.5 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
2.5 V I/O Test Load
Note
19. Tested initially and after any design or process change that may affect these parameters.
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Document Number: 38-05537 Rev. *S Page 23 of 35
Switching Characteristics
Over the Operating Range
Parameter [20, 21] Description -250 -200 -166 Unit
Min Max Min Max Min Max
tPower[22] VCC(typical) to the first access read or
write
1–1–1–ms
Clock
tCYC Clock cycle time 4.0–5–6–ns
FMAX Maximum operating frequency – 250 – 200 – 166 MHz
tCH Clock HIGH 1.8 – 2.0 – 2.4 – ns
tCL Clock LOW 1.8 – 2.0 – 2.4 – ns
Output Times
tCO Data output valid after CLK rise – 2.8 – 3.2 – 3.5 ns
tEOV OE LOW to output valid – 2.8 – 3.2 – 3.5 ns
tDOH Data output hold after CLK rise 1.25 – 1.5 – 1.5 – ns
tCHZ Clock to high Z [23, 24, 25] 1.25 2.8 1.5 3.2 1.5 3.5 ns
tCLZ Clock to low Z [23, 24, 25] 1.25 – 1.5 – 1.5 – ns
tEOHZ OE HIGH to output high Z [23, 24, 25] – 2.8 – 3.2 – 3.5 ns
tEOLZ OE LOW to output low Z [23, 24, 25] 0–0–0–ns
Set-up Times
tAS Address set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
tDS Data input set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
tCENS CEN set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
tWES WE, BWx set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
tALS ADV/LD set-up before CLK rise 1.4 – 1.5 – 1.5 – ns
tCES Chip select set-up 1.4 – 1.5 – 1.5 – ns
Hold Times
tAH Address hold after CLK rise 0.4 – 0.5 – 0.5 – ns
tDH Data input hold after CLK rise 0.4 – 0.5 – 0.5 – ns
tCENH CEN hold after CLK rise 0.4 – 0.5 – 0.5 – ns
tWEH WE, BWx hold after CLK rise 0.4 – 0.5 – 0.5 – ns
tALH ADV/LD hold after CLK rise 0.4 – 0.5 – 0.5 – ns
tCEH Chip select hold after CLK rise 0.4 – 0.5 – 0.5 – ns
Notes
20. Timing reference level is when VDDQ = 2.5 V.
21. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted.
22. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated.
23. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 4 on page 22. Transition is measured ± 200 mV from steady-state voltage.
24. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
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Document Number: 38-05537 Rev. *S Page 24 of 35
Switching Waveforms
Figure 5. Read/Write Timing [26, 27, 28]
WRITE
D(A1)
123456789
CLK
tCYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BWX
ADV/LD
t
AH
t
AS
ADDRESS A1 A2 A3 A4 A5 A6 A7
t
DH
t
DS
Data
In-Out (DQ)
t
CLZ
D(A1) D(A2) D(A5)Q(A4)Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2) BURST
WRITE
D(A2+1)
READ
Q(A3) READ
Q(A4) BURST
READ
Q(A4+1)
WRITE
D(A5) READ
Q(A6) WRITE
D(A7) DESELECT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE UNDEFINED
Q(A6)
Q(A4+1)
Notes
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
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Document Number: 38-05537 Rev. *S Page 25 of 35
Figure 6. NOP, STALL and DESELECT CYCLES [29, 30, 31]
Switching Waveforms (continued)
READ
Q(A3)
45678910
CLK
CE
WE
CEN
BWX
ADV/LD
ADDRESS A3 A4 A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4) STALLWRITE
D(A1)
123
READ
Q(A2) STALL NOP READ
Q(A5) DESELECT CONTINUE
DESELECT
DON’T CARE UNDEFINED
t
CHZ
A2
D(A1) Q(A2) Q(A3)
Notes
29. For this waveform ZZ is tied LOW.
30. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
31. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
CY7C1354CV25
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Document Number: 38-05537 Rev. *S Page 26 of 35
Figure 7. ZZ Mode Timing [32, 33]
Switching Waveforms (continued)
tZZ
ISUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q) High-Z
DESELECT or READ Only
Notes
32. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
33. I/Os are in high Z when exiting ZZ sleep mode.
CY7C1354CV25
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Document Number: 38-05537 Rev. *S Page 27 of 35
Ordering Code Definitions
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz) Ordering Code
Package
Diagram Part and Package Type Operating
Range
166 CY7C1354CV25-166AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial
CY7C1354CV25-166BZC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
200 CY7C1354CV25-200AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial
Temperature Range: C = Commercial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 166 MHz or 200 MHz
V25 = 2.5 V
Process Technology 90 nm
135X = 1354 or 1356
1354 = PL, 256Kb × 36 (9Mb)
1356 = PL, 512Kb × 18 (9Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
C 135X C - XXX XV25 CCY 7XX
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 28 of 35
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85050
ș
ș1
ș2
NOTE:
3. JEDEC SPECIFICATION NO. REF: MS-026.
2. BODY LENGTH DIMENSION DOES NOT
MOLD PROTRUSION/END FLASH SHALL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
BODY SIZE INCLUDING MOLD MISMATCH.
L11.00 REF
L
c
0.45 0.60 0.75
0.20
NOM.MIN.
D1
R2
E1
E
0°
0.08
D
2
A
A
1
A
1.35 1.40
SYMBOL MAX.
7°
0.20
1.45
1.60
0.15
ș
b0.22 0.30 0.38
e0.65 TYP
DIMENSIONS
1
R0.08
L20.25 BSC
0.05
0.20
INCLUDE MOLD PROTRUSION/END FLASH.
15.80 16.00 16.20
13.90 14.00 14.10 NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
21.80 22.00 22.20
19.90 20.00 20.10
L30.20
0°ș1
11° 13°ș212°
51-85050 *G
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 29 of 35
Figure 9. 119-ball PBGA (14 × 22 × 2.4 mm) Package Outline, 51-85115
Package Diagrams (continued)
51-85115 *D
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 30 of 35
Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm (0.5 Ball Diameter)) Package Outline, 51-85180
Package Diagrams (continued)
51-85180 *G
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 31 of 35
Acronyms Document Conventions
Units of Measure
Acronym Description
BGA Ball Grid Array
CE Chip Enable
CEN Clock Enable
CMOS Complementary Metal Oxide Semiconductor
EIA Electronic Industries Alliance
FBGA Fine-Pitch Ball Grid Array
I/O Input/Output
JEDEC Joint Electron Devices Engineering Council
JTAG Joint Test Action Group
LSB Least Significant Bit
MSB Most Significant Bit
NoBL No Bus Latency
OE Output Enable
SRAM Static Random Access Memory
TAP Test Access Port
TCK Test Clock
TDI Test Data-In
TDO Test Data-Out
TMS Test mode select
TQFP Thin Quad Flat Pack
TTL Transistor-Transistor Logic
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
mm millimeter
ms millisecond
mV millivolt
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 32 of 35
Document History Page
Document Title: CY7C1354CV25/CY7C1356CV25, 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05537
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 242032 RKF 07/13/2004 New data sheet.
*A 278969 RKF 10/18/2004 Updated Boundary Scan Exit Order (To match the B Rev of these devices).
Updated Boundary Scan Exit Order (To match the B Rev of these devices).
*B 284929 RKF / VBL 11/01/2004 Updated Functional Overview:
Updated ZZ Mode Electrical Characteristics:
Changed maximum value of IDDZZ parameter from 35 mA to 50 mA.
Added Electrical Characteristics.
Updated Ordering Information:
Updated part numbers.
*C 323636 PCI 02/22/2005 Removed “225 MHz” Frequency Range related information in all instances
across the document.
Added “250 MHz” Frequency Range related information in all instances across
the document.
Updated Pin Definitions:
Modified address expansion as per JEDEC Standard in all instances across
the document.
Updated Thermal Resistance:
Changed value of JA parameter corresponding to 100-pin TQFP Package
from 25 °C/W to 29.41 °C/W.
Changed value of JC parameter corresponding to 100-pin TQFP Package
from 9 °C/W to 6.13 °C/W.
Changed value of JA parameter corresponding to 119-ball BGA Package from
25 °C/W to 34.1 °C/W.
Changed value of JC parameter corresponding to 119-ball BGA Package from
6 °C/W to 14.0 °C/W.
Changed value of JA parameter corresponding to 165-ball FBGA Package
from 27 °C/W to 16.8 °C/W.
Changed value of JC parameter corresponding to 165-ball FBGA Package
from 6 °C/W to 3.0 °C/W.
Updated Switching Characteristics:
Changed minimum value of tCYC parameter from 4.4 ns to 4.0 ns corresponding
to 250 MHz frequency.
Updated Ordering Information:
No change in part numbers.
Removed comment “Lead-free BGX package will be available in 2005.” below
the table.
*D 332879 PCI 03/13/2005 Updated Selection Guide:
Unshaded 200 MHz and 166 MHz speed bins related information.
Updated Pin Definitions:
Added Address Expansion pins.
Updated IEEE 1149.1 Serial Boundary Scan (JTAG):
Updated TAP Instruction Set:
Removed “EXTEST OUTPUT BUS TRI-STATE”.
Updated Electrical Characteristics:
Unshaded 200 MHz and 166 MHz speed bins related information.
Updated details in “Test Conditions” column corresponding to VOL and VOH
parameters.
Updated Switching Characteristics:
Unshaded 200 MHz and 166 MHz speed bins related information.
Updated Ordering Information:
Updated part numbers.
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 33 of 35
*E 357258 PCI 05/05/2005 Changed status from Preliminary to Final.
Updated Selection Guide:
Unshaded 250 MHz speed bin related information.
Updated Electrical Characteristics:
Changed maximum value of ISB2 parameter from 35 mA to 40 mA.
Unshaded 250 MHz speed bin related information.
Updated Switching Characteristics:
Unshaded 250 MHz speed bin related information.
Updated Ordering Information:
Updated part numbers.
*F 377095 PCI 06/10/2005 Updated Electrical Characteristics:
Updated Note 18 (Replaced “VDDQ < VDD” with “VDDQ VDD”).
*G 408298 RXU 11/16/2005 Changed address of Cypress Semiconductor Corporation in page 1 from “3901
North First Street” to “198 Champion Court”.
Replaced “three-state” with “tri-state” in all instances across the document.
Updated Electrical Characteristics:
Replaced “Input Load” with “Input Leakage Current except ZZ and MODE” in
“Description” column corresponding to IX parameter.
Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
Updated Package Diagrams:
spec 51-85180 – Changed revision from ** to *A.
Updated to new template.
*H 501793 VKN 09/13/2006 Updated Switching Characteristics:
Changed minimum value of tTH, and tTL parameters from 25 ns to 20 ns.
Changed maximum value of tTDOV parameter from 5 ns to 10 ns.
Updated Maximum Ratings:
Added “Supply Voltage on VDDQ Relative to GND” and its rating.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *A to *B.
*I 2898958 NJY 03/25/2010 Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *B to *C.
spec 51-85115 – Changed revision from *B to *C.
spec 51-85180 – Changed revision from *A to *C.
*J 3033272 NJY 09/19/2010 Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
Completing Sunset Review.
*K 3052726 NJY 10/08/2010 Updated Ordering Information:
Updated part numbers.
*L 3385314 PRIT 09/29/2011 Updated Package Diagrams:
spec 51-85050 – Changed revision from *C to *D.
Completing Sunset Review.
Document History Page (continued)
Document Title: CY7C1354CV25/CY7C1356CV25, 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05537
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *S Page 34 of 35
*M 3754566 PRIT 09/25/2012 Updated Package Diagrams:
spec 51-85115 – Changed revision from *C to *D.
spec 51-85180 – Changed revision from *C to *F.
Completing Sunset Review.
*N 4537527 PRIT 10/14/2014 Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*O 4571917 PRIT 11/18/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*P 4974141 PRIT 10/19/2015 Updated Package Diagrams:
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*Q 5509821 PRIT 11/04/2016 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*R 6021076 RMES 01/09/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*S 6534109 RMES 04/05/2019 Updated Ordering Information:
Updated part numbers.
Updated to new template.
Document History Page (continued)
Document Title: CY7C1354CV25/CY7C1356CV25, 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05537
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 38-05537 Rev. *S Revised April 5, 2019 Page 35 of 35
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
CY7C1354CV25
CY7C1356CV25
© Cypress Semiconductor Corporation, 2004–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to su blic ense) (1) under its co pyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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