PI74LVC138A 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Fast CMOS 3.3V, 3-Line to 8-Line Decoder/Demultiplexer Product Features Product Description * Functionally compatible with LCX family of products * 1.65V - 3.6V VCC supply operation, -40C to 85C * ESD Protection exceeds 2000V, Human Body Model 200V, Machine Model * Inputs accept up to 5.5V * Balanced sink and source output drives (24mA) * Low ground bounce outputs, <0.8V @ 3.3V, 25C * Packages available: - 16-pin 173-mil wide plastic TSSOP (L) - 16-pin 150-mil wide plastic SOIC (W) Pericom Semiconductor's PI74LVC series of logic circuits are produced using the Company's advanced 0.5 micron CMOS technology, achieving high speed while maintaining low-power operation. The PI74LVC138A devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of the system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Logic Diagram 15 A Selects Inputs B C 1 Y0 14 Y1 2 13 3 12 Y3 11 Inputs can be driven from either 3.3V or 5.0V devices allowing the PI74LVC138A to be used as a translator in a mixed 3.3V/5.0V system. Y2 Y4 Data Outputs 10 Y5 9 Enable Inputs G1 6 G2A 4 G2B 5 Y6 7 Y7 Truth Table Pin Configuration Enable Inputs Select Inputs Outputs G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L H H H H H H H H H X X L L L L L L L L X H X L L L L L L L L X X X L L L L H H H H X X X L L H H L L H H X X X L H L H L H L H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L 1 A 1 16 VCC B 2 15 Y0 C 3 14 Y1 G2A 4 Y2 G2B 5 16-Pin 13 L, W 12 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 PS8674 Y3 03/20/03 PI74LVC138A Fast CMOS 3.3V 3-line to 8-line Decoder/Demultiplexer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ............................................................ -0.5V to 6.5V Input voltage range, VI(1) ............................................................... -0.5V to 6.5V Output voltage range VO(1,2) ............................................... -0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ................................................................ -50mA Output clamp current, IOK (VO <0) ........................................................... -50mA Continuous output current, IO ................................................................ 50mA Continuous current through VCC or GND .............................................. 100mA Package thermal impedance, JA(3): W package ................................... 111C/W L package ....................................... 90C/W Storage Temperature range, Tstg ................................................................. -65C to 150C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current rating are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions(4) Pa ra me te r VC C D e s criptio n S up ply Vo ltage C o nditio n M in. M ax . O p erating 1 .6 5 3.6 Data retentio n o nly V IH V IL High- level Input Vo ltage Low - level Inp ut Vo ltage V C C = 1 .65 V to 1 .9 5 V 1 .5 0 .6 5 x V C C V C C = 2 .3V to 2 .7V 1 .7 V C C = 2 .7V to 3 .6V 2 .0 V C C = 1 .65 V to 1 .9 5 V V C C = 2 .3V to 2 .7V 0.7 V C C = 2 .7V to 3 .6V 0.8 Inp ut Vo ltage 0 5.5 VO O utp ut Vo ltage 0 VC C IO H High- level o utp ut current t/ V TA Lo w- level o utp ut current V C C = 1 .65 V - 4 V C C = 2 .3V - 8 V C C = 2 .7V - 12 VC C = 3V - 24 V C C = 1 .65 V 4 V C C = 2 .3V 8 V C C = 2 .7V 12 VC C = 3V 24 Inp ut transitio n rise o r fall rate O p erating free- air temp erature V 0 .35 x V C C VI IO L U nits -40 mA 10 ns/V 85 C Notes: 4. All unused inputs must be held at VCC or GND to ensure proper device operation. 2 PS8674 03/20/03 PI74LVC138A Fast CMOS 3.3V 3-line to 8-line Decoder/Demultiplexer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over Recommended Operating Free-Air Temperature Range, unless otherwise noted) Parameters VOH Test Conditions VCC Min. 1.65V to 3.6V VCC -0.2V IOH = -4mA 1.65V 1.2 IOH = -8mA 2.3V 1.7 IOH = -12mA 2.7V 2.2 3V 2.4 IOH = -24mA 3V 2.2 IOL = 100A 1.65V to 3.6V 0.2 IOL = 4mA 1.65V 0.45 IOL = 8mA 2.3V 0.7 IOL = 12mA 2.7V 0.4 IOL = 24mA 3V 0.55 IOH = -100A VOL Typ. Max. Units V II (All Inputs) VI = 5.5V or GND 3.6V 5 ICC VI = VCC or GND, IO = 0 3.6V 10 ICC One input a VCC -0.6V, Other inputs at VCC or GND 2.7V to 3.6V 500 CI VI = VCC or GND 3.3V A 3 pF All typical values are measured at VCC = 3.3V, TA = 25C. Operating Characteristics, TA= 25C Parameters Cpd Power Dissipation Capacitance Test Conditions VCC = 1.8V VCC = 2.5V VCC = 3.3V Typ. Typ. Typ. f = 10MHz 35 43 51 Units pF Switching Characteristics (Over Recommended Operating Free-Air Temperature Range, unless otherwise noted, see Figures 1 through 3.) Parameter From (Input) To (Output) A or B or C tpd G2A or G2B G1 Y VCC = 1.8V VCC = 2.5V 0.2V VCC = 2.7V VCC = 3.3V 0.3V Min. Max Min. Max. Min. Max. Min. Max. 1 15.9 1 9.9 1 7.9 1 6.7 1 15.4 1 9.4 1 7.4 1 6.5 1 14.4 1 8.4 1 6.4 1 5.8 tsk(o) Units ns 1 . Skew between any two outputs of the same package switching in the same direction. 3 PS8674 03/20/03 PI74LVC138A Fast CMOS 3.3V 3-line to 8-line Decoder/Demultiplexer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 1.8V 0.15V 2xVCC Open GND S1 1k From Output Under Test CL = 30pF 1k (See Note A) Test S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input tW VCC/2 VCC 0V tsu VCC/2 Input th VCC/2 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPLH tPHL Output Waveform 2 S1 at Open (see Note B) VOH Output VCC/2 VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC VCC/2 VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH VOL +0.15V VOL tPHZ VCC/2 VOH -0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. Outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd H. Not all parameters and waveforms are applicable to all devices. 4 PS8674 03/20/03 PI74LVC138A Fast CMOS 3.3V 3-line to 8-line Decoder/Demultiplexer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V 2xVCC 500 S1 From Output Under Test CL = 30pF Open GND 500 (See Note A) Test S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit tW VCC Timing Input VCC VCC/2 VCC/2 Input VCC/2 0V tsu 0V th VCC Data Input VCC/2 Voltage Waveforms Pulse Duration VCC/2 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL 0V Output Waveform 1 S1 at 2 x VCC (see Note B) VOH VCC/2 Output VCC/2 VOL tPLH tPHL Output Waveform 2 S1 at Open (see Note B) VOH Output VCC/2 VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC VCC/2 VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH VOL +0.15V VOL tPHZ VCC/2 VOH -0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 2. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. Outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd H. Not all parameters and waveforms are applicable to all devices. 5 PS8674 03/20/03 PI74LVC138A Fast CMOS 3.3V 3-line to 8-line Decoder/Demultiplexer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 2.7V and 3.3V 0.3V 6V 500 S1 Open GND From Output Under Test CL = 50pF 500 (See Note A) Test S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Load Circuit tW 2.7V Timing Input 2.7V 1.5V 1.5V Input 1.5V 0V tsu 0V th Voltage Waveforms Pulse Duration 2.7V Data Input 1.5V 1.5V 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL 0V Output Waveform 1 S1 at 2 x VCC (see Note B) VOH VCC/2 Output VCC/2 VOL tPLH tPHL Output Waveform 2 S1 at GND (see Note B) VOH Output VCC/2 VCC/2 VOL Voltage Waveforms Propagation Delay Times 2.7V 1.5V 1.5V 0V tPZL tPLZ 3V 1.5V tPZH VOL +0.3V VOL tPHZ 1.5V VOH -0.3V VOH 0V Voltage Waveforms Enable and Disable Times Figure 3. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.5ns, tF 2.5ns. D. Outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd H. Not all parameters and waveforms are applicable to all devices. 6 PS8674 03/20/03 PI74LVC138A Fast CMOS 3.3V 3-line to 8-line Decoder/Demultiplexer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 16-pin 150-mil wide SOIC (W) Package 16 .149 .157 3.78 3.99 .0099 .0196 0.25 x 45 0.50 1 .0075 .0098 0-8 .386 .393 9.80 10.00 0.41 1.27 .053 .068 .0155 .0260 0.393 0.660 REF 1.35 1.75 .016 .050 .2284 .2440 5.80 6.20 SEATING PLANE .050 BSC 1.27 0.19 0.25 .0040 0.10 .0098 0.25 .013 .020 0.330 0.508 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 16-pin 173-mil wide TSSOP (L) Package 16 .169 .177 4.3 4.5 1 .193 .201 4.9 5.1 .004 .008 .047 max. 1.20 0.45 .018 0.75 .030 SEATING PLANE .0256 BSC 0.65 .007 .012 .002 .006 0.09 0.20 .252 BSC 6.4 0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 0.19 0.30 Ordering Information Ordering Code Package Type PI74LVC138AL 16-pin, 173-mil wide plastic TSSOP PI74LVC138AW 16-pin, 150-mil wide plastic SOIC Operating Range -40C to 85C Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 7 PS8674 03/20/03