ASAHI KASEI [AK4356] AK4356 192kHz 24Bit Six-Channel DAC for DVD-Audio GENERAL DESCRIPTION The AK4356 is a high performance six channels DAC corresponding to 96kHz sampling mode of DVD. Two channels of them can operate up to 192kHz sampling fully correspond to DVD-Audio standards. The AK4356 introduces the advanced multi-bit architecture for modulator. This new architecture achieves the wider dynamic range, while keeping much the same superior distortion characteristics as conventional Single Bit way. In the AK4356, the analog outputs are filtered in the analog domain by switched-capacitor filter (SCF) with high tolerance to clock jitter. The analog outputs are full differential output, so the device is suitable for hi-end applications. FEATURES o 128x Oversampling o Sampling Rate up to 192kHz for 2 channels mode, 96kHz for 6 channels mode o 24Bit 8 times Digital Filter with Slow roll-off option Ripple: 0.005dB, Attenuation: 75dB o THD+N: -94dB o DR, S/N: 112dB o High Tolerance to Clock Jitter o Low Distortion Differential Output o Channel Independent Digital De-emphasis for 32, 44.1 & 48kHz sampling o Channel Independent Zero Detect Pin o Channel Independent Digital Attenuator with soft-transition o Soft Mute o 3-wire Serial Interface for Volume Control o I/F format: MSB justified, LSB justified, I2S o TTL Level Digital I/F o Master Clock Normal Speed: 256fs, 384fs, 512fs or 768fs Double Speed: 128fs, 192fs, 256fs or 384fs o Power Supply: 4.75 to 5.25V o 44pin LQFP Package o Ta: -40 to 85C M0072-E-02 2003/09 -1- ASAHI KASEI [AK4356] n Block Diagram DZFL1 LOUT1+ LOUT1DZFR1 ROUT1+ ROUT1DZFL2 LOUT2+ LOUT2DZFR2 ROUT2+ ROUT2DZFL3 LOUT3+ LOUT3DZFR3 ROUT3+ ROUT3- SCF DAC DATT SCF DAC DATT SCF DAC DATT SCF DAC DATT SCF DAC DATT SCF DAC Audio I/F AK4356 XTI XTO MCLK LRCK BICK MCKO LRCK Controller BICK CS CCLK CDTI Control Register LRCK BICK SDTI1 SDTI2 SDTI3 DATT M0072-E-02 AC3 SDOUT1 SDOUT2 SDOUT3 2003/09 -2- ASAHI KASEI [AK4356] n Ordering Guide AK4356VQ AKD4356 -40+85C Evaluation Board 44pin LQFP(0.8mm pitch) ROUT1+ ROUT1- LOUT2+ LOUT2- ROUT2+ ROUT2- LOUT3+ LOUT3- ROUT3+ ROUT3- AVSS 44 43 42 41 40 39 38 37 36 35 34 n Pin Layout LOUT1- 1 33 AVDD LOUT1+ 2 32 VREFH DZFL2 3 31 DZFR2 DZFR1 4 30 DZFL3 DZFL1 5 29 DZFR3 CAD0 6 28 DZFE CAD1 7 27 DIF2 AK4356VQ Top View 17 18 19 20 21 22 SMUTE CCLK CDTI CSN DFS0 CKS0 16 CKS1 15 CKS2 23 LRCK 24 11 SDTI3 10 DVDD 14 MCLK 13 DIF0 SDTI2 DIF1 25 SDTI1 26 9 12 8 BICK DVSS PDN M0072-E-02 2003/09 -3- ASAHI KASEI [AK4356] PIN/FUNCTION No. 1 2 3 4 5 6 7 8 Pin Name LOUT1LOUT1+ DZFL2 DZFR1 DZFL1 CAD0 CAD1 PDN I/O O O O O O I I I 9 10 11 12 13 14 15 16 17 BICK MCLK DVDD DVSS SDTI1 SDTI2 SDTI3 LRCK SMUTE I I I I I I I 18 19 20 CCLK CDTI CSN I I I Function DAC1 Lch Negative Analog Output Pin DAC1 Lch Positive Analog Output Pin DAC2 Lch Zero Input Detect Pin DAC1 Rch Zero Input Detect Pin DAC1 Lch Zero Input Detect Pin Chip Address 0 Pin Chip Address 1 Pin Power-Down & Reset Pin When "L", the AK4356 is powered-down and the control registers are reset to default state. If the state of CAD0-1 changes, then the AK4356 must be reset by PDN. Audio Serial Data Clock Pin Master Clock Input Pin Digital Power Supply Pin, +4.75+5.25V Digital Ground Pin DAC1 Audio Serial Data Input Pin DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin Audio Input Channel Clock Pin Soft Mute Pin (Note) When this pin goes to "H", soft mute cycle is initialized. When returning to "L", the output mute releases. Control Data Clock Pin Control Data Input Pin Chip Select Pin This pin should be held to "H" except for access. M0072-E-02 2003/09 -4- ASAHI KASEI [AK4356] No. 21 Pin Name DFS0 I/O I 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 CKS0 CKS1 CKS2 DIF0 DIF1 DIF2 DZFE DZFR3 DZFL3 DZFR2 VREFH AVDD AVSS ROUT3ROUT3+ LOUT3LOUT3+ ROUT2ROUT2+ LOUT2LOUT2+ ROUT1ROUT1+ I I I I I I I O O O I O O O O O O O O O O Function Double Speed Sampling Mode 0 Pin (Note) "L": Normal Speed, "H": Double Speed at DFS1 bit = "0". Input Clock Select 0 Pin (Note) Input Clock Select 1 Pin (Note) Input Clock Select 2 Pin (Note) Audio Data Interface Format 0 Pin (Note) Audio Data Interface Format 1 Pin (Note) Audio Data Interface Format 2 Pin (Note) Zero Input Detect Enable Pin (Note) DAC3 Rch Zero Input Detect Pin DAC3 Lch Zero Input Detect Pin DAC2 Rch Zero Input Detect Pin Positive Voltage Reference Input Pin, AVDD Analog Power Supply Pin Analog Ground Pin, +4.75+5.25V DAC3 Rch Negative Analog Output Pin DAC3 Rch Positive Analog Output Pin DAC3 Lch Negative Analog Output Pin DAC3 Lch Positive Analog Output Pin DAC2 Rch Negative Analog Output Pin DAC2 Rch Positive Analog Output Pin DAC2 Lch Negative Analog Output Pin DAC2 Lch Positive Analog Output Pin DAC1 Rch Negative Analog Output Pin DAC1 Rch Positive Analog Output Pin Note: SMUTE, DFS0, CKS0, CKS1, CKS2, DIF0, DIF1, DIF2, DZFE pins are ORed with serial control register. M0072-E-02 2003/09 -5- ASAHI KASEI [AK4356] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 1) Parameter Symbol min AVDD -0.3 Analog Power Supplies DVDD -0.3 Digital |AVSS-DVSS| (Note 2) GND Input Current (any pins except for supplies) IIN Analog Input Voltage VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature Ta -40 Storage Temperature Tstg -65 Note: 1. All voltages with respect to ground. 2. AVSS and DVSS must be connected to the same analog ground plane. max 6.0 6.0 0.3 10 AVDD+0.3 DVDD+0.3 85 150 Units V V V mA V V C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 1) Parameter Symbol min Power Supplies Analog AVDD 4.75 (Note 3) Digital DVDD 4.75 Note: 1. All voltages with respect to ground. 3. The power up sequence between AVDD and DVDD is not critical. typ 5.0 5.0 max 5.25 5.25 Units V V *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. M0072-E-02 2003/09 -6- ASAHI KASEI [AK4356] ANALOG CHARACTERISTICS (Ta=25C; AVDD, DVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=44.1kHz; BICK=64fs; Signal Frequency =1kHz; 24bit Data; RL2k; Measurement Frequency=20Hz20kHz at 44.1kHz, 20Hz~40kHz at fs=96kHz, 20Hz~80kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Dynamic Characteristics (Note 4) Resolution 24 S/(N+D) fs=44.1kHz 88 94 fs=96kHz 86 92 DR (-60dBFS) fs=44.1kHz, A-weighted 106 112 fs=96kHz 105 S/N (Note 5,6) fs=44.1kHz, A-weighted 106 112 fs=96kHz 105 Interchannel Isolation 90 110 DC Accuracy Interchannel Gain Mismatch 0.2 0.5 Gain Drift (Note 7) 20 Output Voltage (AOUT+) - (AOUT-) (Note 8) 2.55 2.75 2.95 Load Resistance (Note 9) 2 Load Capacitance 25 Power Supply Rejection (Note 10) 50 Power Supplies Power Supply Current Normal Operation (PDN = "H") AVDD 60 90 DVDD (fs=44.1kHz) 15 30 (fs=96kHz) 20 40 (fs=192kHz) 15 30 Power-Down-Mode (PDN = "L") AVDD+DVDD (Note 11) 10 100 Units Bits dB dB dB dB dB dB dB dB ppm/C Vpp k pF dB mA mA mA mA A Note: 4. Measured by UPD(ROHDE & SCHWARZ). Refer to the evaluation board manual. 5. 107dB at CCIR-ARM weighted 6. S/N is independent of input bit length. 7. VREFH is constantly +5.0V. 8. Full scale voltage (0dB). Output voltage scales with the voltage of VREFH pin. AOUT(typ.@0dB)=(AOUT+)-(AOUT-)=2.75Vpp*VREFH/5.0 9. AC load 10. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held a constant voltage. 11. All digital input pins including clock pins (MCLK, BICK and LRCK) are connected to DVSS. M0072-E-02 2003/09 -7- ASAHI KASEI [AK4356] FILTER CHARACTERISTICS (fs=44.1kHz) (Ta=25C; AVDD, DVDD=4.755.25V; fs=44.1kHz; DFS1 = DFS0 = "0"; DEM=OFF) Parameter Symbol min typ Digital Filter Passband (Note 12) 0.01dB PB 0 -6.0dB 22.05 Stopband (Note 12) SB 24.1 Passband Ripple PR Stopband Attenuation SA 75 Group Delay (Note 13) GD 27.2 Digital Filter + SCF FR Frequency Response: 020.0kHz 0.2 max Units 20.0 - - kHz kHz kHz dB dB 1/fs - dB 0.005 Note: 12. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@0.01dB), SB=0.546*fs. 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of both channels on the input register to the output of analog signal. FILTER CHARACTERISTICS (fs=96kHz) (Ta=25C; AVDD, DVDD=4.755.25V; fs=96kHz; DFS1 = "0"; DFS0 = "1"; DEM=OFF) Parameter Symbol min typ Digital Filter Passband (Note 14) 0.01dB PB 0 -6.0dB 48.0 Stopband (Note 14) SB 52.5 Passband Ripple PR Stopband Attenuation SA 75 Group Delay (Note 13) GD 27.2 Digital Filter + SCF FR Frequency Response: 040.0kHz 0.3 max Units 43.5 - - kHz kHz kHz dB dB 1/fs - dB 0.005 Note: 14. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@0.01dB), SB=0.546*fs. M0072-E-02 2003/09 -8- ASAHI KASEI [AK4356] FILTER CHARACTERISTICS (fs=192kHz) (Ta=25C; AVDD, DVDD=4.755.25V; fs=192kHz; DFS1 = "1"; DFS0 = "0"; DEM=OFF) Parameter Symbol min typ Digital Filter Passband (Note 15) 0.01dB PB 0 -6.0dB 96.0 Stopband (Note 15) SB 105 Passband Ripple PR Stopband Attenuation SA 75 Group Delay (Note 13) GD 27.2 Digital Filter + SCF FR Frequency Response: 080.0kHz 0.5 max Units 87.0 - - kHz kHz kHz dB dB 1/fs - dB max 0.8 0.5 10 Units V V V V A 0.005 Note: 15. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@0.01dB), SB=0.546*fs. DIGITAL CHARACTERISTICS (Ta=25C; AVDD, DVDD=4.755.25V) Parameter High-Level Input Voltage Low-Level Input Voltage Hight-Level Output Voltage (Iout= -100A) Low-Level Output Voltage (Iout= 100A) Input Leakage Current Symbol VIH VIL VOH VOL Iin M0072-E-02 min 2.2 DVDD-0.5 - typ - 2003/09 -9- ASAHI KASEI [AK4356] SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD=4.755.25V; CL=20pF) Parameter Master Clock Timing (Note 16) Frequency Duty LRCK frequency (Note 17) Normal Speed Mode (DFS1-0 = "00") Double Speed Mode (DFS1-0 = "01") 4 times Speed Mode (DFS1-0 = "10") Duty Cycle Serial Interface Timing BICK Period Normal Speed Mode Double Speed Mode 4 times Speed Mode BICK Pulse Width Low Pulse Width High BICK "" to LRCK Edge (Note 18) LRCK Edge to BICK "" (Note 18) SDTI Hold Time SDTI Setup Time Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" Rise Time of CSN Fall Time of CSN Rise Time of CCLK Fall Time of CCLK Power-down/Reset Timing PDN Pulse Width (Note 19) Symbol min typ max Units fCLK Duty 8.192 40 36.864 60 MHz % fsn fsd fsq Duty 32 64 128 45 48 96 192 55 kHz kHz kHz % tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/64fs 1/64fs 33 33 20 20 20 20 ns ns ns ns ns ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tR1 tF1 tR2 tF2 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns ns ns ns ns tPDW 150 20 20 20 20 ns Note: 16. For Double and 4 times Speed modes please see Appendix A for relationship of MCLK and BCLK/LRCK. 17. If sampling speed mode (DFS0-1) changes, please reset by PDN pin or RSTN bit. 18. BICK rising edge must not occur at the same time as LRCK edge. 19. The AK4356 can be reset by PDN pin "L" upon power up. If CKS0-2 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit. M0072-E-02 2003/09 - 10 - ASAHI KASEI [AK4356] n Timing Diagram tCLK VIH MCLK VIL 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing For Double and 4 times Speed modes timing please see Appendix A for relationship of MCLK and BCLK/LRCK. VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Audio Interface Timing M0072-E-02 2003/09 - 11 - ASAHI KASEI [AK4356] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL WRITE Data Input Timing tPDW PDN VIL Power-down & Reset Timing M0072-E-02 2003/09 - 12 - ASAHI KASEI [AK4356] OPERATION OVERVIEW System Clock Input The external clocks which are required to operate the AK4356 are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with sampling clock (LRCK) but the phase is not critical. However, in Double and 4 times Speed Modes, the phase relationship between MCLK and LRCK/BICK is limited. (Refer to Appendix A). MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. The frequency of MCLK can be set by CKS0-2, and can be selected to normal, double or 4 times speed mode by DFS0-1 (See Table 1). 4 times speed mode can be used for only DAC1. If DAC1 is in 4 times speed mode, DAC2 and DAC3 are automatically powered down. When the states of SLOW, DIF2-0, DFS1-0 or CKS2-0 changes, the AK4356 should be reset by PDN pin or RSTN bit. All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4356 is in normal operation mode (PDN = "H"). If these clocks are not provided, the AK4356 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4356 should be in the power-down mode (PDN = "L" or all DACs are set in the power-down mode by PW1-3 bits) or in the reset mode (RSTN = "0"). After exiting reset at power-up etc., the AK4356 is in the power-down mode until MCLK and LRCK are input. DFS1-0 "00" "01" (Normal Speed) (Double Speed) 0 128fs 256fs 1 256fs 256fs 0 384fs 192fs 1 384fs 384fs 0 512fs 256fs 1 512fs N/A 0 768fs 384fs 1 768fs N/A Table 1. System Clock (DFS1-0 = "11": reserved) Mode CKS2 CKS1 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 fs [kHz] 32 64 128 44.1 88.2 176.4 48 96 192 Mode Normal Double 4 times Normal Double 4 times Normal Double 4 times CKS0 128fs 192fs 256fs 384fs 8.1920 12.2880 8.1920 12.2880 16.3840 24.5760 16.3840 24.5760 11.2896 16.9344 11.2896 16.9344 22.5792 33.8688 22.5792 33.8688 12.2880 18.4320 12.2880 18.4320 24.5760 36.8640 24.5760 36.8640 Table 2. Example of System Clock [MHz] M0072-E-02 "10" (4 times Speed) N/A N/A N/A N/A 128fs N/A 192fs N/A 512fs 16.3840 22.5792 24.5760 - default (DFS1-0 = "00") 768fs 24.5760 33.8688 36.8640 - 2003/09 - 13 - ASAHI KASEI [AK4356] n Audio Serial Interface Format Audio data is input to the AK4356 via the SDTI1-3 pins using BICK and LRCK inputs. 5 serial data formats are supported and selected by DIF2-0 pins or DIF2-0 bits (See Table 3, compatible with the AK4324/4393). In all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0 SDTI L/R 16bit, LSB justified H/L 20bit, LSB justified H/L 24bit, MSB justified H/L I2S L/H 24bit, LSB justified H/L Table 3. Audio data format BICK 32fs 40fs 48fs 32fs or 48fs 48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 default LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 0 14 1 6 5 14 4 15 3 16 2 17 1 0 31 15 0 14 1 6 5 14 4 15 3 16 2 17 1 0 31 15 0 14 1 BICK (64fs) SDTI Mode 0 Don't care 15 14 0 Don't care 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing M0072-E-02 2003/09 - 14 - ASAHI KASEI [AK4356] LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1 0 1 BICK (64fs) SDTI Mode 1 Don't care 19 0 Don't care 19 0 Don't care 19 0 19 0 19:MSB, 0:LSB SDTI Mode 4 Don't care 23 22 21 20 23 22 20 21 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1,4 Timing LRCK 0 1 2 22 24 23 30 31 0 1 2 22 23 24 30 31 BICK (64fs) SDTI 23 22 1 0 Don't care 23 22 1 0 Don't care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing M0072-E-02 2003/09 - 15 - ASAHI KASEI [AK4356] LRCK 0 1 2 3 11 12 13 14 15 0 1 2 3 11 12 13 14 15 0 1 BICK (32fs) SDTI 8 0 23 1 22 2 13 3 23 12 24 11 25 10 9 31 8 0 23 1 22 2 12 13 3 23 24 11 25 10 9 31 8 0 23 1 BICK (64fs) SDTI 1 23 22 0 Don't care 23 22 1 0 Don't care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing n Output Volume The AK4356 includes channel independent digital output volumes (ATT) with 256 levels at 0.5dB steps including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to -127dB and mute. When changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. n De-emphasis filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc=50/15s). It can be set for DAC1 (SDTI1), DAC2 (SDTI2) and DAC3 (SDTI3) independently. It is enabled or disabled with the control register data of DEM1-0 and DFS1-0. The de-emphasis filter is disabled at double or 4 times sampling mode (except for DFS0 = DFS1 = "0"). DEM1 DEM0 De-emphasis 0 0 44.1kHz 0 1 OFF default 1 0 48kHz 1 1 32kHz Table 4. De-emphasis filter control with DEM1-0 (DFS1-0 = "00") DFS1 DFS0 De-emphasis 0 0 See Table 4. default 0 1 OFF 1 0 OFF 1 1 OFF Table 5. De-emphasis filter control with DFS1-0 M0072-E-02 2003/09 - 16 - ASAHI KASEI [AK4356] n Zero detection The AK4356 has channel-independent zeros detect function. When the input data at each channel is continuously zero for 8192 LRCK cycles, DZF pin of each channel goes to "H". DZF pin of each channel immediately goes to "L" if input data of each channel is not zero after going DZF "H". If RSTN bit is "0", DZF pins of all channels go to "H". DZF pins of all channels go to "L" 4/fs after RSTN bit returns to "1". If DZFM bit is set to "1", DZF pins of all channels go to "H" only when the input data at all channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be disabled by DZFE bit. In this case, DZF pins of all channels are always "L" (except for the case of RSTN = "0"). n Soft mute operation Soft mute operation is performed at digital domain. When the SMUTE pin goes to "H", the output signal is attenuated by - during 1024 LRCK cycles. When the SMUTE pin is returned to "L", the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE 1024/fs 0dB 1024/fs (1) (3) Attenuation - GD (2) GD AOUT DZF (4) 8192/fs Notes: (1) The output signal is attenuated by - during 1024 LRCK cycles (1024/fs). (2) Analog output corresponding to digital input have the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. (4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to "H". DZF pin immediately goes to "L" if input data are not zero after going DZF "H". Figure 5. Soft mute and zero detection n System Reset The AK4356 should be reset once by bringing PDN = "L" upon power-up. The AK4356 is powered up and the internal timing starts clocking by LRCK "" after exiting reset and power down state by MCLK. The AK4356 is in the power-down mode until MCLK and LRCK are input. M0072-E-02 2003/09 - 17 - ASAHI KASEI [AK4356] n Power-down All DACs are placed in the power-down mode by bringing PDN pin "L" and each digital filter is also reset at the same time. The internal register values are initialized by PDN "L". This reset should always be done after power-up. Because some click noise occurs at the edge of PDN, the analog output should be muted externally if the click noise influences system application. Figure 6 shows the power-down/up sequence. Each DAC can be powered down by each power-down bit (PW1-3) "0". In this case, the internal register values are not initialized and the analog output is Hi-Z. Because some click noise occurs, the analog output should be muted externally if the click noise influences system application. If DAC1 is in 4 times speed mode (DFS1=1, DFS0=0), DAC2 and DAC3 are automatically powered down. Both analog outputs go to analog common voltage (AVDD/2). PDN Internal State Normal Operation Power-down D/A In (Digital) Normal Operation "0" data GD D/A Out (Analog) (1) GD (3) (2) (3) (1) (4) Clock In Don't care MCLK, LRCK, BICK DZF External MUTE (6) (5) Mute ON Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode. (3) Click noise occurs at the edge of PDN signal. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = "L"). (5) Please mute the analog output externally if the click noise (3) influences system application. The timing example is shown in this figure. (6) DZF pins of all channels are "L" in the power-down mode (PDN = "L"). Figure 6. Power-down/up sequence example M0072-E-02 2003/09 - 18 - ASAHI KASEI [AK4356] n Reset Function When RSTN=0, all DACs are powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZF pins of all channels go to "H". Figure 7 shows the sequence of reset by RSTN bit. RSTN bit 2~3/fs (6) Internal RSTN bit Internal State Normal Operation D/A In (Digital) "0" data (1) D/A Out (Analog) Normal Operation Digital Block Power-down GD GD (3) (2) (3) (1) (4) Clock In Don't care MCLK,LRCK,BICK 2/fs(5) DZFL/DZFR Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage. (3) Click noise occurs at the edges(" ") of the internal timing of RSTN bit. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = "L"). (5) DZF pins go to "H" when the RSTN bit becomes "0", and go to "L" at 4~5/fs after RSTN bit becomes "1". (6) There is a delay, 2~3/fs from RSTN bit "1" to the internal RSTN "1". Figure 7. Reset sequence example M0072-E-02 2003/09 - 19 - ASAHI KASEI [AK4356] n Serial Control Interface The AK4356 can control its functions via both pins and registers. CKS2-0, DIF2-0, DFS0, DZFE and SMUTE pins are ORed with their registers. Internal registers may be written to the 3 wire uP interface pins: CSN, CCLK & CDTI. The data on this interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK. Data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max). The CSN pin should be held to "H" except for access. The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = "L" initializes the registers to their default values. Writing "0" to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be initialized. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1=CAD1, C0=CAD0) Read/Write (Fixed to "1" : Write only) Register Address Control Data Figure 7. Control I/F Timing Function Pin set-up Register set-up Double Speed O O 4 times Speed X O De-emphasis X O DZFE O O DZFM X O SMUTE O O Attenuator X O Slow roll-off response X O Table 6. Function Table (O: Supported, X: Not supported) Note: Writing to control register is inhibited when PDN = "L" or the MCLK is not fed. M0072-E-02 2003/09 - 20 - ASAHI KASEI [AK4356] n Mapping of Program Registers Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH Register Name Control 1 Control 2 Speed & Power Down Control De-emphasis Control LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control Test Mode D7 0 0 0 0 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 0 D6 SLOW 0 0 0 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 0 D5 DZFM 0 DFS1 D4 DZFE CKS2 DFS0 D3 DIF2 CKS1 PW3 D2 DIF1 CKS0 PW2 D1 DIF0 PW1 D0 RSTN RSTN RSTN DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 0 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 TEST4 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 TEST3 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 TEST2 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 TEST1 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 TEST0 SMUTE Note: For addresses from 0BH to 1FH, data is not written. When PDN goes to "L", the registers are initialized to their default values. When RSTN bit goes to "0", the internal timing is reset, DZF pins of all channels go to "H" but registers are not initialized to their default values. DZFE, DIF2-0, CKS2-0, SMUTE and DFS0 are ORed with pins. M0072-E-02 2003/09 - 21 - ASAHI KASEI [AK4356] n Register Definitions Addr 00H Register Name Control 1 Default D7 0 0 D6 SLOW 0 D5 DZFM 0 D4 DZFE 0 D3 DIF2 0 D2 DIF1 0 D1 DIF0 0 D0 RSTN 1 RSTN: Internal timing reset 0: Reset. DZF pins of all channels go to "H" and registers are not initialized. 1: Normal operation When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit. Some click noise occurs at that timing. DIF2-0: Audio data interface modes (See Table 3.) Initial: "000", Mode 0 Register bits of DIF2-0 are ORed with the DFS2-0 pins. DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit. In this case, the DZF pins of all channels are always "L". Register bit of DZFE is ORed with the DZFE pin. DZFM: Data Zero Detect Mode 0: Channel Separated Mode 1: Channel ANDed Mode If the DZFM bit is set to "1", the DZF pins of all channels go to "H" only when the input data at all channels are continuously zeros for 8192 LRCK cycles. SLOW: Slow roll-off response enable 0: Disable 1: Enable Addr 01H Register Name Control 2 Default D7 0 0 D6 0 0 D5 0 0 D4 CKS2 0 D3 CKS1 0 D2 CKS0 0 D1 SMUTE 0 D0 RSTN 1 RSTN: Internal timing reset 0: Reset. DZF pins of all channels go to "H" and registers are not initialized. 1: Normal operation When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit. Some click noise occurs at that timing. SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft-muted Register bit of SMUTE is ORed with the SMUTE pin. CKS2-0: Master Clock Frequency Select (See Table 2.) Initial: "000", Mode 0 Register bits of CKS2-0 are ORed with the CKS2-0 pins. M0072-E-02 2003/09 - 22 - ASAHI KASEI Addr 02H [AK4356] Register Name Speed & Power Down Control Default D7 0 0 D6 0 0 D5 DFS1 0 D4 DFS0 0 D3 PW3 1 D2 PW2 1 D1 PW1 1 D0 RSTN 1 RSTN: Internal timing reset 0: Reset. DZF pins of all channels go to "H" and registers are not initialized. 1: Normal operation When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit. Some click noise occurs at that timing. PW3-1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 PW2: Power down control of DAC2 PW3: Power down control of DAC3 All sections are powered-down by PW1=PW2=PW3=0. DFS1-0: Sampling speed control (See Table 1.) 00: Normal speed 01: Double speed 10: 4 times speed (DAC2 and DAC3 are automatically powered down.) Register bit of DFS0 is ORed with the DFS0 pin. When sampling speed mode is changed between normal and double/4 times speed mode, DFS1-0 bit should be changed after changing MCLK frequency (figure below). Some click noise occurs at this timing. MCLK Sampling speed normal 4 times /double normal When sampling speed mode is changed between double and 4 times speed mode, sampling mode should be changed to normal speed mode after changing MCLK frequency, and then it should be changed to double/4 times speed mode (figure below). Some click noise occurs at those changing timing. MCLK Addr 03H Register Name De-emphasis Control Default Sampling speed double/ 4 times D7 0 0 D6 0 0 normal 4 times /double D5 D4 D3 D2 D1 D0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0 0 1 0 1 0 1 DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (See Table 4,5.) Initial: "01", OFF DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 (See Table 4,5.) Initial: "01", OFF DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (See Table 4,5.) Initial: "01", OFF M0072-E-02 2003/09 - 23 - ASAHI KASEI Addr 04H 05H 06H 07H 08H 09H [AK4356] Register Name LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control Default D7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 1 D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 1 D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 1 D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 1 D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 1 D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 1 D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 1 D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 1 ATT7-0: Attenuation Level 256 levels, 0.5dB step ATT7-0 FFH FEH FDH : : 02H 01H 00H Attenuation 0dB -0.5dB -1.0dB : : -126.5dB -127.0dB MUTE (-) The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from FFH(0dB) to 00H(MUTE). If PDN pin goes to "L", the ATTs are initialized to FFH. The ATTs are FFH when RSTN = "0". When RSTN return to "1", the ATTs fade to their current value. Digital attenuator is independent of soft mute function. Addr 0AH Register Name Test Mode Default D7 0 0 D6 0 0 D5 0 0 D4 TEST4 0 D3 TEST3 0 D2 TEST2 0 D1 TEST1 0 D0 TEST0 0 TEST4-0: Test mode M0072-E-02 2003/09 - 24 - ASAHI KASEI [AK4356] SYSTEM DESIGN Figure 8 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Condition: Chip Address="00" + 10u Digital 5V 0.1u ROUT1- 43 14 SDTI2 LOUT2+ 42 15 SDTI3 LOUT2- 41 AK4356 16 LRCK ROUT2+ 40 17 SMUTE ROUT2- 39 18 CCLK LOUT3+ 38 Top View 19 CDTI LOUT3- 37 L1ch LPF L1ch MUTE L1ch OUT R1ch LPF R1ch MUTE R1ch OUT L2ch LPF L2ch MUTE L2ch OUT R2ch LPF R2ch MUTE R2ch OUT L3ch LPF L3ch MUTE L3ch OUT R3ch LPF R3ch MUTE R3ch OUT 33 AVDD 32 VREFH 31 DZFR2 30 DZFL3 29 DZFR3 AVSS 34 28 DZFE 22 CKS0 26 DIF1 ROUT3- 35 25 DIF0 ROUT3+ 36 21 DFS0 24 CKS2 20 CSN 23 CKS1 uP ROUT1+ 44 13 SDTI1 27 DIF2 DSP LOUT1- 1 DZFL2 3 12 DVSS LOUT1+ 2 DZFR1 4 CAD0 6 DZFL1 5 PDN 8 CAD1 7 BICK 9 DIR MCLK 10 DVDD 11 Reset Mode Control Analog 5V + 0.1u System Ground 10u Analog Ground Figure 8. Typical Connection Diagram M0072-E-02 2003/09 - 25 - ASAHI KASEI [AK4356] 9 8 7 6 5 4 3 2 1 BICK PDN CAD1 CAD0 DZFL1 DZFR1 DZFL2 LOUT1+ LOUT1- MCLK 10 Analog Ground DVDD 11 12 DVSS ROUT1- 43 14 SDTI2 LOUT2+ 42 15 SDTI3 LOUT2- 41 16 LRCK ROUT2+ 40 AK4356 ROUT3- 35 22 CKS0 AVSS 34 33 AVDD 21 DFS0 31 DZFR2 ROUT3+ 36 30 DZFL3 37 20 CSN 29 DZFR3 LOUT3- 26 DIF1 38 19 CDTI 25 DIF0 39 LOUT3+ 24 CKS2 ROUT2- 18 CCLK 23 CKS1 17 SMUTE 28 DZFE Controller ROUT1+ 44 13 SDTI1 27 DIF2 System 32 VREFH Digital Ground Figure 9. Ground Layout Note: AVSS and DVSS must be connected to the same analog ground plane. 1. Grounding and Power Supply Decoupling The AK4356 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the AK4356 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be near to the AK4356 as possible, with the small value ceramic capacitors being the nearest. 2. Voltage Reference Inputs VREFH sets the analog output range. VREFH pin is normally connected to AVDD with a 0.1F ceramic capacitor. All signals, especially clocks, should be kept away from the VREFH pin in order to avoid unwanted coupling into the AK4356. 3. Analog Outputs The analog outputs are full-differential outputs and 0.55 x VREFH Vpp (typ) centered around the internal common voltage (about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 5.5Vpp (typ @VREFH=5V). The bias voltage of the external summing circuit is supplied externally. The input data format is 2's complement. The output voltage(VAOUT) is a positive full scale for 7FFFFF(@24bit) and a negative full scale for 800000H(@24bit). The ideal VAOUT is 0V for 000000H(@24bit). The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. DC offset on AOUT+/- is eliminated without AC coupling since the analog outputs are differential. Figure 10 and 11 show the example of external op-amp circuit summing the differential outputs. M0072-E-02 2003/09 - 26 - ASAHI KASEI [AK4356] 4.7k AOUT- 4.7k 470p R1 Vop 3300p 4.7k AOUT+ Vop Analog Out R1 4.7k 470p 1k BIAS 47u 0.1u When R1=200 fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz 1k Figure 10. External 2nd order LPF Circuit Example (using op-amp with single power supply) AOUT- 4.7k 4.7k R1 470p +Vop 3300p AOUT+ 4.7k Analog Out R1 4.7k 470p -Vop When R1=200 fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies) M0072-E-02 2003/09 - 27 - ASAHI KASEI [AK4356] PACKAGE 44pin LQFP (Unit: mm) 1.70max 12.800.30 00.2 10.00 23 33 0.80 12.800.30 22 10.00 34 12 44 1 11 0.370.10 0.170.05 010 0.600.20 0.15 n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate M0072-E-02 2003/09 - 28 - ASAHI KASEI [AK4356] MARKING AKM AK4356VQ XXXXXXX JAPAN 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4356VQ 4) Country of Origin 5) Asahi Kasei Logo IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. M0072-E-02 2003/09 - 29 - ASAHI KASEI [AK4356] Appendix A In Double and 4 times Speed Modes, the phase relationship between MCLK and LRCK/BICK is limited (Table 7). If the phase relationship happens during this prohibited period, it is possible to occur the inverse of output channel. The phase relationship must be set to avoid the prohibited period when the AK4356 operates at Double Speed Mode or 4 times Speed Mode. The prohibited period is specified by the combination of digital power supply voltage (DVDD), MCLK frequency and audio data format (Table 3). When the audio data formats are 16/20/24bit LSB Justified (Mode 0,1,4) and 24bit MSB Justified (Mode 2), the phase relationship (tLRM: Figure 12) between the rising edge of LRCK and the rising edge of MCLK has the prohibited period of min to max in Table 7. In case of I2S Compatible (Mode 3), the relationship between the falling edge of BICK and the rising edge of MCLK has the prohibited period (tBCM: Figure 13) Sampling Mode Double Speed Double Speed Double Speed Double Speed Double Speed Double Speed 4 times Speed 4 times Speed Digital Power Supply, DVDD 4.75 to 5.25V 4.75 to 5.25V 4.75 to 5.25V 4.75 to 5.25V 4.75 to 5.25V 4.75 to 5.25V 4.75 to 5.25V 4.75 to 5.25V MCLK Frequency 128fs 192fs 256fs 256fs 384fs 384fs 128fs 192fs CKS2 0 0 0 1 0 1 1 1 Mode Setting CKS1 CKS0 DFS1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 DFS0 1 1 1 1 1 1 0 0 Prohibited Period min max 0.1 0.6 -0.6 -0.1 -0.7 -0.2 -0.7 -0.2 -1.4 -0.9 -1.4 -0.9 -0.7 -0.2 -1.4 -0.9 Units ns ns ns ns ns ns ns ns Table 7. Prohibited Period LRCK 1.5V tLRM 1.5V MCLK Figure 12. 16/20/24bit LSB Justified, 24bit MSB Justified BICK 1.5V tBCM 1.5V MCLK Figure 13. I2S Compatible M0072-E-02 2003/09 - 30 -