February 2005 Data Sheet

© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

in 5

increments

and GND

configurations

Product Family Block Diagram

General Description and Overview

The ispClock5610 and ispClock5620 are in-system-programmable high-fanout PLL-based clock drivers designed

for use in high performance communications and computing applications. The ispClock5610 provides up to 10 sin-

gle-ended or five differential clock outputs, while the ispClock5620 provides up to 20 single-ended or 10 differential

clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS,

volatile E

Table 1. ispClock5600 Family Members

Figure 1. ispClock5610 Functional Block Diagram

Absolute Maximum Ratings

Core Supply Voltage V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V

PLL Supply Voltage V

JTAG Supply Voltage V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V

Output Driver Supply Voltage V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V

Output Voltage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V

= 2.5V 2.375 2.5V 2.625 — — — — — —

= 3.3V 3.0 3.3 3.6 — — — — — —

Erase/Reprogram Cycles 1000 — —

= 640MHz 110 120 mA

= 640MHz 150 160 mA

Logic Standard

(V) V

Max. (V) V

LVCMOS 2.5V -0.3 0.7 1.7 3.6 0.4 V

SSTL2 Class 1 -0.3 V

- 0.18 V

SSTL3 Class 1 -0.3 V

- 0.2 V

Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other

selected parameters as noted in the various tables of this data sheet.

from the Lattice web site at www.latticesemi.com).

quency-lock mode can be set from 16 through 256.

tion of the LOCK output.

Figure 11. ispClock5600 Loop Filter (Simplified)

used to optimize overall jitter performance including phase jitter.

divider values:

V DC% V DC%

41040

81443

12 18 44

16 22 45

20 26 46

24 30 47

28 34 47

56 62 48

be determined by

enabled, features such as lock detect and skew generation are unavailable.

Reference and External Feedback Inputs

Table 5. REFSEL and FBKSEL Operation for ispClock5620

0 REFA+/- 0 FBKA+/-

1 REFB+/- 1 FBKB+/-

M x Vk

The following usage guidelines are suggested for interfacing to supported logic families.

LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)

pair. The ‘-’ input terminal should be tied to the appropriate VREF value, and the associated REFVTT or FBKVTT

terminal should be tied to a VTT termination supply. The positive input’s terminating resistor should be engaged and

set to 50Ω. Figure 15 shows an appropriate configuration. Refer to the “Recommended Operating Conditions -

Supported Logic Standards” table in this data sheet for suitable values of VREF and VTT.

and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive

divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage

Figure 15. SSTL2, SSTL3, HSTL Receiver Configuration

HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory

systems. Figure 16 shows how ispClock5600 reference input should be configured for accepting these standards.

Figure 16. Differential HSTL/SSTL Receiver Configuration

LVDS/Differential LVPECL

may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out-

properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5600’s inter-

(Figure 18)

Figure 18. LVPECL Input Receiver Configuration

Output Drivers

The ispClock5600 provide banks of configurable, internally-terminated high-speed dual-output line drivers. The

ispClock5610 provides five driver banks, while the ispClock5620 provides ten. Each of these driver banks may be

configured to provide either a single differential output signal, or a pair of single-ended output signals. Programma-

ble internal source-series termination allows the ispClock5600 to be matched to transmission lines with imped-

ances ranging from 40 to 70 Ohms. The outputs may be independently enabled or disabled, either from E2CMOS

configuration or by external control lines. Additionally, each can be independently programmed to provide a fixed

amount of signal delay or skew, allowing the user to compensate for the effects of unequal PCB trace lengths or

to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground

where possible. All GND0 pins must be tied to ground, regardless of whether or not the associated bank is used.

thought the profile select inputs PS0 and PS1, as shown in Table 8.

Table 8. Profile Select Function

Each profile controls the following internal configuration items:

(<100 MHz) which gradually increases as it approaches a locked condition. To prevent invalid outputs from being

applied to the rest of the system, it is recommended that either the SGATE, OEX, or OEY pins be used to control

the outputs based on the status of the LOCK pin. Holding the SGATE pin LOW during power-up will result in the

GOE HIGH also disables internal feedback and will prevent the device from ever achieving lock.

Figure 28. PAC-Designer Design Entry Screen

In-System Programming

The ispClock5600 is an In-System Programmable (ISP™) device. This is accomplished by integrating all E2CMOS

configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG

interface at normal logic levels. Once a device is programmed, all configuration information is stored on-chip, in

non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispClock5600 instruc-

tions are described in the JTAG interface section of this data sheet.

User Electronic Signature

A user electronic signature (UES) feature is included in the E2CMOS memory of the ispClock5600. This consists of

IEEE 1149.1 serial interface section of this data sheet.

Production Programming Support

preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production

programming equipment, giving customers a wide degree of freedom and flexibility in production planning.

Evaluation Fixture

allel port of a PC using a Lattice ispDOWNLOAD® cable. It demonstrates proper layout techniques for the

PACCLK5620-EV Evaluation board only, with components, fully assembled.

specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.

1149.1-1990 (which now includes IEEE Std. 1149.1a-1993).

ified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manu-

facturer. The two required registers are the bypass and boundary-scan registers. Figure 30 shows how the

instruction and various data registers are organized in an ispClock5600.

Figure 30. ispClock5600 TAP Registers

TAP Controller Specifics

an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a

reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on

default state.

Figure 31. TAP States

only in their entry points. When either block is entered, the first action is a capture operation. For the Data Regis-

ters, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previ-

ously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load

the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a

Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in a

compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state.

Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new

function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-

Test-Logic-Rst

Note: The value shown adjacent to each state transition in this figure

represents the signal present at TMS at the time of a rising edge at TCK.

the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec-

tively). The ispClock5000 contains the required minimum instruction set as well as one from the optional instruction

set. In addition, there are several proprietary instructions that allow the device to be configured and verified. For

The following table lists the instructions supported by the ispClock5600 JTAG Test Access Port (TAP) controller:

tion is defined by the 1149.1 standard to be all zeros (000000).

EXTEST 0000 0000 External Test.

ADDRESS_SHIFT 0000 0001 Address register (10 bits)

DATA_SHIFT 0000 0010 Address column data register (89 bits)

BULK_ERASE 0000 0011 Bulk Erase

PROGRAM 0000 0111 Program column data register to E2

PROGRAM_DISABLE 0001 1110 Disable Program Mode

HIGHZ 0001 1000 Force all outputs to High-Z state

SAMPLE/PRELOAD 0001 1100 Capture current state of pins to boundary scan register

CLAMP 0010 0000 Drive I/Os with boundary scan register

USER_LOGIC_RESET 0010 0010 Resets User Logic

INTEST 0010 1100 Performs in-circuit functional testing of device.

ERASE DONE 0010 0100 Erases the ‘Done’ bit only

PROG_INCR 0010 0111 Program column data register to E2 and auto-increment address register

scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this

instruction is defined by Lattice as shown in Table 9.

shifted out. The device must already be in programming mode for this instruction to execute.

ming mode for this instruction to execute.

PROGRAM_USERCODE – This instruction writes the contents of the UES register (32 bits) into E2CMOS memory.

The device must already be in programming mode for this instruction to execute.

INTEST – This instruction performs in-circuit functional testing of the device.