EtronTech Em51256C 32K x 8 High Speed SRAM Preliminary, 3/96 Features Pin Assignment 28-Pin 300-mil DIP and SOJ * Fast Access Time: 10ns/12ns/15ns * 32K x 8 Organization A14 1 28 Vcc A12 2 27 WE# A7 3 26 A13 A6 4 25 A8 * Low Power Consumption A5 5 24 A9 A4 6 23 A11 * Fully Static Operation A3 7 22 OE# * TTL Compatible I/O A2 8 21 A10 A1 9 20 CS# * Common I/O for Low Pin Count A0 10 19 I/O8 * JEDEC Standard Pinouts I/O1 11 18 I/O7 I/O2 12 17 I/O6 * Three Package Types 28-pin 300-mil plastic SOJ 28-pin 300-mil plastic DIP 28-pin 8 x 13.4mm plastic TSOP 1 (Forward Type) I/O3 13 16 I/O5 GND 14 15 I/O4 * Single +5V 10% Power Supply * Advanced CMOS Process Ordering Information Part Number Speed Em51256C-10J 10ns Package SOJ Em51256C-10P 10ns DIP Em51256C-12J 12ns SOJ Em51256C-12P 12ns DIP Em51256C-15J 15ns SOJ Em51256C-15P 15ns DIP Em51256C-15TS 15ns TSOP 1 Key Specifications Speed tRC tOE Active Stand By - 10 10ns 10ns 5ns 195mA 20mA - 12 12ns 12ns 7ns 195mA 20mA - 15 15ns 15ns 8ns 150mA 10mA tAA 28-Pin 8 x 13.4mm TSOP 1 OE# 1 28 A10 A11 2 27 CS# A9 3 26 I/O8 A8 4 25 I/O7 A13 5 24 I/O6 WE# 6 23 I/O5 Vcc 7 22 I/O4 A14 8 21 GND A12 9 20 I/O3 A7 10 19 I/O2 A6 11 18 I/O1 A5 12 17 A0 A4 13 16 A1 A3 14 15 A2 Pin Names Symbol A0 - A14 I/O1 - I/O8 CS# OE# WE# GND Vcc Function Address Inputs Data Inputs/Outputs Chip Select Output Enable Write Enable Ground +5V Power Supply Overview The Em51256C is a high speed SRAM organized in 32,768 words by 8 bits. It is designed with advanced CMOS technology. Each memory cell consists of four transistors and two high valued resistors. It allows lower power consumption and faster access time. The Em51256C follows JEDEC standard pinouts. It is packaged in three kind of package types, that are 28-pin 300-mil plastic SOJ, 28-pin 300-mil plastic DIP and 28-pin 8 x 13.4mm plastic TSOP 1 (forward type). Etron Technology Inc. 1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Em51256C Block Diagram A3 A4 A5 A6 A7 A8 A12 A13 A14 Address Buffer 9 Memory Cell Array 512 Rows 512 Columns 512 Row Decoders 64 x 8 I/O1 ~ I/O8 8 8 8 Input Data Control Sense/Switch 512 Column Decoders 6 Output Data Control Address Buffer CS# OE# A11 A10 A9 A2 A1 A0 WE# Preliminary 2 March 1996 EtronTech Em51256C Absolute Maximum Ratings Supply voltage, VCC Input and output voltages, VIN -0.5 to VCC +0.3V -0.5 to +7.0V Operating temperature, TOPR 0 to +70C Storage temperature, TSTG -55 to +125C Power dissipation, PD 1.0 W Notes: Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The devices should be operated within the limits specified under DC and AC Characteristics. Truth Table1 ICC CS# H WE# X OE# X Mode Not selected I/O High-Z L H L Read Active L H H L L X DOUT disabled Write DOUT High-Z DIN Active Standby Active Notes: 1. X = don't care Capacitance1 TA = 25C; f = 1 MHz Parameter Input capacitance I/O capacitance Symbol Min Typ Max Unit Test Conditions CIN CI/O 6 pF 8 pF VIN = 0V VI/O = 0V Notes: 1. This parameter is sampled and not 100% tested. Preliminary 3 March 1996 EtronTech Em51256C Recommended Operating Conditions Parameter Symbol Min Typ Max Unit VCC VIL 4.5* 5.0 5.5 V - 0.5 0.8 V 2.2 V 0 VCC + 0.3 70 Supply voltage Input voltage, low Input voltage, high Ambient temperature VIH TA C Note: 1. For Em51256C-10, supply voltage (min) is 4.75V. DC Characteristics TA = 0 to +70C; VCC = +5.0V 10% Parameter Symbol Test Conditions Min - 10 Max Min - 12 Max Min - 15 Max Unit Input leakage current ILI VIN = 0 to VCC; VCC = max -5 -5 -5 -5 -5 5 A Output leakage current ILO VOUT = 0 to VCC; OE# or CS# = VIH; VCC = max - 10 - 10 - 10 - 10 - 10 10 A Operating supply current 1 ICC CS# = VIL; f = MAX IDOUT = 0 mA 195 195 150 mA TTL standby current 1 ISB CS# = VIH, f = MAX 70 70 50 mA ISB12 CS#UVCC - 0.2V VI/O, VINO0.2V or U VCC - 0.2V, f = 0 20 20 10 mA Output voltage, low VOL IOL = 8.0 mA 0.4 0.4 0.4 V Output voltage, high VOH IOH = - 4.0 mA 2.4 2.4 2.4 V CMOS standby current Notes: 1. At f = MAX all I/O pin are cycling at the max frequency of 1/tRC. 2. f = 0 means no I/O lines changes. Preliminary 4 March 1996 EtronTech Em51256C AC Characteristics * TA = 0 to +70C * Vcc = 5.5V ~ 4.5V for Em51256C-12/15 Vcc = 5.5V ~ 4.75V for Em51256C-10 * Input pulse levels: Vss to 3.0V * Input rise and fall times: 3ns * Input and Output timing reference levels: 1.5V * Output load: See figure 1 and figure 2 Fig 1. Output Load 5V 480 DOUT 30pF* 25 5 * Including Scope and Jig Fig 2. Output Load for tCHZ, tCLZ, tOLZ, tOHZ, tWZ and tOW 5V 480 DOUT 25 5 5 pF* * Including Scope and Jig Preliminary 5 March 1996 EtronTech Parameter Em51256C Symbol Em51256C - 10 Min Max Em51256C - 12 Min Max Em51256C - 15 Min Max Unit Read Cycle Read cycle time tRC 10 12 15 ns Address access time tAA 10 12 15 ns Chip select access time tACS 10 12 15 ns Output hold from address change tOH 3 5 5 ns Chip selection to output in low-Z 1 tCLZ 3 3 3 ns Chip deselection to output in high-Z 1 tCHZ 0 5 0 5 0 7 ns Output enable access time tOE 5 7 8 ns Output disable to output in low-Z 1 tOLZ 0 0 0 ns Output disable to output in high-Z 1 tOHZ 5 5 7 ns Chip selection to power-up time tPU 0 0 0 ns Chip deselection to power-down time tPD 10 12 15 ns Write cycle time tWC 10 12 15 ns Chip select to end of write tCW 10 9 10 ns Address valid to end of write tAW 10 11 13 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 10 8 10 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 7 6 8 ns Data hold time tDH 0 0 0 ns Write enable to output in high-Z 1 tWZ 0 3 0 5 0 7 ns Output active from end of write 1 tOW 3 3 3 ns Write Cycle Notes: 1. Transition is measured at +/-200 mV from steady-state voltage with the loading shown is Fig.2. These AC parameters are sampled but not 100% tested. Preliminary 6 March 1996 EtronTech Em51256C Timing Waveforms Read Cycle No. 1 (Address Access) t RC Address Address Valid t AA t OH DOUT Data Valid Previous Data Valid Note : (1) WE is high for a read cycle. (2) The device is continuously selected; CS= V IL Read Cycle No. 2 (Chip Select Access) t RC Address Address Valid t AA t ACS CS t CHZ t CLZ High Impedance D High Impedance OUT Note : (1) WE is high for a read cycle. (2) Address valid prior to or coincident with CS transition low. Preliminary 7 March 1996 EtronTech Em51256C Read Cycle No. 3 (OE Access) t RC Address t AA OE t OE D High Impedance t OHZ t OLZ Data Valid OUT Preliminary 8 March 1996 EtronTech Em51256C Timing Waveforms (Cont.) Write Cycle No. 1 (WE-Controlled) t WC *1 Address t AW t CW CS t AS t WP t WR WE t DW D IN t DH Data-in Valid t OW t W Z *3 *2 D High Impedance Data Undefined OUT (2) If OE is high, the I/O pins remain in high-Z state. No te s: (3) During data undefined period, the I/O pins may be active. Data input signals of oppsite polarity to I/O pins must not to applied. (1) CS or WE must be high during address transition. Write Cycle No. 2 (CS-Controlled) *1 t WC Address t WR t AW t t CW AS CS t WP WE t DW D IN t DH Data-in Valid tWZ *2 High Impedance Data Undefined D OUT No te s: (1) CS or WE must be high during address transition. (2) If OE is high, the I/O pins remain in a high-Z state. Preliminary 9 March 1996 EtronTech Em51256C Outline Drawing 28-pin 300-mil SOJ 28 E HE 15 1 14 L A2 A C D e b A1 s b1 Symbol D Seating Plane Dimension in inch Dimension in mm e Min -----0.027 0.095 0.026 0.016 0.008 -----0.295 0.044 Nom ----------0.100 0.028 0.018 0.010 0.710 0.300 0.050 Max 0.140 -----0.105 0.032 0.022 0.014 0.730 0.305 0.056 Min -----0.69 2.41 0.66 0.41 0.20 -----7.49 1.12 Nom ----------2.54 0.71 0.46 0.25 18.03 7.62 1.27 Max 3.56 -----2.67 0.81 0.56 0.36 18.54 7.75 1.42 e1 HE L S Y 0.245 0.327 0.077 ----------0 0.265 0.337 0.087 ---------------- 0.285 0.347 0.097 0.045 0.004 10 6.22 8.31 1.96 ----------0 6.73 8.56 2.21 ---------------- 7.24 8.81 2.46 1.14 0.10 10 A A1 A2 b1 b c D E e1 y Note: 1. Dimension D Max & s include mold flash or tie bar burrs. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch and are determined at the mold parting line. 4. Controlling dimension : inch 5. General appearance spec. should be based on final visual inspection spec. Preliminary 10 March 1996 EtronTech Em51256C 11.80 0.10 0.465 0.004 0~8 0.006 +0.004 -0.002 8.00 0.315 #15 #14 0.15 +0.10 - 0.05 0.55 0.022 0.43 0.017 #28 8.40 MAX 0.331 #1 0.004MAX 0.10MAX 13.40 0.20 0.528 0.008 0.008 +0.004 -0.002 0.20 +0.10 - 0.05 28-pin 8 x 13.4mm TSOP 1 0.00 MIN 0.000 120 MAX 0.047 0.50 0.10 0.020 0.004 Preliminary 11 March 1996