Freescale Semiconductor Advance Information Document Number: MC34844 Rev. 9.0, 3/2012 10 Channel LED Backlight Driver with Integrated Power Supply The 34844/A is a high efficiency, LED driver for use in backlighting LCD displays from 10" to 20"+. Operating from supplies of 7.0 to 28 V, the MC34844/A is capable of driving up to 160 LEDs in 10 parallel strings. Current in the 10 strings is matched to within 2%, and can be programmed via the I2C/SM Bus interface. The 34844/A also includes a Pulse Width Monitor (PWM) generator for LED dimming. The LEDs can be dimmed to one of 256 levels, programmed through the I2C/SM Bus interface. Up to 65,000:1 (256:1 PWM, 256:1 Current DAC) dimming ratio. The integrated boost converter generates the minimum output voltage required to keep all LEDs illuminated with the selected current, providing the highest efficiency possible. The 34844 has an integrated boost self-clocks at a default frequency of 600 kHz, but may be programmed via I2C to 150/300/ 600/1200 kHz. The PWM frequency can be set from 100 Hz to 25 kHz, or can be synchronized to an external input. If not synchronized to another source, the internal PWM rate outputs on the CK pin. This enables multiple devices to be synchronized together. The 34844A has a default boost frequency of 320 kHz, but may be programmed via I2C to 160/320/650/1300 kHz. The PWM frequency can be set from 110 Hz to 27 kHz, or can be synchronized to an external input. If not synchronized to another source, the internal PWM rate outputs on the CK pin. This enables multiple devices to be synchronized together. The 34844/A also supports optical/temperature closed loop operation and also features LED over-temperature protection, LED short protection, and LED open circuit protection. The IC also includes over-voltage protection, over-current protection, and under-voltage lockout. 34844 34844A LED DRIVER EP SUFFIX (PB-FREE) 98ASA10800D 32-PIN QFN-EP ORDERING INFORMATION Device MC34844EP/R2 MC34844AEP/R2 Temperature Range (TA) Package -40 C to 105 C 32 QFN-EP Features * Input voltage of 7.0 to 28 V * 2.5 A integrated boost FET * Up to 50 mA on the 34844 LED current per channel * Up to 80 mA on the 34844A LED current per channel * 90% efficiency (DC:DC) * I2C/SM Bus interface * 10 channel current mirror with 2% current matching * Boost output voltage up to 60V, with Dynamic Headroom Control (DHC) * PWM frequency programmable or synchronizable from 100 to 25,000 Hz for the 34844 * PWM frequency programmable or synchronizable from 110 to 27,000 Hz for the 34844A * 32-Ld 5x5x1.0mm TQFN Package Applications * * * * Monitors and HDTV - up to 42 inch Personal Computer Notebooks GPS Screens Small screen Televisions * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2009-2012. All rights reserved. 34844 VIN VDC1 VDC2 7.0 to 28 V SWA SWB VOUT VDC3 PGNDA COMP PGNDB SLOPE Control Unit VDC1 VDC1 FAIL SCK SDA A0/SEN CK ISET PIN NIN ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 PWM M/~S EN VDC1 VCC GND Figure 1. MC34844 Simplified Application Diagram (SM Bus Mode) 34844A VIN 7.0 to 28V SWA SWB VDC1 VDC2 PWM PGNDA COMP PGNDB SLOPE Control Unit FAIL SCK SDA PWM PWM VOUT VDC1 A0/SEN CK M/~S EN VDC1 ISET PIN NIN VOUT VOUT VDC3 GND VCC ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 Figure 2. MC34844A Simplified Application Diagram (Manual Mode) 34844 2 Analog Integrated Circuit Device Data Freescale Semiconductor DEVICE VARIATIONS DEVICE VARIATIONS MC34844 is within the MC34844 Specifications Pages 4 to 31, MC34844A is within the MC34844A Specifications Pages 32 to 54 Table 1. Key Device Variations between the MC34844 and MC34844A Electrical Parameter(1) Condition Value Maximum LED Current mA 34844 55 34844A 85 LED Channel Sink Current (typ) 34844 RISET=5.1 k 0.1% 50 34844A RISET=3.48 k 0.1% 80 Switching Frequency 34844 34844A PWM Frequency Range 34844 Unit (typ) (BST [1:0]=0) 0.15 (BST [1:0]=1) 0.30 (BST [1:0]=2) [default] 0.60 (BST [1:0]=3) 1.20 (BST [1:0]=0) 0.16 (BST [1:0]=1)) [default] 0.32 (BST [1:0]=2) 0.65 (BST [1:0]=3) 1.30 This frequency range applies for Master mode, Slave mode, and Manual mode 34844A mA MHz Hz 100 - 25000 110 - 27000 Notes 1. Refer to the respective Electrical Parameters for specific details 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 3 MC34844 MC34844 SPECIFICATIONS PAGES 4 TO 31 MC34844 SPECIFICATIONS PAGES 4 TO 31 34844 4 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM SWA VIN VDC1 VDC2 SWB LDO A0/SEN OVP VDC3 PGNDA COMP SLOPE BOOST CONTROLLER PGNDB VOUT CK EN CLOCK/PLL V SENSE FAIL M/~S PWM I0 PWM GENERATOR I1 I2 SCK SDA I2C INTERFACE 10 CHANNEL 50 mA CURRENT MIRROR I3 I4 I5 I6 I7 I8 ISET CURRENT DAC PIN TEMP/OPTO LOOP CONTROL NIN I9 OCP/OTP/UVLO GND Figure 3. 34844 Simplified Internal Block Diagram 34844 5 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 PIN CONNECTIONS VOUT VDC2 M/~S COMP VDC1 SCK SDA PWM PIN CONNECTIONS 32 31 30 29 28 27 26 25 VIN 1 24 CK PGNDB 2 23 VDC3 TRANSPARENT TOP VIEW SWB 3 SWA 4 22 SLOPE 21 NIN QFN - EP 5.0 MM X 5.0 MM 32 LEAD PGNDA 5 20 PIN EP GND A0/SEN 6 19 ISET EN 7 18 FAIL IO 8 EP = Exposed Pad 17 I9 9 10 11 12 13 14 15 16 I1 I2 I3 I4 I5 I6 I7 I8 Figure 4. 34844 Pin Connections Table 2. 34844 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. Pin Number Pin Name Pin Function Formal Name Definition 1 VIN Power Input voltage 2 PGNDB Power Power Ground Power ground 3 SWB Input Switch node B Boost switch connection B 4 SWA Input Switch node A Boost switch connection A 5 PGNDA Power Power Ground Power ground 6 A0/SEN Input Device Select Address select, device select pin or OVP HW control 7 EN Input Enable 8 - 17 I0-I9 Input LED Channel 18 FAIL Open Drain Fault detection 19 ISET Passive Current set 20 PIN Input Positive current scale 21 NIN Input Negative current scale Negative input analog current control 22 SLOPE Passive Boost Slope 23 VDC3 Output Internal Regulator 3 24 CK Input/Output Clock signal Input supply Enable pin (active high, internal pull-up) LED string connections Fault detected pin (open drain): No Failure = Low-impedance Failure = High-impedance LED current setting resistor Positive input analog current control Boost slope compensation Setting resistor Decoupling capacitor for internal phase locked loop power Clock synchronization pin (input for M/~S = low - internal pull-up, output for M/~S = high) 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 6 MC34844 PIN CONNECTIONS Table 2. 34844 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. Pin Number Pin Name Pin Function Formal Name Definition 25 PWM Input External PWM 26 SDA Bidirectional I2C data I2C data Line 27 SCK Bidirectional I2C clock I2C clock line 28 VDC1 Output Internal Regulator 1 29 COMP Passive Compensation pin 30 M/~S Input Master/Slave selector Selects Master mode (1) or Slave mode (0) 31 VDC2 Output Internal Regulator 2 Decoupling capacitor for internal regulator 32 VOUT Input Voltage Output EP GND - Ground External PWM input (internal pull-down) Decoupling capacitor for internal logic rail Boost converter Type compensation pin Boost Output voltage sense pin Ground Reference for all internal circuits other than Boost FET 34844 7 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS Maximum Pin Voltages VMAX V A0/SEN 7.0 I0, I1, I2, I3, I4, I5, I6, I7, I8, I9,EN(5) 45 VIN 30 SWA, SWB, VOUT 65 FAIL, PIN, NIN, ISET, M/~S, CK, PWM 6.0 Maximum LED Current ESD IMAX Voltage(2) 55 VESD mA V Human Body Model (HBM) +2000 Machine Model (MM) +200 THERMAL RATINGS Ambient Temperature Range Junction to Ambient Temperature Junction to Case Temperature (3) (3) Maximum junction temperature Storage temperature range Peak Package Reflow Temperature During Reflow (4) TA -40 to 105 C TJA 32 C/W TJC 3.5 C/W TJ 150 C TSTO -40 to 150 C TPPRT 260 C Power Dissipation W TA = 25 C 3.9 TA = 70 C 2.5 TA = 85 C 2.0 TA = 105 C 1.4 Notes 2. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2), and the Machine Model (MM) (AEC-Q100003), RZAP = 0 3. 4. 5. Per JEDEC51 Standard for Multilayer PCB Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 45 V is the Maximum allowable voltage on all LED channels in off-state. 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 8 MC34844 ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Static and Dynamic Electrical Characteristics Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40 C TA 105 C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VIN 7.0 12 28 V Manual & SM Bus: EN = Low, SCK & SDA=Low - 2.0 - A I2C: EN = Low, SETI2C bit = 1, CLRI2C bit = 0 - 17 - ISLEEP - 3.0 - mA IOPERATIONAL - 10.0 - mA UVLO 5.4 6.0 6.4 V UVLOHYST 150 200 250 mV VDC1 2.4 2.5 2.6 V VDC2 5.5 6.0 6.5 V VDC3 2.4 2.5 2.6 V SUPPLY Supply Voltage Supply Current when Shutdown Mode Supply Current when Sleep Mode ISHUTDOWN SM-Bus: EN = low, SCK & SDA= Active, SETI2C bit = 0, EN bit = 0 I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 0 Supply Current when Operational Mode Manual: EN= High, SCK & SDA=Low, PWM=Low SM-Bus: EN= Low, SCK & SDA=Active, EN bit= 1, PWM=Low I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 1, PWM=Low Under-voltage Lockout VIN Rising Under-voltage Hysteresis VIN Falling VDC1 Voltage(6) CVDC1 = 2.2 F VDC2 Voltage(6) CVDC2 = 2.2 F VDC3 Voltage(6) CVDC3 = 2.2 F BOOST Output Voltage Range(7) V VIN = 7.0 V VOUT1 8.0 - 43 VIN = 28 V VOUT2 31 - 60 IFET 2.3 2.5 2.7 A RDSON - 250 500 m IBOOST_LEAK - - 10 A EFFBOOST - 90 - % Boost Switch Current Limit RDSON of Internal FET IDRAIN= 1.0 A Boost Switch Off-state Leakage Current VSWA,SWB = 65 V Peak Boost Efficiency(8) Notes 6. This output is for internal use only and not to be used for other purposes. A 1.0 k resistor between the VDC3 and VDC1 pin is recommended for <-20 C operation. 7. Minimum and Maximum output voltages are dependent on Min/Max duty cycle condition. 8. Guaranteed by design 34844 9 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Static and Dynamic Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40 C TA 105 C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit IOUT/VIN -0.2 - 0.2 %/V IOUT/VLED -0.2 - 0.2 %/V VSLOPE - 0.49 - V/s ACSA - 9.0 - Current Sense Resistor RSENSE - 22 - m OTA Transconductance GM - 200 - S Transconductance Sink and Source Current Capability ISS - 100 - A VHOLD 0.45 0.5 0.55 V IFAIL_LEAK - - 5 A VOL - - 0.4 V ISINK 49 50 51 mA VMIN 675 750 825 mV IMATCH -2.0 - 2.0 % VSET 2.017 2.048 2.079 V ILEDRES - 1.5 - % ICH_LEAK - - 10 A VPIN_DIS 2.2 - - V IPIN -2.0 - 2.0 A Line Regulation (9) VIN=7.0 to 28 V Load Regulation (9) VLED = 8.0 to 65 V (all Channels) Slope compensation voltage ramp RSLOPE = 68 k Current Sense Amplifier Gain Output Voltage Precharge FAIL PIN Off-state Leakage Current VFAIL = 5.5 V On-state Voltage Drop ISINK = 4.0 mA LED CHANNELS Sink Current ICHx Register = 255, RISET=5.1 k 0.1%, PIN&NIN = Disabled, TA=25 C Regulated minimum voltage across drivers Pulse Width > 4.0 s Current Matching Accuracy ISET Pin Voltage RISET=5.1 k 0.1% LED Current Amplitude Resolution 1.0 mA < ILED < 50 mA Off-state Leakage Current, All channels (VCH = 45 V) PIN INPUT Voltage to Disable PIN mode PIN Bias Current PIN = VSET Analog Dimming Current IDIM_PIN mA ICHx Register = 255, RISET=5.1 k 0.1% PIN = VSET/2 23.75 25 26.25 PIN = VSET 47.50 50 52.50 Notes 9. Guaranteed by design 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 10 MC34844 ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Static and Dynamic Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40 C TA 105 C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VNIN_DIS 2.2 - - V ININ -2.0 - 2.0 A NIN INPUT Voltage to Disable NIN mode NIN Bias Current NIN = VSET Analog Dimming Current IDIM_NIN mA ICHx Register = 255, RISET=5.1 k 0.1% NIN = VSET/2 23.75 25 26.25 NIN = 0 V 47.50 50 52.50 150 165 175 - 25 - OVER-TEMPERATURE PROTECTION Over-temperature Threshold(10) OTT Rising Hysteresis C 2 I C/SM BUS PHYSICAL LAYER [SCK, SDA] I2C Address ADRI2C - 1110110 - Binary SM-Bus Address ADRSMB - 1110110 - Binary Input Low Voltage VILI -0.3 - 0.8 V Input High Voltage VIHI 2.1 - 5.5 V Input Hysteresis VHYSI 0.3 - - V Output Low Voltage VOLI - - 0.4 V IINI -5.0 - 5.0 A CINI - - 10 F Input Low Voltage VILL -0.3 - 0.5 V Input High Voltage VIHL 1.5 - 5.5 V VHYSL - 0.1 - V IIIL -5.0 - 5.0 A VOLL - - 0.2 V VOHL 2.2 - 5.5 V CINI - - 5.0 F Sink Current < 4.0 mA Input Current Input Capacitance(10) LOGIC INPUTS / OUTPUTS (CK, M/~S, PWM, A0/SEN) Input Hysteresis Input Current Output Low Voltage (CK) ISINK < 2.0 mA Output High Voltage (CK) ISOURCE < 2.0 mA Input Capacitance(10) Notes 10. Guaranteed by design 34844 11 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Static and Dynamic Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40 C TA 105 C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit OVP = Fh OVPFH 60.5 62.5 64.5 V OVP = Eh OVPEH 56.5 58 60 V OVP = Dh OVPDH 53 54 56 V OVP = Ch OVPCH 49 51 52.5 V OVP = Bh OVPBH 45 47 48.5 V OVP = Ah OVPAH 41 43 44.5 V OVP = 9h OVP9H 38 39 40.5 V OVP = 8h OVP8H 34 36 37.5 V OVP = 7h OVP7H 30.5 32 33.5 V OVP = 6h OVP6H 26 28 30 V OVP = 5h OVP5H 23 24 25 V OVP = 4h OVP4H 19 20 21 V OVP = 3h OVP3H 15 16 17 V OVP = 2h OVP2H 11 12 13 V Over-voltage threshold, OVPHW 6.15 6.5 6.85 V ISINK_OVP - 100 - A Switching Frequency (BST [1:0]=0) fSW0 0.14 0.15 0.17 MHz Switching Frequency (BST [1:0]=1) fSW1 0.27 0.30 0.33 MHz Switching Frequency (BST [1:0]=2) fSW2 0.54 0.60 0.66 MHz Switching Frequency (BST [1:0]=3) fSW3 1.08 1.2 1.32 MHz Minimum Duty Cycle DMIN - 10 15 % Maximum Duty Cycle OVER-VOLTAGE PROTECTION Over-voltage Clamp - OVP Register Table: Set by Hardware, Voltage at A0/SEN A0/SEN Sink Current BOOST DMAX 80 85 - % Soft Start Period tSS - 6.5 - ms Boost Switch Rise Time(10) tTR - 15 - ns Boost Switch Fall Time(10) tF - 25 - ns Notes 11. Guaranteed by design 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 12 MC34844 ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Static and Dynamic Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40 C TA 105 C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit fPWMS 100 - 25000 Hz PWM GENERATOR PWM Frequency Range (13) M/~S = Low (Slave Mode) PWM Frequency fPWMM Hz M/~S = High (Master Mode) FPWM Register = 768 22500 25000 27500 90 100 110 tfPWM - 0.39 - % tPWM_IN 150 - - ns fPWM 100 - 23000 Hz fCKS 100 - 25000 Hz fCKS_JITTER - - 0.1 % FPWMS=25 kHz - - 50 ms FPWMS=100 Hz - 2000 - ms 22500 25000 27500 Hz 90 100 110 FPWM Register = 192,000 PWM dimming resolution PWM PIN (DIRECT PWM CONTROL) Input PWM Pin Minimum Pulse(13) Input PWM Frequency Range PHASE LOCK LOOP CK Slave Mode Frequency Lock Range(12) M/~S = Low (Slave Mode) CK Slave Mode Input Jitter(13) M/~S = Low (Slave Mode) Slave Mode Acquisition Time TS_ACQ M/~S = Low (Slave Mode) CK Frequency (Master Mode) fCKMASTER FPWM Register = 768 FPWM Register = 192,000 I2C/SM BUS PHYSICAL LAYER [SCK, SDA] Interface Frequency Range fSCK SM Bus Power-on-Reset Time tRST - tF Output fall time 400 kHz - 100 ms 40 - 160 ns tR 20 - 80 ns tR/tF - - 25 ns tR/tF - 23 50 ns 10 F < CL < 400 F Output rise time 10 F<CL<400 F LOGIC OUTPUT (CK) Output Rise and Fall time(12) CL<100 F LED CHANNELS Channels Rise and Fall Time(13) Notes 12. Special considerations should be made for frequencies between 100 Hz to 1.0 KHz. Please refer to Functional Device Operation for further details. 13. Guaranteed by design 34844 13 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION LED backlighting has become very popular for small and medium LCDs, due to some advantages over other backlighting schemes, such as the widely used cold cathode fluorescent lamp (CCFL). The advantages of LED backlighting are low cost, long life, immunity to vibration, low operational voltage, and precise control over its intensity. However, there is an important drawback of this method. It requires more power than most of the other methods, and this is a major problem if the LCD size is large enough. To address the power consumption problem, solid state optoelectronics technologies are evolving to create brighter LEDs with lower power consumption. These new technologies together with highly efficient power management LED drivers are turning LEDs, a more suitable solution for backlighting almost any size of LCD panel, with really conservative power consumption. One of the most common schemes for backlighting with LED is the one known as "Array backlighting". This creates a matrix of LEDs all over the LCD surface, using defraction and diffused layers to produce an homogenous and even light at the LCD surface. Each row or column is formed by a number of LEDs in series, forcing a single current to flow through all LEDs in each string. Using a current control driver, per row or column, helps the system to maintain a constant current flowing through each line, keeping a steady amount of light even with the presence of line or load variations. They can also be use as a light intensity control by increasing or decreasing the amount of current flowing through each LED string. To achieve enough voltage to drive a number of LEDs in series, a boost converter is implemented, to produce a higher voltage from a smaller one, which is typically used by the logical blocks to do their function. The 34844 implements a single channel boost converter together with 10 input channels, for driving up to 16 LEDs per string to create a matrix of more than 160 LEDs. Together with its 90% efficiency and I2C programmable or external current control, among other features, makes the 34844 a perfect solution for backlighting small and medium size LCD panels, on low power portable and high definition devices. FUNCTIONAL PIN DESCRIPTION INPUT VOLTAGE SUPPLY (VIN) IC ENABLE (EN) IC Power input supply voltage, is used internally to produce internal voltage regulation (VDC1, VDC3) for logic functioning, and also as an input voltage for the boost regulator. The active high enable pin is internally pulled high through pull-up resistors. Applying 0 V to this pin would stop the IC from working. INTERNAL VOLTAGE REGULATOR 1 (VDC1) This pin is for internal use only, and not to be used for other purposes. A capacitor of 2.2 F should be connected between this pin and ground for decoupling purposes. INTERNAL VOLTAGE REGULATOR 2 (VDC2) INPUT/OUTPUT CLOCK SIGNAL (CK) This pin can be used as an output clock signal (master mode), or input clock signal (slave mode), to synchronize more than one device. MASTER/SLAVE MODE SELECTION (M/~S) This pin is for internal use only, and not to be used for other purposes. A capacitor of 2.2 F should be connected between this pin and ground for decoupling purposes. Setting this pin High puts the device into Master mode, producing an output synchronization clock at the CK pin. Setting this pin low, puts the device in Slave mode, using the CK pin as an input clock. INTERNAL VOLTAGE REGULATOR 3 (VDC3) EXTERNAL PWM INPUT (PWM) This pin is for internal use only, and not to be used for other purposes. A capacitor of 2.2 F should be connected between this pin and ground for decoupling purposes. A 1.0 k resistor between the VDC3 and VDC1 pin is recommended for <-20 C operation. This pin is internally pulled down. An external PWM signal can be applied to modulate the LED channel directly in absence of an I2C interface. BOOST COMPENSATION PIN (COMP) Passive pin used to compensate the boost converter. Add a capacitor and a resistor in series to GND to stabilize the system. CLOCK I2C SIGNAL (SCK) Clock line for I2C communication. ADDRESS I2C SIGNAL (SDA) Address line for I2C communication. 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 14 MC34844 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION A0/SEN Address select, device select pin, or Hardware Overvoltage Protection (OVP) Control. CURRENT SET (ISET) Each LED string can drive up to 50 mA. The maximum current can be set by using a resistor from this pin to GND. POSITIVE CURRENT SCALING (PIN) Positive current scaling factor for the external analog current control. Applying 0 V to this pin, scales the current to near 0%, and in the same way, applying 2.048 V (Vset), the scale factor is 100%. By applying a voltage higher than 2.2 V, the scaling factor is disabled, and the internal pull-ups are activated. If PIN pin and NIN pin are used at the same time then by applying 0 V to the PIN pin and 2.048 V to NIN pin, scales the current to near 0%, and in the same way, applying 2.048 V to the PIN pin and 0 V to NIN pin, scales the current to 100%. By applying a voltage higher than 2.2 V, the scaling factor is disabled and the internal pull-ups are activated in both pins. NEGATIVE CURRENT SCALING (NIN) Negative current scaling factor for the external analog current control. Setting 0 V to this pin scales the current to 100%, in the same way, setting 2.048 V (Vset) the scale factor is near 0%. By applying a voltage higher than 2.2 V, the scaling factor is disabled and the internal pull-ups are activated. If PIN pin and NIN pin are used at the same time then by applying 0 V to the PIN pin and 2.048 V to NIN pin, scales the current near 0%, and in the same way, applying 2.048 V to the PIN pin and 0 V to NIN pin, scales the current to 100%. By applying a voltage higher than 2.2 V, the scaling factor is disabled and the internal pull-ups are activated in both pins. GROUND (GND) Ground Reference for all internal circuits other than the Boost FET. The Exposed Pad (EP) should be used for thermal heat dissipation. I0-I9 Current LED driver, each line has the capability of driving up to 50 mA. FAULT DETECTION PIN (FAIL) When a fault situation is detected, this pin goes into high impedance. BOOST SLOPE COMPENSATION SETTING RESISTOR (SLOPE) Use an external resistor of about 68 k to configure the Boost compensation slope. POWER GROUND PINS (PGNDA, PGNDB) Ground pin for the internal Boost FET. OUTPUT VOLTAGE SENSE PIN (VOUT) Input pin to monitor the output voltage. It also supplies the input voltage for the internal regulator 2 (VDC2). SWITCHING NODE PINS (SWA, SWB) Switching node of boost converter. 34844 15 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC34844 - Functional Block Diagram Regulators / Power Down Boost 3 Internal Regulators Protection / Failure Detection Over-temperature Protection Over-current Protection Under-voltage Protection Over-voltage Protection LED Open Protection LED Channels Logic Control Optical and Temperature Control PWM Dimming Serial Interface Control Regulator / Power down Protection / Failure Detection LED Channels Logic Control Boost Figure 5. Functional Internal Block Diagram REGULATORS/ POWER DOWN The 34844 is designed to operate from input voltages in the 7.0 to 28 V range. This is stepped down internally by LDOs to 2.5 V (VDC1 and VDC3) and 6 V (VDC3) for powering internal circuitry. If the input voltage falls below the UVLO threshold, the device automatically enters in power down mode. Operating Modes: The device can be operated by the EN pin and/or SDA/ SCK bus lines, resulting in three distinct operation modes: * Manual mode, there is no I2C capability, the bus line pins must be tied low, and the EN pin controls the ON/OFF operation. * SM Bus mode, EN pin must be tied low and the device is turned ON by any activity on the bus lines. The part shuts down if the bus lines are held low for more than 27 ms, the 27 ms watchdog timer can be disabled by I2C (setting SETI2C bit high) or tying the EN pin high. In Sleep mode (EN bit=0) the device reduces the power consumption by leaving "alive" only the blocks required for I2C communication. * I2C mode, has to be configured by I2C communication (SETI2C bit = 1) right after the IC is turned ON, it prevents the part from being turned ON/OFF by the bus. Sleep mode is also present and it is intended to save power, but still keep the IC prepared to communicate by I2C. Turning the EN pin OFF, the chip enters into a low power mode. 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 16 MC34844 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 5. Operation Current Consumption Modes Mode Manual SM Bus EN Pin SCK/SDA Pins I2C Bit Command Current Consumption Mode Low Low N/A Shutdown High Low N/A Operational Low Low (> 27 ms) EN bit = X Shutdown Low Active EN bit = 0 Sleep Low Active EN bit = 1 Operational Low X CLRI2C bit = 0 SETI2C bit = 1 I2C Low Power (Shutdown) Comments Part Doesn't Wake-up EN bit = X SETI2C bit = 1 I2 C High X CLRI2C bit = 0 Sleep EN bit = 0 SETI2C bit = 1 High X CLRI2C bit = 0 Operational EN bit = 1 BOOST HARDWARE OVP: The integrated boost converter operates in nonsynchronous mode and integrates a 2.5 A FET. An integrated sense circuit is used to sense the voltage at the LED current mirror inputs and automatically sets the boost output voltage (DHC) to the minimum voltage needed to keep all LEDs biased with the required current. The DHC is designed to operate under specific pulse width conditions in the LED drivers. It operates for pulse widths higher than 4.0 s If the pulse widths are shorter than specified, the DHC circuit will not operate and the voltage across the LED drivers will increase to a value given by the OVP minus the total LED voltage in the LED string. Therefore it is imperative to select the proper OVP level to minimize power dissipation. The OVP can be set from 11 to 62 V, ~4.0 V spaced, using the I2C interface (OVP Register). If I2C capability is not present, the OVP can be controlled by a resistor divider connected from VOUT to GND with its mid point tied to A0/ SEN pin (threshold = 6.5 V). During an OVP condition, the output voltage will go to the OVP level which is programmed via the I2C interface or settled by a resistor divider on A0/SEN pin, or by a zener diode. The formulas to calculate the hardware OVP using any of the two methods are as follows: The OVP value should be set to greater than the maximum LED voltage over the whole temperature range. A good practice is to set it 5.0 V or so above the max LED voltage. The boost converter also features internal Over-current Protection (OCP) and has a user programmable Overvoltage Protection (OVP). The OCP operates on a cycle by cycle basis. However, if the OCP condition remains for more than 10 ms then the device turns off the LED Drivers, the Boost goes to Sleep mode and the output FAULT pin goes into high-impedance. The device can only be restarted by recycling the enable or creating a Power On Reset (POR). The user can program the boost frequency by I2C (BST[1:0]) only after the IC is powered up and before the boost circuit is turned ON for the first time (PWM pin low to high). This sequence avoids boost frequency to be changed inadvertently during operation. The first I2C command has to wait for 5.0 ms after the part is turned ON, in order to allow sufficient time for the device power up sequence to be completed. The boost controller has an integral track and hold amplifier with indefinite hold time capability, to enable immediate LED on cycles after extended off times. During extended off times, the external LEDs cool down from their normal quiescent operating temperature and thereby experience a forward voltage change, typically an increase in the forward voltage. This change can be significant for applications with a large number of series LEDs in a string operating at high current. If the boost controller did not track this increased change, the potential on the LED drivers would saturate for a few cycles once the LED channels are reenabled. Method 1 Method 2 VOUT RUPPER A0/SEN RLOWER VZENER2 A0/SEN OVP = VZENER2 + 6.5 V OVP = 6.5 V [(RUPPER / RLOWER) + 1] + (100E-6 x RUPPER) 34844 17 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Also the device has a precharge voltage that add 0.5 Volts to the Boost, cycle by cycle of the PWM. It helps the boost to respond faster every time the load turns back on again. CURRENT MIRROR The programmable current mirror matches the current in 10 LED strings to within 2%. The maximum current is set using a resistor to GND from the ISET pin. This can be scaled down using the I2C interface to 255 levels. Zero current is achieved by turning off the LED Driver by I2C (registers CHENx = 0 h) for a duty cycle from 0% to 99% or by pulling PWM pin low regardless of the duty cycle. I2C capability allows the channels to be controlled individually or in parallel. Current on LED Channel (PIN and NIN mode disabled) Eqn. 1 ICH [ RegisterValue ] Current [ A ] = ----------------------------------------------------------RSET [ ohms ] In the off state, the LEDs current is set to 0 and the boost converter stops switching. This feature allows to drive more than 50 mA of current by connecting the LED string to 2 or more LED channels in parallel. For example; if the application requires to drive 5 channels at 100 mA, then the bottom of each LED string should be connected to two channels in order to duplicate the current capability (Example: CH0+CH1 = 100 mA). PWM GENERATOR The PWM generator can operate in either master or slave modes, as set by the M/~S pin. In master mode, the internal PWM generator frequency is programmed through the I2C interface (registers FPWM). The default programmed value set the number of 25 kHz clocks (40 s) in one PWM cycle. The 18-bit resolution allows minimum PWM frequencies of 100 Hz to be programmed. The resulting frequency is output on the CK pin. PWM Frequency Eqn. 2 19.2Mhz PWMFrequency [ Hz ] = -------------------------------------------------------------------FPWM [ RegisterValue ] In slave mode, the CK pin acts as an input. The internal digital PLL uses this frequency as the PWM frequency. By setting one device as master, and connecting the CK output to the input on a number of slave configured devices, all PWM frequencies are synchronized together. The duty cycle of the PWM waveform in both master and slave modes is set using a second register on the I2C interface (register DPWM), and can be controlled from 100% duty cycle to 1/256 TPWM = 0.39%. Zero percent of duty cycle is achieved by turning LED drivers off (register CHENx = 0h) or pulling PWM pin low. An external PWM can also be used. The PWM input is 'AND'ed with the internal signal. By setting the serial interface to 100% duty cycle (default), the external pin has full control of the PWM duty cycle. This pin can also be used to modulate the LED at a lower frequency than the PWM dimming frequency (Minimum pulse width = 150 ns). A pulsed mode can also be programmed using the I2C interface (STROBE bit = 1). In this mode, each rising edge of the PWM signal turns on the next channel, while turning off all other channels. The duration that the channel is illuminated is set by the duty cycle of the PWM input pin. This can be used to scan the output channels. DISABLING LED CHANNELS The 34844 allows the user to enable and disable each of the 10 channels separately by writing the corresponding CHENx bit on Registers 08 and 09 thru I2C. When a channel is disabled thru the I2C prior the device starts to operate, the corresponding LED driver is disabled but the feedback circuit is still connected. This may interfere with the operation of the dynamic headroom control (DHC) which can lead to erratic output voltage regulation. For this condition, the output voltage may ramp up to the OVP level if the voltage on the LED driver is not substantially above the DHC regulation voltage (0.75 V typ). Because of this operation under I2C/SMBUS Mode, we recommend to connect the unused channels to VDC2 thru a100 kohm resistor and also follow the below powering up sequence: 1. PWM pin = Low. 2. Power up the part. 3. Program the I2C commands and disable the unused channels. 4. Enable the Boost and current drivers by taking PWM pin to HIGH. This previous device's operation does not happen when all channels are being used because the voltage across the LED drivers is always equal or higher than the DHC regulation voltage (0.75 V typ). For this condition, the user can disable/ enable any of the channels thru I2C without causing any erratic behavior but the FAIL pin cannot be cleared. If FAIL pin is to be cleared thru I2C, it will be necessary to use the suggested configuration shown at the FAIL PIN session. FAIL PIN If a LED fails open in any of the LED strings, the voltage in that particular LED channel will be close to ground and the LED open failure is detected. When this happens, a failure is registered, the FAIL pin is set to its high-impedance stage, and the channel is turned off. The FAIL pin cannot be cleared for manual mode unless a complete power on reset is applied. However for I2C/SMBUS mode, the FAIL pin is cleared by disabling the malfunction channels (CHENx = 0) and clearing the failure bit (CLRFAIL bit = 1). If the application only requires clearing the failure for the floating or unused channels, then the unused channels must be connected to VDC2 thru a 100 kohm resistor to avoid reach instability problems. This will allow detecting another failure from the connected channels. (See Figure 6) 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 18 MC34844 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION If I2C communication is not present, FAIL condition should be reset by removing the failure and re-enabling the device thru the EN pin. OPTICAL AND TEMPERATURE CONTROL LOOP The 34844 supports both optical and temperature loop control. Figure 6. Single Channel Disconnect Circuit. For applications where multiple failure detection is required, then one 100 kohm resistor must be placed from each channel to a diode (D2) connected to VDC2. The resistor will provide a pull up voltage to the disconnected channels so that they do not interfere with the DHC circuit. The diode (D2) ensures that when the connected channels are in PWM off state the LED strings do no conduct current to VDC2. (See Figure 7) For temperature loop control, the LED brightness can be adjusted depending on the temperature of the LEDs. For optical loop control, the 34844 supports both optical closed loop backlight control, where the brightness of the backlight is maintained at a required level by adjusting the light output, until the desired level is achieved, or with ambient light control, where the backlight brightness increases as ambient light increases. Both temperature and optical loops are supported through the PIN and NIN pins. Each pin supports a 0-2.048 V input range which affects the current through the LEDs. The PIN pin increases current as the voltage rises from 0-2.048 V. The NIN pin reduces current as the voltage rises from 02.048 V. A 10.2 k resistor or higher value must be used at the ISET pin if the part is configured to use PIN+NIN control loop functionality, the 50 mA maximum current is achieved at the higher allowed level of PIN/NIN pins, ensuring the maximum current of the LED Drivers are not exceeded. The optical and temperature control loop can be disabled by I2C setting bits (PINEN & NINEN), or by tying PIN and NIN pins high (>2.2 V) it is called VSET mode, and the LED Driver maximum current is set to 50 mA by using a 5.1 k resistor at the ISET pin. Current on LED Channel (PIN mode) Eqn. 3 ( VPIN x ICH [ RegisterValue ] ) Current [ A ] = ---------------------------------------------------------------------------------------RSET [ ohms ] x 2 Current on LED Channel (NIN mode) Eqn. 4 ( 2.048 - VNIN ) x ICH [ RegisterValue ] Current [ A ] = ------------------------------------------------------------------------------------------------------------RSET [ ohms ] x 2 Current on LED Channel (PIN+NIN mode) Eqn. 5 ( 2.048 - VNIN + VPIN ) x ICH [ RegisterValue ] Current [ A ] = ----------------------------------------------------------------------------------------------------------------------------------RSET [ ohms ] x 2 LED FAILURE PROTECTION Figure 7. Resistor/Diode placement for multiple open circuit detection If the fail pin cannot be cleared by software then it indicates that the failure is because of t an over-current in the Boost. Since this is a critical failure the only way to clear it is by releasing the part from the over-current condition and then shutdown the part (Refer to Table 5) Open LED Protection If LED fails open in any of the LED strings, the voltage in that channel will be pulled close to zero, which will cause the channel to be disabled. As a result, the boost output voltage will go to the OVP level and then come down to the regulation level to continue powering the rest of the LED strings. Short LED Protection If an LED shorted in any of the LED strings, the device will continue to operate without interruption. However, if the 34844 19 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION shorted LED happens to be in the LED string with the highest forward voltage, the DHC circuit will automatically regulate the output voltage with respect to the new highest LED voltage. If more LEDs are shorted in the same LED string, it may cause excessive power dissipation in the channel which may cause the OTT circuit to trip which will completely shutdown the device. OVER-TEMPERATURE PROTECTION The 34844 has an on-chip temperature sensor that measures die temperature. If the IC temperature exceeds the OTT threshold, the IC will turn off all power sources inside the IC (LED drivers, boost and internal regulators) until the temperature falls below the falling OTT threshold. Once it comes back on, it will operate with the default configuration (refer to Table 7). SERIAL INTERFACE CONTROL The 34844 uses an I2C interface capable of operating in standard (100 kHz) or fast (400 kHz) modes. The A0/SEN pin can be used an address select pin to allow more than 2 devices in the system. The A0/SEN pin should be held low on all chips expect the one to be addressed, where it is taken HIGH. 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 20 MC34844 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES NORMAL MODE I 2C In normal operation the 34844 is programed via to drive up to 50 mA of current through each one of the LED channels. The 34844 can be configured in master or slave mode as set by the M/~S pin. In Master mode, the internal PWM generator frequency is programmed through the I2C interface. The programmed value sets the number of 25 kHz clocks (40s) in one PWM cycle. The 18-bit resolution allows minimum PWM frequencies of 100 Hz to be programmed. The resulting frequency is output on the CK pin. In slave mode, the CK pin acts as an input. The internal digital PLL uses this frequency as the PWM frequency. By setting one device as a master, and connecting the CK output to the input on a number of slave configured devices, all PWM frequencies are synchronized together. For this application A0/SEN pin indicates which device is enable for I2C control. In Slave mode, an internal phase lock loop will lock the internal PWM generator period to the period of the signal present at the CK pin. The PLL can lock to any frequency from 100 Hz to 25 KHz provided the jitter is below 1000 ppm. At frequencies above 1.0 KHz, the PLL will maintain lock regardless of the transient power conditions imposed by the user (i.e. going from 0% duty cycle to 100% at 20W LED display power). Below 1.0 kHz, thermal time constants on the die are such that the PLL may momentarily lose lock if the die temperature changes substantially during a large load power step. As explained below, this anomaly can be avoided by controlling the rate of change in PWM duty cycle. To better understand this issue, consider that the on chip PLL uses a VCO that is subject to thermal drift on the order of 1000 ppm/C. Further consider that the thermal time constant of the chip is on the order of single digit milliseconds. Therefore, if a large power load step is imposed by the user (i.e. going from 0% duty cycle to 100% duty cycle with a load power of 20 W), the die will experience a large temperature wave gradient that will propagate across the chip surface and thereby affect the instantaneous frequency of the VCO. As long as such changes are within the bandwidth of the PLL, the PLL will be able to track and maintain lock. Exceeding this rate of change may cause the PLL to lose lock and the backlight will momentarily be blanked until lock is reacquired. At 100 Hz lock, the PLL has a bandwidth of approximately 10 Hz. This means that temperature changes on the order of 100 ms are tolerable without losing lock. But full load power changes on the order of 10 ms (i.e. 100 Hz PWM) are not tracked out and the PLL can momentarily lose lock. If this happens, as stated above, the LED drivers are momentarily disabled until lock is reacquired. This will be manifested as a perceivable short flash on the backlight immediately after the load change. To avoid this problem, one can simply limit large instantaneous changes in die temperature by invoking only small power steps when raising or lowering the display power at low PWM frequencies. For example, to maintain lock while transitioning from 0% to 100% duty cycle at 20 W load power and a PWM frequency of 100 Hz would entail stepping the power at a rate not to exceed 1% per 10 ms. If a load of less than 20 W is used, then the rate of rise can be increased. As the locked PWM frequency increases (i.e. use 600 Hz instead of 100 Hz), the step rate can be further increased to approximately 4% per 2.0 ms. The exact step rate to avoid loss of PLL lock is a function of essentially three things: (a) the composite thermal resistance of the user's PCB assembly, (b) the load power, and (c) the PWM frequency. For all cases below 1.0 KHz, simply using a rate of 1% duty cycle change per PWM period will be adequate. If this is too slow, the value can be optimized experimentally once the hardware design is complete. At PWM rates above 1.0 KHz, it is not necessary to control the rate of change in PWM duty cycle. It is important to point out that when operating in the master mode, one does not need to concern themselves with loss of lock since the reference clock and the VCO clock are collocated on the die, and therefore experience the same thermal shift. Hence in master mode, once lock is initially acquired, it is not lost and no blanking of the display occurs. The duty cycle of the PWM in both master and slave mode is set using a second register on the I2C interface. An external PWM signal can also be applied in the PWM pin. This pin is AND'ed with the internal signal, giving the ability to control the duty cycle either via I2C or externally by setting any of the 2 signals to 100% duty cycle. STROBE MODE A strobe mode can be programmed via I2C. In this mode, each rising edge of the PWM signal turns on the next channel, while turning off all other channels. The duration that the channel is illuminated is set by the duty cycle of the PWM input pin. This mode can be also programmed by controlling the ON and OFF state of each LED channel via I2C. MANUAL MODE The 34844 can also be used in Manual mode without using the I2C interface. By setting the pin M/~S High, the LED dimming will be controlled by the external PWM signal. The over-voltage protection limit can be settled by a resistor divider on A0/SEN pin. 34844 21 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 FUNCTIONAL DEVICE OPERATION I2C BUS SPECIFICATION During manual mode, all internal Registers are in Default Configuration, refer Table 7, under this configuration the PIN and NIN pins are enabled to scale the current capability per string and may be disable by setting 2.2 V in the corresponding pin. Also in this mode, the device can be enabled as follows: + EN pin + PWM signal (Two Signals): In this configuration, the PWM signal applied to PWM pin will be in charge of controlling the LED dimming and a second signal will enable or disable the chip through the EN pin. Figure 21 + PWM Signal tied to SDA pin (Just ONE signal): In this configuration the PWM pin should be tied to SDA pin. The PWM signal applied to PWM pin will be in charge of controlling LED dimming and enable the device every time the PWM is active. For this configuration EN pin should be LOW. POWER DOWN MODE If the input voltage falls below the UVLO threshold, the device enters automatically into power down mode. When in power down, the supply current is reduced below 2.0 A when there is no I2C activity, and it rises up when I2C interface is enabled. I2C BUS SPECIFICATION The 34844 is a unidirectional device that can only be written by an external control unit. Since the device is a 7 bit address device (1110110), the control unit needs to follow a specific data transfer format which is shown in Figure 8. Figure 8. A Complete Data Transfer For a complete data transfer, please use this format in the The receiver (34844) must pull down the SDA line during following order: this acknowledge pulse to indicate that the data was correctly written. 1. START condition * Bits in the first byte: The first seven bits of the first bite 2. The 34844 device address and Write instruction make up the slave address. The eighth bit is the LSB (least (R/W = 0) significant bit), which determines the direction of the 3. First data pack, it corresponds to the 34844 Register message (Write = 0) that needs to be written. (refer to Table ) For the 34844 device, when an address is sent, each of the 4. Second data pack, it corresponds to the value that devices in a system compares the first seven bits after the should be written to that register. (refer to Table ) START condition with its address. If they match, the device considers itself addressed by the control unit as a 5. STOP condition slave-receiver. I2C variables description: * STOP: this condition occurs when SDA changes from LOW to HIGH while SCK is HIGH * START: this condition occurs when SDA changes from HIGH to LOW while SCK is HIGH. For more information about "I2C BUS SPECIFICATION" please refer to the following link: * ACKNOWLEDGE: The acknowledge clock pulse is generated by the Master (Control Unit). http://www.nxp.com/acrobat_download/literature/ * The transmitter releases the SDA line (HIGH) during the 9398/39340011.pdf acknowledge clock pulse. 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 22 MC34844 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS Table 6. Write Registers reg / db 00 D7 D6 OVP3 OVP2 D5 OVP1 D4 D3 OVP0 D2 D1 NINEN PINEN EN CLRI2C SETI2C 01 D0 04 FPWM5 FPWM4 FPWM3 FPWM2 FPWM1 FPWM0 05 FPWM11 FPWM10 FPWM9 FPWM8 FPWM7 FPWM6 06 FPWM17 FPWM16 FPWM15 FPWM14 FPWM13 FPWM12 DPWM5 DPWM4 DPWM3 DPWM2 DPWM1 DPWM0 CHEN4 CHEN3 CHEN2 CHEN1 CHEN0 CHEN9 CHEN8 CHEN7 CHEN6 CHEN5 BST1 BST0 07 DPWM7 DPWM6 08 09 STRB CLRFAIL ALL_OFF 14 F0 ICH0_7 ICH0_6 ICH0_5 ICH0_4 ICH0_3 ICH0_2 ICH0_1 ICH0_0 F1 ICH1_7 ICH1_6 ICH1_5 ICH1_4 ICH1_3 ICH1_2 ICH1_1 ICH1_0 F2 ICH2_7 ICH2_6 ICH2_5 ICH2_4 ICH2_3 ICH2_2 ICH2_1 ICH2_0 F3 ICH3_7 ICH3_6 ICH3_5 ICH3_4 ICHG_3 ICH3_2 ICH3_1 ICH3_0 F4 ICH4_7 ICH4_6 ICH4_5 ICH4_4 ICH4_3 ICH4_2 ICH4_1 ICH4_0 F5 ICH5_7 ICH5_6 ICH5_5 ICH5_4 ICH5_3 ICH5_2 ICH5_1 ICH5_0 F6 ICH6_7 ICH6_6 ICH6_5 ICH6_4 ICH6_3 ICH6_2 ICH6_1 ICH6_0 F7 ICH7_7 ICH7_6 ICH7_5 ICH7_4 ICH7_3 ICH7_2 ICH7_1 ICH7_0 F8 ICH8_7 ICH8_6 ICH8_5 ICH8_4 ICH8_3 ICH8_2 ICH8_1 ICH8_0 F9 ICH9_7 ICH9_6 ICH9_5 ICH9_4 ICH9_3 ICH9_2 ICH9_1 ICH9_0 FA ICHG_7 ICHG_6 ICHG_5 ICHG_4 ICHG_3 ICHG_2 ICHG_1 ICHG_0 Table 7. Register Description Register Name Default Value (Hex) EN 1 Chip Enable by software. This signal is `OR'ed with external EN (0=off, 1 =on) PINEN 1 PIN pin enable (0=off, 1 =on) NINEN 1 NIN pin enable (0=off, 1 =on) OVP[3:0] F OVP voltage SETI2C 0 SET I2C communication (Disable SM Bus Mode) CLRI2C 0 Clear set I2C FPWM[17:0] 300 PWM Frequency DPWM[7:0] FF PWM Duty Cycle (FFh =100%) CHEN[9:0] 3FF Channel Enable (0=off, 1=on) ALL_OFF 0 All 10 channels OFF at the same. In order to reactivate channels this bit should be clear. CLRFAIL 0 Clear fail if channels are re-enable. STRB 0 Strobe MODE (0=Parallel, 1=Strobe) Description 34844 23 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 7. Register Description Register Name Default Value (Hex) BST[1:0] 2 ICH#[7:0] FF Channel Current Program (FFh = Maximum Current) ICHG[7:0] FF Global Current Program Description Boost Frequency (150,300,600,1200 kHz) [0h=150 Hz] Table 8. Over-voltage Protection REGISTER (HEX) OVP VALUE (VOLTS) 2 11 3 15 4 19 5 23 6 27 7 31 8 35 9 39 A 43 B 47 C 51 D 55 E 59 F 62 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 24 MC34844 FUNCTIONAL DEVICE OPERATION TYPICAL PERFORMANCE CURVES (TA=25C) TYPICAL PERFORMANCE CURVES (TA=25C) 95% 94% 93% Efficiency (%) 92% 91% 90% Fs = 600KHz L=22uH, DCR=52mO Schottky V12P10-E3/86A COUT = 2x4.7F, 2x2.2F/100V FPWM=600Hz, 100% duty Load = 16 LEDs, 50mA/channel VLED = 48V, 1V /channel 89% 88% 87% 86% 85% 10 12 14 16 18 20 22 24 26 28 30 Vin, volts Figure 9. Boost efficiency vs Input Voltage 50.50 ILED (highest VLED channel), mA 50.45 Fs = 600KHz L=22uH, DCR=52mO Schottky V12P10-E3/86A COUT = 2x4.7F, 2x2.2F/100V FPWM=600Hz, 100% duty Load = 16 LEDs, 50mA/channel V LED = 48V, 1V /channel 50.40 50.35 50.30 50.25 50.20 50.15 50.10 50.05 50.00 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vin, volts Figure 10. Line Regulation, VIN Changing 34844 25 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 FUNCTIONAL DEVICE OPERATION TYPICAL PERFORMANCE CURVES (TA=25C) 50.0 45.0 50.01 mA LED Current, mA 40.0 37.59 mA 35.0 30.0 25.0 25.03 mA 20.0 15.0 12.46 mA 10.0 FPWM=25KHz 5.0 0.0 0.4% 0.14 mA 25.0% 50.0% 75.0% 99.6% PWM Duty Cycle (%) Figure 11. PWM Dimming Linearity 10.10 10.08 10.06 Bias Current, mA 10.04 10.02 10.00 9.98 9.96 9.94 I2C Mode SM_Bus Mode Manual Mode 9.92 9.90 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vin, volts Figure 12. Bias Current vs Input Voltage (Operational Mode) 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 26 MC34844 FUNCTIONAL DEVICE OPERATION TYPICAL PERFORMANCE CURVES (TA=25C) 3.12 3.10 Bias Current, mA 3.08 3.06 3.04 3.02 I2C Mode 3.00 SM_Bus Mode 2.98 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vin, volts Figure 13. Bias Current vs Input Voltage (Sleep Mode) COMP Vin=24V Load=16 LEDs, 50mA/channel VLED = 47V, 1V VOUT INDUCTOR CURRENT Figure 14. Boost Soft Start 34844 27 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 FUNCTIONAL DEVICE OPERATION TYPICAL PERFORMANCE CURVES (TA=25C) ILED, CH1 ISET=40mA (all channels) FPWM=600Hz, 40% duty VCH1 VOUT (ac coupled) Precharge INDUCTOR CURRENT Figure 15. Typical Operation Waveforms for FPWM=600 Hz, 40% Duty SWA SWB INDUCTOR CURRENT VOUT (ac coupled) ILED, CH1 ISET=50mA (all channels) FPWM=600Hz, 100% duty Figure 16. Typical Operation Waveforms for FPWM=600 Hz, 100% Duty 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 28 MC34844 FUNCTIONAL DEVICE OPERATION TYPICAL PERFORMANCE CURVES (TA=25C) VCh1 ISET = 20mA, FPWM=20KHz, Duty=0.78% (2LSB) ILED1 Figure 17. Low Duty Dimming Operation Waveforms (FPWM=20 kHz, 2LSB) VCh1 ISET = 20mA, FPWM=20KHz, Duty=0.39% (1LSB) ILED1 Figure 18. Low Duty Dimming Operation Waveforms (FPWM=20 kHz, 1LSB) 34844 29 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844 TYPICAL APPLICATIONS TYPICAL APPLICATIONS MANUAL MODE (Single Wire Control) 22uH VIN = 24V 1 2 VOUT U1 1.0K 47uF 1 + 2.2uF 2.2uF 2.2uF 0 56pF 0 5.6K 309K 1.8nF 0 0 CLK VOUT 0 150K OVP = 55V 20K VDC1 5.1K VDC1 VDC1 VDC2 VDC3 29 22 COMP SLOPE 32 PGNDA PGNDB CK EN 25 PWM 27 26 SCK SDA 6 30 A0/SEN M/~S 19 ISET 20 21 PIN NIN 0 VOUT VIN 28 31 23 Master CK Output 24 7 SWA SWB 4 3 2 D1 1 LED MATRIX (16S10P) 13.8uF + 5 2 FAIL 18 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 8 9 10 11 12 13 14 15 16 17 GND 33 VCC 3.3K 0 34844 0 Figure 19. Manual Mode (Single Wire Control) MANUAL MODE (Two Wire Control) 22uH VIN = 24V 1 2 VOUT U2 1.0K 47uF 1 + 2.2uF 2.2uF 0 2.2uF 56pF 0 Control 5.6K 309K 1.8nF 0 EN PWM Unit VOUT 150K 0 OVP = 55V 20K VDC1 5.1K VDC1 0 VDC1 VDC2 VDC3 29 22 COMP SLOPE Master CK Output 24 7 0 VIN 28 31 23 PWM 27 26 SCK SDA 6 30 A0/SEN M/~S 19 ISET 20 21 PIN NIN VOUT 32 PGNDA PGNDB CK EN 25 SWA SWB 4 3 34844 2 D5 1 LED MATRIX (16S10P) 13.8uF + 5 2 FAIL 18 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 8 9 10 11 12 13 14 15 16 17 GND 33 VCC 3.3K 0 0 Figure 20. Manual Mode (Two Wire Control) 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 30 MC34844 TYPICAL APPLICATIONS 22uH VIN = 24V 1 2 VOUT U3 1.0K 47uF 1 + 2.2uF 2.2uF 0 2.2uF 56pF 0 5.6K 309K 1.8nF Master CK 0 0 Control VDC1 0 SCK SDA Unit VDC1 5.1K VDC1 VIN 28 31 23 VDC1 VDC2 VDC3 29 22 COMP SLOPE 24 7 CK EN 25 PWM 27 26 SCK SDA 6 30 A0/SEN M/~S 19 ISET 20 21 PIN NIN 0 SWA SWB 4 3 VOUT 32 D8 2 1 LED MATRIX (16S10P) 13.8uF + 5 2 PGNDA PGNDB FAIL 18 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 8 9 10 11 12 13 14 15 16 17 GND 33 VCC 3.3K 0 34844 0 Figure 21. SM Bus Mode MASTER - SLAVE Connection 22uH VIN = 24V 1 2 VOUT U4 1.0K 47uF 1 2.2uF 2.2uF 0 2.2uF 5.6K 56pF VDC1 VDC2 VDC3 29 22 COMP SLOPE 24 7 CK EN 25 PWM 27 26 SCK SDA VDC1 6 30 A0/SEN M/~S 5.1K 19 ISET 20 21 PIN NIN 309K 1.8nF 0 0 0 Master CK VDC1 VDC1 0 SWA SWB 4 3 VOUT 32 VIN 28 31 23 + PGNDA PGNDB 2 D1 1 LED MATRIX (16S10P) 13.8uF + 5 2 FAIL 18 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 8 9 10 11 12 13 14 15 16 17 GND 33 VCC 3.3K 0 34844 0 A0/SEN (Master) A0/SEN (Slave) MASTER Device Control Unit SDA SCK SLAVE Device VIN = 24V 1 22uH 2 VOUT U5 1.0K 47uF 1 2.2uF 0 2.2uF 2.2uF 0 56pF 5.6K VDC1 VDC2 VDC3 29 22 COMP SLOPE Master CK 24 7 CK EN VDC1 25 PWM 27 26 SCK SDA 6 30 A0/SEN M/~S 19 ISET 20 21 PIN NIN 309K 1.8nF 0 0 Input 5.1K VDC1 0 VIN 28 31 23 + SWA SWB 4 3 VOUT 32 PGNDA PGNDB 34844 2 D2 1 LED MATRIX (16S10P) 13.8uF + 5 2 FAIL 18 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 8 9 10 11 12 13 14 15 16 17 GND 33 VCC 3.3K 0 0 Figure 22. Master - Slave Connection 34844 31 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A MC34844A SPECIFICATIONS PAGES 32 TO 54 MC34844A SPECIFICATIONS PAGES 32 TO 54 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 32 MC34844A INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM SWA VIN SWB VDC1 LDO VDC2 A0/SEN OVP VDC3 PGNDA COMP BOOST CONTROLLER SLOPE PGNDB VOUT CK CLOCK/PLL EN V SENSE FAIL M/~S PWM I0 PWM GENERATOR I1 I2 SCK SDA I2C INTERFACE 10 CHANNEL 80 mA CURRENT MIRROR I3 I4 I5 I6 I7 I8 ISET CURRENT DAC PIN TEMP/OPTO LOOP CONTROL NIN I9 OCP/OTP/UVLO GND Figure 23. 34844A Simplified Internal Block Diagram 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 33 MC34844A PIN CONNECTIONS VOUT VDC2 M/~S COMP VDC1 SCK SDA PWM PIN CONNECTIONS 32 31 30 29 28 27 26 25 VIN 1 24 CK PGNDB 2 23 VDC3 TRANSPARENT TOP VIEW SWB 3 SWA 4 22 SLOPE 21 NIN QFN - EP 5MM X 5MM 32 LEAD PGNDA 5 20 PIN EP GND A0/SEN 6 19 ISET EN 7 18 FAIL IO 8 EP = Exposed Pad 17 I9 9 10 11 12 13 14 15 16 I1 I2 I3 I4 I5 I6 I7 I8 Figure 24. 34844A Pin Connections Table 9. 34844A Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 42. Pin Number Pin Name Pin Function Formal Name Definition 1 VIN Power Input voltage 2 PGNDB Power Power Ground Power ground 3 SWB Input Switch node B Boost switch connection B 4 SWA Input Switch node A Boost switch connection A 5 PGNDA Power Power Ground Power ground 6 A0/SEN Input Device Select Address select, device select pin or OVP HW control 7 EN Input Enable 8 - 17 I0-I9 Input LED Channel 18 FAIL Open Drain Fault detection 19 ISET Passive Current set 20 PIN Input Positive current scale 21 NIN Input Negative current scale Negative input analog current control 22 SLOPE Passive Boost Slope 23 VDC3 Output Internal Regulator 3 24 CK Input/Output Clock signal 25 PWM Input External PWM Input supply Enable pin (active high, internal pull-up) LED string connections Fault detected pin (open drain): No Failure = Low-impedance Failure = High-impedance LED current setting resistor Positive input analog current control Boost slope compensation Setting resistor Decoupling capacitor for internal phase locked loop power Clock synchronization pin (input for M/~S = low - internal pull-up, output for M/~S = high) External PWM input (internal pull-down) 34844A 34 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A PIN CONNECTIONS Table 9. 34844A Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 42. Pin Number Pin Name Pin Function Formal Name Definition 26 SDA Bidirectional I2C data I2C data Line 27 SCK Bidirectional I2C clock I2C clock line 28 VDC1 Output Internal Regulator 1 29 COMP Passive Compensation pin 30 M/~S Input Master/Slave selector Selects Master mode (1) or Slave mode (0) 31 VDC2 Output Internal Regulator 2 Decoupling capacitor for internal regulator 32 VOUT Input Voltage Output EP GND - Ground Decoupling capacitor for internal logic rail Boost converter Type compensation pin Boost Output voltage sense pin Ground Reference for all internal circuits other than Boost FET 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 35 MC34844A ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 10. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS Maximum Pin Voltages VMAX V A0/SEN 7.0 I0, I1, I2, I3, I4, I5, I6, I7, I8, I9(17) EN, VIN 45 30 SWA, SWB, VOUT 65 FAIL, PIN, NIN, ISET, M/~S, CK, PWM 6.0 Maximum LED Current ESD Voltage (14) IMAX 85 VESD mA V Human Body Model (HBM) +2000 Machine Model (MM) +200 THERMAL RATINGS Ambient Temperature Range TA -40 to 105 C Junction to Ambient Temperature(15) TJA 32 C/W Junction to Case Temperature(15) TJC 3.5 C/W TJ 150 C Storage temperature range TSTO -40 to 150 C Peak Package Reflow Temperature During Reflow(16) TPPRT 260 C Maximum junction temperature Power Dissipation W TA = 25C 3.9 TA = 70C 2.5 TA = 85C 2.0 TA = 105C 1.4 Notes 14. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2), and the Machine Model (MM) (AEC-Q100003), RZAP = 0 15. 16. 17. Per JEDEC51 Standard for Multilayer PCB Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 45 V is the Maximum allowable voltage on all LED channels in off-state. 34844A 36 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 11. Static and Dynamic Electrical Characteristics Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, -40C TA 105C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VIN 7.0 12 28 V SUPPLY Supply Voltage(20) Supply Current when Shutdown Mode A ISHUTDOWN Manual: PWM = Low, EN = Low, SCK & SDA=Low - 2.0 17 - - 4.0 - mA - 13.0 - mA UVLO 5.4 6.0 6.4 V UVLOHYST - 300 - mV VDC1 2.3 2.5 2.75 V VDC2 5.5 6.0 6.5 V VDC3 2.3 2.5 2.75 V VIN = 7.0 V VOUT1 8.0 - 28 V VIN = 28 V VOUT2 32 - 60 IFET 2.3 2.5 2.7 A tBOOST_TIME - 10 - ms RDSON of Internal FET (IDRAIN= 1.0 A) RDSON - 250 500 m Boost Switch Off-state Leakage Current IBOOST_LEAK - - 10 A Feedback pin Off-state Leakage Current (VOUT = 65 V ) VOUTLEAK - 500 700 A Peak Boost Efficiency(20) EFFBOOST - 90 - % SM Bus: EN bit = 0, SCK & SDA=Low, EN pin= Low I2C: SETI2Cbit=1, CLRI2C=0, EN bit= 0, EN pin = Low Supply Current when Sleep Mode ISLEEP SM-Bus: EN = low, SCK & SDA= Active, SETI2C bit = 0, EN bit = 0 I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 0 Supply Current when Operational Mode IOPERATIONAL Manual: EN= High, SCK & SDA=Low, PWM=Low SM-Bus: EN= Low, SCK & SDA=Active, EN bit= 1, PWM=Low I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 1, PWM=Low Under-voltage Lockout (VIN Rising) Under-voltage Hysteresis (VIN Falling) VDC1 Voltage (18) CVDC1 = 2.2 F VDC2 Voltage(18) CVDC2 = 2.2 F VDC3 Voltage(18) CVDC3 = 2.2 F BOOST Output Voltage Range(19)(20) Boost Switch Current Limit Boost Switch Current Limit Timeout VSWA,SWB = 65 V Notes 18. This output is for internal use only and not to be used for other purposes. A 1.0 k resistor between the VDC3 and VDC1 pin is recommended for <-20 C operation. 19. Minimum and Maximum output voltages are dependent on Min/Max duty cycle and current limit condition. 20. Guaranteed by design 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 37 MC34844A ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 11. Static and Dynamic Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, -40C TA 105C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit IOUT/VIN -0.2 - 0.2 %/V IOUT/VLED -0.2 - 0.2 %/V VSLOPE - 0.49 - V/s ACSA - 9.0 - Current Sense Resistor RSENSE - 22 - m OTA Transconductance GM - 200 - S Transconductance Sink and Source Current Capability ISS - 100 - A IFAIL_LEAK - - 50 A VOL - - 0.4 V Line Regulation (21) - Load Regulation VIN=7.0 to 28 V (21) - VLED = 8.0 to 65 V (all Channels) Slope compensation voltage ramp - RSLOPE = 68 k Current Sense Amplifier Gain FAIL PIN Off-state Leakage Current - VFAIL = 5.5 V On-state Voltage Drop - ISINK = 4.0 mA LED CHANNELS Sink Current ISINK ICHx Register = 255, PIN&NIN = Disabled, TA=25 C RISET=3.48 k, 0.1% Regulated minimum voltage across drivers Pulse Width > 400 ns Current Matching Accuracy ISET Pin Voltage VMIN IMATCH mA 78.4 80 81.6 625 700 775 -2.0 - 2.0 mV VSET RISET=3.48 k, 0.1% % V 2.007 2.048 2.069 - 1.5 - ICH_LEAK - - 10 A VPIN_DIS 2.2 - - V IPIN -2.0 - 2.0 A PIN = VSET/2 36 40 44 mA PIN = VSET 76 80 84 LED Current Amplitude Resolution ILEDRES 1.0 mA < ILED < 80 mA Off-state Leakage Current, All channels - (VCH = 45 V) % PIN INPUT Voltage to Disable PIN mode PIN Bias Current PIN = VSET Analog Dimming Current IDIM_PIN ICHx Register = 255, RISET=3.48 k 0.1% Notes 21. Guaranteed by design 34844A 38 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 11. Static and Dynamic Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, -40C TA 105C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VNIN_DIS 2.2 - - V ININ -2.0 - 2.0 A NIN = VSET/2 36 40 44 mA NIN = 0 V 76 80 84 150 165 175 - 25 - NIN INPUT Voltage to Disable NIN mode NIN Bias Current NIN = VSET Analog Dimming Current IDIM_NIN ICHx Register = 255, RISET=3.48 k 0.1% OVER-TEMPERATURE PROTECTION Over-temperature Threshold(22) OTT Rising Hysteresis C 2 I C/SM BUS PHYSICAL LAYER [SCK, SDA] I2C Address ADRI2C - 1110110 - Binary SM-Bus Address ADRSMB - 1110110 - Binary Input Low Voltage VILI -0.3 - 0.8 V Input High Voltage VIHI 2.1 - 5.5 V Input Hysteresis VHYSI - 0.3 - V Output Low Voltage Sink Current < 4.0 mA VOLI - - 0.4 V IINI -5.0 - 5.0 A CINI - - 10 F Input Low Voltage VILL -0.3 - 0.5 V Input High Voltage VIHL 1.5 - 5.5 V Input Current Input Capacitance (22) LOGIC INPUTS / OUTPUTS (CK, M/~S, PWM, A0/SEN, EN) Input Hysteresis VHYSL - 0.1 - V Input Low Voltage (EN) VILL -0.3 - 0.5 V Input High Voltage (EN) VIHL 2.1 - 28 V Output Low Voltage (CK) VOLL - - 0.45 V VOHL 2.2 - 5.5 V IIIL -5.0 - 5.0 A CINI - - 5.0 F ISINK < 2.0 mA Output High Voltage (CK) ISOURCE < 2.0 mA Input Current Input Capacitance(22) Notes 22. Guaranteed by design 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 39 MC34844A ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 11. Static and Dynamic Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, -40C TA 105C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit OVP = Fh (Default) OVPFH 60.5 62.5 64.5 V OVP = Eh OVPEH 56.5 58 60 V OVP = Dh OVPDH 53 54 56 V OVP = Ch OVPCH 49 51 52.5 V OVP = Bh OVPBH 45 47 48.5 V OVP = Ah OVPAH 41 43 44.5 V OVP = 9h OVP9H 38 39 40.5 V OVP = 8h OVP8H 34 36 37.5 V OVP = 7h OVP7H 30.5 32 33.5 V OVP = 6h OVP6H 26 28 30 V OVP = 5h OVP5H 23 24 25 V Over-voltage threshold, OVPHW 6.15 6.5 6.85 V ISINK_OVP 70 100 130 A Switching Frequency (BST [1:0]=0) fSW0 0.14 0.16 0.18 MHz Switching Frequency (BST [1:0]=1) (Default) fSW1 0.29 0.32 0.35 MHz Switching Frequency (BST [1:0]=2) fSW2 0.59 0.65 0.72 MHz Switching Frequency (BST [1:0]=3) fSW3 1.17 1.30 1.42 MHz Boost Switching Frequency fSW 0.29 0.32 0.35 MHz Minimum Duty Cycle DMIN - 10 15 % Maximum Duty Cycle DMAX 80 85 - % tSS - 6.5 - ms tTR - 15 - ns tF - 25 - ns OVER-VOLTAGE PROTECTION Over-voltage Clamp - OVP Register Table: Set by Hardware, Voltage at A0/SEN A0/SEN Sink Current, TA=25C BOOST Soft Start Period Boost Switch Rise Time Boost Switch Fall Time (23) (23) Notes 23. Guaranteed by design 34844A 40 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A ELECTRICAL CHARACTERISTICS STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS Table 11. Static and Dynamic Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, -40C TA 105C, PGND = 0 V, unless otherwise noted. Characteristic Symbol Min Typ Max Unit fPWMS 110 - 27000 Hz 25000 27000 29000 Hz 103 110 112 tfPWM - 0.39 - % tPWM_IN 150 - - ns fPWM 110 - 27000 Hz fCKS 110 - 27000 Hz fCKS_JITTER - - 0.1 % PWM GENERATOR PWM Frequency Range (25) M/~S = Low (Slave Mode) PWM Frequency fPWMM M/~S = High (Master Mode) FPWM Register = 768 FPWM Register = 192,000 PWM dimming resolution PWM PIN (DIRECT PWM CONTROL) Input PWM Pin Minimum Pulse(25) Input PWM Frequency Range PHASE LOCK LOOP CK Slave Mode Frequency Lock Range(24) M/~S = Low (Slave Mode) CK Slave Mode Input Jitter(25) M/~S = Low (Slave Mode) Slave Mode Acquisition Time TS_ACQ M/~S = Low (Slave Mode) FPWMS=27 kHz - 50 - ms FPWMS=110 Hz - 2000 - ms 25000 27000 29000 Hz 103 110 112 CK Frequency (Master Mode) fCKMASTER FPWM Register = 768 FPWM Register = 192,000 I2C/SM BUS PHYSICAL LAYER [SCK, SDA] Interface Frequency Range fSCK SM Bus Power-on-Reset Time tRST - tSHUTDOWN SM Bus Shut down mode Timeout Output fall time(25) 400 kHz 100 - ms - 30 - ms tF 40 - 160 ns tR 20 - 80 ns tR/tF - 25 - ns tR/tF - 23 50 ns 10 F < CL < 400 F Output rise time(25) 10 F<CL<400 F LOGIC OUTPUT (CK) Output Rise and Fall time CL<100 F LED CHANNELS Channels Rise and Fall Time(25) Notes 24. Special considerations should be made for frequencies between 110 Hz to 1.0 KHz. Please refer to Functional Device Operation for further details. 25. Guaranteed by design 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 41 MC34844A FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION LED backlighting has become very popular for small and medium LCDs, due to some advantages over other backlighting schemes, such as the widely used cold cathode fluorescent lamp (CCFL). The advantages of LED backlighting are low cost, long life, immunity to vibration, low operational voltage, and precise control over its intensity. However, there is an important drawback of this method. It requires more power than most of the other methods, and this is a major problem if the LCD size is large enough. To address the power consumption problem, solid state optoelectronics technologies are evolving to create brighter LEDs with lower power consumption. These new technologies together with highly efficient power management LED drivers are turning LEDs, a more suitable solution for backlighting almost any size of LCD panel, with really conservative power consumption. One of the most common schemes for backlighting with LED is the one known as "Array backlighting". This creates a matrix of LEDs all over the LCD surface, using defraction and diffused layers to produce an homogenous and even light at the LCD surface. Each row or column is formed by a number of LEDs in series, forcing a single current to flow through all LEDs in each string. Using a current control driver, per row or column, helps the system to maintain a constant current flowing through each line, keeping a steady amount of light even with the presence of line or load variations. They can also be use as a light intensity control by increasing or decreasing the amount of current flowing through each LED string. To achieve enough voltage to drive a number of LEDs in series, a boost converter is implemented, to produce a higher voltage from a smaller one, which is typically used by the logical blocks to do their function. The 34844A implements a single channel boost converter together with 10 input channels, for driving up to 16 LEDs per string to create a matrix of more than 160 LEDs. Together with its 90% efficiency and I2C programmable or external current control, among other features, makes the 34844A a perfect solution for backlighting small and medium size LCD panels, on low power portable and high definition devices. FUNCTIONAL PIN DESCRIPTION INPUT VOLTAGE SUPPLY (VIN) IC ENABLE (EN) IC Power input supply voltage, is used internally to produce internal voltage regulation (VDC1, VDC3) for logic functioning, and also as an input voltage for the boost regulator. The active high enable terminal is internally pulled high through pull-up resistors. Applying 0V to this terminal would stop the IC from working. INTERNAL VOLTAGE REGULATOR 1 (VDC1) This pin is for internal use only, and not to be used for other purposes. A capacitor of 2.2 F should be connected between this pin and ground for decoupling purposes. INTERNAL VOLTAGE REGULATOR 2 (VDC2) INPUT/OUTPUT CLOCK SIGNAL (CK) This terminal can be used as an output clock signal (master mode), or input clock signal (slave mode), to synchronize more than one device. MASTER/SLAVE MODE SELECTION (M/~S) This pin is for internal use only, and not to be used for other purposes. A capacitor of 2.2 F should be connected between this pin and ground for decoupling purposes. Setting this pin High puts the device into Master mode, producing an output synchronization clock at the CK terminal. Setting this pin low, puts the device in Slave mode, using the CK pin as an input clock. INTERNAL VOLTAGE REGULATOR 3 (VDC3) EXTERNAL PWM INPUT (PWM) This pin is for internal use only, and not to be used for other purposes. A capacitor of 2.2 F should be connected between this pin and ground for decoupling purposes. A 1.0 k resistor between the VDC3 and VDC1 pin is recommended for <-20 C operation. This terminal is internally pulled down. An external PWM signal can be applied to modulate the LED channel directly in absence of an I2C interface. BOOST COMPENSATION PIN (COMP) Passive terminal used to compensate the boost converter. Add a capacitor and a resistor in series to GND to stabilize the system. CLOCK I2C SIGNAL (SCK) Clock line for I2C communication. ADDRESS I2C SIGNAL (SDA) Address line for I2C communication. 34844A 42 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION A0/SEN Address select, device select pin, or Hardware Overvoltage Protection (OVP) Control. CURRENT SET (ISET) Each LED string can drive up to 50 mA. The maximum current can be set by using a resistor from this pin to GND. POSITIVE CURRENT SCALING (PIN) Positive current scaling factor for the external analog current control. Applying 0 V to this pin, scales the current to near 0%, and in the same way, applying VSET (2.048 V Typ.), the scale factor is 100%. By applying a voltage higher than 2.2 V, the scaling factor is disabled, and the internal pull-ups are activated. If PIN pin and NIN pin are used at the same time then by applying 0 V to the PIN pin and VSET to NIN pin, scales the current to near 0%, and in the same way, applying VSET to the PIN pin and 0 V to NIN pin, scales the current to 100%. By applying a voltage higher than 2.2 V, the scaling factor is disabled and the internal pull-ups are activated in both pins. NEGATIVE CURRENT SCALING (NIN) Negative current scaling factor for the external analog current control. Setting 0 V to this pin scales the current to 100%, in the same way, setting VSET (2.048 V Typ.) the scale factor is near 0%. By applying a voltage higher than 2.2 V, the scaling factor is disabled and the internal pull-ups are activated. If PIN pin and NIN pin are used at the same time then by applying 0 V to the PIN pin and VSET to NIN pin, scales the current to near 0%, and in the same way, applying VSET to the PIN pin and 0 V to NIN pin, scales the current to 100%. By applying a voltage higher than 2.2 V, the scaling factor is disabled and the internal pull-ups are activated in both pins. GROUND (GND) Ground Reference for all internal circuits other than the Boost FET. The Exposed Pad (EP) should be used for thermal heat dissipation. I0-I9 Current LED driver, each line has the capability of driving up to 50 mA. FAULT DETECTION PIN (FAIL) When a fault situation is detected, this pin goes into high impedance. BOOST SLOPE COMPENSATION SETTING RESISTOR (SLOPE) The resistor to be used for the SLOPE depends on the Input and Output voltage difference as well as the inductor value. Please use the formula shown in the Components Calculation section to calculate the value accordingly. POWER GROUND TERMINALS (PGNDA, PGNDB) Ground terminal for the internal Boost FET. OUTPUT VOLTAGE SENSE TERMINAL (VOUT) Input terminal to monitor the output voltage. It also supplies the input voltage for the internal regulator 2 (VDC2). SWITCHING NODE TERMINALS (SWA, SWB) Switching node of boost converter. 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 43 MC34844A FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC34844 - Functional Block Diagram Regulators / Power Down Boost 3 Internal Regulators Protection / Failure Detection Over-temperature Protection Over-current Protection Under-voltage Protection Over-voltage Protection LED Open Protection LED Channels Logic Control Optical and Temperature Control PWM Dimming Serial Interface Control Regulator / Power down Protection / Failure Detection LED Channels Logic Control Boost Figure 25. Functional Internal Block Diagram REGULATORS The 34844A is designed to operate from input voltages in the 7.0 to 28 V range. This is stepped down internally by LDOs to 2.5 V (VDC1 and VDC3) and 6 V (VDC3) for powering internal circuitry. If the input voltage falls below the UVLO threshold, the device automatically enters in shut down mode. Power UP Sequence: The power up sequence for applying VIN, with respect to the ENABLE and PWM signals, is very important to assure a good performance of the part. It is recommended to follow this sequence: 1. Apply VIN first 2. Wait for a couple of milliseconds (~2.0 ms) to let the logic and internal regulators get settled 3. Take the EN pin high, or keep it low depending on the operating mode 4. Apply the PWM signal Operating Modes: The device can be operated by the EN pin and/or SDA/ SCK bus lines, resulting in three distinct operation modes: * Manual mode, there is no I2C capability, the bus line pins must be tied low, and the EN pin controls the ON/OFF operation. To shutdown the part in Manual mode, first the PWM pin should be taken low followed by the EN pin. The part will not shut down unless VOUT collapses to a voltage below 30 V. * SM Bus mode, EN pin must be tied low and the device is turned ON by any activity on the bus lines. The part shuts down if the bus lines are held low for more than 30 ms, the 30 ms watchdog timer can be disabled by I2C (setting SETI2C bit high) or tying the EN pin high. In Sleep mode (EN bit=0) the device reduces the power consumption by leaving "alive" only the blocks required for I2C communication.To shutdown the part in SM Bus mode, the EN bit should first be a '0', then the SCK and SDA should be taken low. * I2C mode, has to be configured by I2C communication (SETI2C bit = 1) right after the IC is turned ON, it prevents the part from being turned ON/OFF by the bus. Sleep mode is also present and it is intended to save power, but still keep the IC prepared to communicate by I2C. By taking the EN bit low and then the EN pin low, the part enters into a shutdown mode. 34844A 44 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 12. Operation Current Consumption Modes MODE Manual SM Bus EN Pin SCK/SDA Pins I2C Bit Command Current Consumption Mode Comments Low Low N/A Shutdown PWM pin = Low High Low N/A Operational Low Low (> 27 ms) EN bit = 0 Shutdown Low Active EN bit = 0 Sleep Low Active EN bit = 1 Operational Low X CLRI2C bit = 0 SETI2C bit = 1 I2C Low Power (Shutdown) Part Doesn't Wake-up EN bit = 0 SETI2C bit = 1 I2 C High X CLRI2C bit = 0 Sleep EN bit = 0 SETI2C bit = 1 High X CLRI2C bit = 0 Operational EN bit = 1 BOOST The integrated boost converter operates in nonsynchronous mode and integrates a 2.5 A FET. An integrated sense circuit is used to sense the voltage at the LED current mirror inputs and automatically sets the boost output voltage (DHC) to the minimum voltage needed to keep all LEDs biased with the required current. The DHC is designed to operate for pulse widths > 400 ns in the LED drivers. If the pulse widths are shorter than specified, the DHC circuit will not operate and the voltage across the LED drivers will increase to a value given by the OVP minus the total LED voltage in the LED string. Therefore it is imperative to select the proper OVP level to minimize power dissipation. The user can program the boost frequency by I2C (BST[1:0]) only after the IC is powered up and before the boost circuit is turned ON for the first time (PWM pin low to high). This sequence avoids boost frequency to be changed inadvertently during operation. The first I2C command has to wait for 5.0 ms after the part is turned ON, in order to allow sufficient time for the device power up sequence to be completed. Please follow this sequence in order to change the Boost frequency thru I2C: 1. Take PWM pin low 2. Disable the part by software (EN bit = low) 3. Write the new Boost frequency data (BST[1:0]) normal quiescent operating temperature and thereby experience a forward voltage change, typically an increase in the forward voltage. This change can be significant for applications with a large number of series LEDs in a string operating at high current. If the boost controller did not track this increased change, the potential on the LED drivers would saturate for a few cycles once the LED channels are reenabled. HARDWARE AND SOFTWARE OVP: The OVP value should be set to a higher value than the maximum LED voltage over the whole temperature range. A good practice is to set it 5.0 V or so above the max LED voltage. The OVP can be set from 11 to 62 V, ~4.0 V spaced, using the I2C interface (OVP Register). If the I2C capability is not present, the OVP can be controlled either by a resistor divider connected from VOUT to GND, with its mid point tied to the A0/SEN pin, or by a zener diode from VOUT to the A0/SEN pin (threshold = 6.5 V). During an OVP condition, the output voltage will go to the OVP level, which is programmed via the I2C interface or settled by a resistor divider on A0/SEN pin, or by a zener diode. The formulas to calculate the hardware OVP using any of the two methods are as follows: Method 1 VOUT 4. Enable the part by software (EN bit = high) 5. Reconfigure all registers 6. Take PWM pin High The boost controller has an integral track and hold amplifier with indefinite hold time capability, to enable immediate LED on cycles after extended off times. During extended off times, the external LEDs cool down from their Method 2 VOUT RUPPER A0/SEN RLOWER VZENER2 A0/SEN OVP = VZENER2 + 6.5 V OVP = 6.5 V [(RUPPER / RLOWER) + 1] + (100E-6 x RUPPER) 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 45 MC34844A FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION OVER-CURRENT PROTECTION (OCP) The boost converter also features internal Over-current Protection (OCP) and has a user programmable Overvoltage Protection (OVP). The OCP operates on a cycle by cycle basis. However, if the OCP condition remains for more than 10ms then the device turns off the LED Drivers, the Boost goes to Sleep mode and the output FAULT pin goes into high-impedance. The device can only be restarted by recycling the enable or creating a Power On Reset (POR). CURRENT MIRROR The programmable current mirror matches the current in 10 LED strings to within 2%. The maximum current is set using a resistor to GND from the ISET pin. This can be scaled down using the I2C interface to 255 levels. Zero current is achieved by turning off the LED Driver by I2C (registers CHENx = 0h) for a duty cycle from 0% to 99%, or by pulling PWM pin low regardless of the duty cycle. I2C capability allows the channels to be controlled individually or in parallel. Current on LED Channel (PIN and NIN mode disabled) VSET [ V ] x 136 ISINK [ A ] = -------------------------------------------RISET [ ] x Eqn. 6 ICH [ RegisterValue ] ----------------------------------------------------------255 Default ICH[RegisterValue]=255 In the off state, the LEDs current is set to 0 and the boost converter stops switching. This feature allows to drive more than 80 mA of current by connecting the LED string to 2 or more LED channels in parallel. For example; if the application requires to drive a channels at 160 mA, then the bottom of each LED string should be connected to two channels in order to duplicate the current capability (Example: CH0+CH1 = 160 mA). The duty cycle of the PWM waveform in both master and slave modes is set using a second register on the I2C interface (register DPWM), and can be controlled from 100% duty cycle to 1/256 Tpwm = 0.39%. Zero percent of duty cycle is achieved by turning LED drivers off (register CHENx = 0h) or pulling PWM pin low. An external PWM can also be used. The PWM input is 'AND'ed with the internal signal. By setting the serial interface to 100% duty cycle (default), the external pin has full control of the PWM duty cycle. This pin can also be used to modulate the LED at a lower frequency than the PWM dimming frequency (DHC Minimum pulse width = 400 ns). POWER OFF AND POWER ON LED CHANNELS The 34844A allows the user to Power OFF and Power ON any channel independently thru I2C/SM-BUS mode. The POWER ON function reconnects the LED driver and the feedback circuit to the channel to allow functionality to that channel again. On an opposite way when the channel is POWER OFF, the LED driver and feedback circuit are disconnected to the channels. This function is very useful for applications where one or more channel has to be shutdown to avoid the output voltages goes to OVP during the start up of the part. The sequence to make these functions work is the following: To POWER ON LED channels: 1. Take PWM pin low 2. Set POWER ON bit high (MSB of Register 09) 3. Set high all Channels that should be power on by writing "1" on CHENx bits (Registers 08 & 09) 4. Clear POWER ON bit 5. Take PWM pin high PWM GENERATOR The PWM generator can operate in either master or slave modes, as set by the M/~S pin. In master mode, the internal PWM generator frequency is programmed through the I2C interface (registers FPWM). The default programmed value set the number of 27 kHz clocks (40 s) in one PWM cycle. The 18-bit resolution allows minimum PWM frequencies of 110 Hz to be programmed. The resulting frequency is output on the CK pin. PWM Frequency To POWER OFF LED channels: 1. Take PWM pin low 2. Set POWER OFF bit high (MSB of Register 08) 3. Clear all Channels that should be power off by writing "0" on CHENx bits (Registers 08 & 09) 4. Clear POWER OFF bit 5. Take PWM pin high Eqn. 7 20.736Mhz FPWM [ Hz ] = -------------------------------------------------------------------FPWM [ RegisterValue ] In slave mode, the CK pin acts as an input. The internal digital PLL uses this frequency as the PWM frequency. By setting one device as master, and connecting the CK output to the input on a number of slave configured devices, all PWM frequencies are synchronized together. POWER ON bit and POWER OFF bit shouldn't be set at the same time in order to avoid damage to the part. POWER ON/OFF channels should be reconfigured every time the part gets recovered from a POR or shutdown condition. This also apply if the part is reenabled by software. If the part is reenabled by software, it is recommended to take PWM pin low, reenable the part and then follow the corresponding sequence shown above. 34844A 46 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION DISABLING LED CHANNELS The 34844A allows the user to enable and disable each of the 10 channels separately by writing the corresponding CHENx bit on Registers 08 and 09 thru I2C. Since the enable and disable functions reconnects the feedback circuit of the LED drivers, this shouldn't be used on any channel that shuts down either because an open LED channel condition or because is was previously POWER OFF. This could cause instability issues since the voltage on this open LED driver is not substantially above the DHC regulation voltage (0.75 V typ) and may interfere with the operation of the dynamic headroom control (DHC) which can lead to erratic output voltage regulation FAIL PIN If a LED fails open in any of the LED strings, the voltage in that particular LED channel will be close to ground and the LED open failure is detected. When this happens, a failure is registered, the FAIL pin is set to its high-impedance stage, and the channel is shut down. The FAIL pin cannot be cleared for manual mode unless a complete power on reset is applied. However for I2C/SMBUS mode, the FAIL pin can be cleared by cycling the clear fail bit (CLRFAIL bit = 0 - 1 - 0). This allows the user to waive any known failure and set the device for being able to detect any other failure during operation. If the fail pin cannot be cleared by software then it indicates that the failure is because of an over-current in the Boost. Since this is a critical failure the only way to clear it is by releasing the part from the over-current condition and then shutdown the part (Refer to Table 12) If I2C communication is not present, FAIL condition should be reset by removing the failure and re-enabling the device thru the EN pin. OPTICAL AND TEMPERATURE CONTROL LOOP The 34844A supports both optical and temperature loop control. For temperature loop control, the LED brightness can be adjusted depending on the temperature of the LEDs. For optical loop control, the 34844A supports both optical closed loop backlight control, where the brightness of the backlight is maintained at a required level by adjusting the light output, until the desired level is achieved, or with ambient light control, where the backlight brightness increases as ambient light increases. Both temperature and optical loops are supported through the PIN and NIN pins. Each pin supports a 0 V to VSET (2.048 V typ.) input range which affects the current through the LEDs. The PIN pin increases current as the voltage rises from 0 to VSET. The NIN pin reduces current as the voltage rises from 0 - VSET. A 6.98 kohm resistor or higher value must be used at the ISET pin if the part is configured to use PIN+NIN control loop functionality, the 80 mA maximum current is achieved at the higher allowed level of PIN/NIN pins, ensuring the maximum current of the LED Drivers are not exceeded. The optical and temperature control loop can be disabled by I2C setting bits (PINEN & NINEN), or by tying PIN and NIN pins high (>2.2 V). The LED Driver maximum current is set to 80 mA by using a 3.48 kohm resistor at the ISET pin. Current on LED Channel (PIN mode) VPIN [ V ] IDIM [ A ] = ISINK [ A ] x -----------------------2 Eqn. 8 Current on LED Channel (NIN mode) Eqn. 9 IDIM [ A ] = ISINK [ A ] x ( VSET - VNIN ) [ V ] ---------------------------------------------------2 Current on LED Channel (PIN+NIN mode) IDIM [ A ] = ISINK [ A ] x Eqn. 10 ( VSET + VPIN - VNIN ) [ V ] -------------------------------------------------------------------------2 VPIN and VNIN is the voltage applied on PIN and NIN pins correspondingly. For ISINK formula please refer to Equation 1. LED FAILURE PROTECTION Open LED Protection If LED fails open in any of the LED strings, the voltage in that channel will be pulled close to zero, which will cause the channel to be disabled. As a result, the boost output voltage will go to the OVP level and then come down to the regulation level to continue powering the rest of the LED strings. Short LED Protection If an LED shorted in any of the LED strings, the device will continue to operate without interruption. However, if the shorted LED happens to be in the LED string with the highest forward voltage, the DHC circuit will automatically regulate the output voltage with respect to the new highest LED voltage. If more LEDs are shorted in the same LED string, it may cause excessive power dissipation in the channel which may cause the OTT circuit to trip which will completely shutdown the device. OVER-TEMPERATURE PROTECTION The 34844A has an on-chip temperature sensor that measures die temperature. If the IC temperature exceeds the OTT threshold, the IC will turn off all power sources inside the IC (LED drivers, boost and internal regulators) until the temperature falls below the falling OTT threshold. Once it comes back on, it will operate with the default configuration (refer to Table 14). SERIAL INTERFACE CONTROL The 34844A uses an I2C interface capable of operating in standard (100 kHz) or fast (400 kHz) modes. The A0/SEN pin can be used an address select pin to allow more than 2 devices in the system. The A0/SEN pin should be held low on all chips expect the one to be addressed, where it is taken HIGH. 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 47 MC34844A FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES NORMAL MODE In normal operation the 34844A is programed via I2C to drive up to 50 mA of current through each one of the LED channels. The 34844A can be configured in master or slave mode as set by the M/~S pin. In Master mode, the internal PWM generator frequency is programmed through the I2C interface. The programmed value sets the number of 27 kHz clocks (37s) in one PWM cycle. The 18-bit resolution allows minimum PWM frequencies of 110 Hz to be programmed. The resulting frequency is output on the CK pin. In slave mode, the CK pin acts as an input. The internal digital PLL uses this frequency as the PWM frequency. By setting one device as a master, and connecting the CK output to the input on a number of slave configured devices, all PWM frequencies are synchronized together. For this application A0/SEN pin indicates which device is enable for I2C control. In Slave mode, an internal phase lock loop will lock the internal PWM generator period to the period of the signal present at the CK pin. The PLL can lock to any frequency from 110 Hz to 27 KHz provided the jitter is below 1000 ppm. At frequencies above 1.0 KHz, the PLL will maintain lock regardless of the transient power conditions imposed by the user (i.e. going from 0% duty cycle to 100% at 20W LED display power). Below 1.0 kHz, thermal time constants on the die are such that the PLL may momentarily lose lock if the die temperature changes substantially during a large load power step. As explained below, this anomaly can be avoided by controlling the rate of change in PWM duty cycle. To better understand this issue, consider that the on chip PLL uses a VCO that is subject to thermal drift on the order of 1000 ppm/C. Further consider that the thermal time constant of the chip is on the order of single digit milliseconds. Therefore, if a large power load step is imposed by the user (i.e. going from 0% duty cycle to 100% duty cycle with a load power of 20 W), the die will experience a large temperature wave gradient that will propagate across the chip surface and thereby affect the instantaneous frequency of the VCO. As long as such changes are within the bandwidth of the PLL, the PLL will be able to track and maintain lock. Exceeding this rate of change may cause the PLL to lose lock and the backlight will momentarily be blanked until lock is reacquired. At 110 Hz lock, the PLL has a bandwidth of approximately 10 Hz. This means that temperature changes on the order of 100 ms are tolerable without losing lock. But full load power changes on the order of 10 ms (i.e. 110 Hz PWM) are not tracked out and the PLL can momentarily lose lock. If this happens, as stated above, the LED drivers are momentarily disabled until lock is reacquired. This will be manifested as a perceivable short flash on the backlight immediately after the load change. To avoid this problem, one can simply limit large instantaneous changes in die temperature by invoking only small power steps when raising or lowering the display power at low PWM frequencies. For example, to maintain lock while transitioning from 0% to 100% duty cycle at 20 W load power and a PWM frequency of 110 Hz would entail stepping the power at a rate not to exceed 1% per 10 ms. If a load of less than 20 W is used, then the rate of rise can be increased. As the locked PWM frequency increases (i.e. use 600 Hz instead of 110 Hz), the step rate can be further increased to approximately 4% per 2.0 ms. The exact step rate to avoid loss of PLL lock is a function of essentially three things: (a) the composite thermal resistance of the user's PCB assembly, (b) the load power, and (c) the PWM frequency. For all cases below 1.0 KHz, simply using a rate of 1% duty cycle change per PWM period will be adequate. If this is too slow, the value can be optimized experimentally once the hardware design is complete. At PWM rates above 1.0 KHz, it is not necessary to control the rate of change in PWM duty cycle. It is important to point out that when operating in the master mode, one does not need to concern themselves with loss of lock since the reference clock and the VCO clock are collocated on the die, and therefore experience the same thermal shift. Hence in master mode, once lock is initially acquired, it is not lost and no blanking of the display occurs. The duty cycle of the PWM in both master and slave mode is set using a second register on the I2C interface. An external PWM signal can also be applied in the PWM pin. This pin is AND'ed with the internal signal, giving the ability to control the duty cycle either via I2C or externally by setting any of the 2 signals to 100% duty cycle. MANUAL MODE The 34844A can also be used in Manual mode without using the I2C interface. By setting the pin M/~S High, the LED dimming will be controlled by the external PWM signal. The over-voltage protection limit can be settled by a resistor divider or a zener diode on A0/SEN pin. During manual mode, all internal Registers are in Default Configuration, refer Table 14, under this configuration the PIN and NIN pins are enabled to scale the current capability per string and may be disable by setting 2.2 V in the corresponding terminal. Also in this mode, the device can be enabled as follows: * EN pin + PWM signal (Two Signals): In this configuration, the PWM signal applied to PWM pin will be in charge of controlling the LED dimming and a second signal will enable or disable the chip through the EN pin. * PWM Signal tied to SDA pin (Just ONE signal): In this configuration the PWM pin should be tied to the SDA pin. The PWM signal applied to PWM pin will be in 34844A 48 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A FUNCTIONAL DEVICE OPERATION I2C BUS SPECIFICATION charge of controlling LED dimming and enabling the device every time the PWM is active. For this configuration the EN pin should be LOW. I2C BUS SPECIFICATION The 34844A is a unidirectional device that can only be written by an external control unit. Since the device is a 7 bit address device (1110110), the control unit needs to follow a specific data transfer format which is shown in Table 26. Figure 26. A Complete Data Transfer For a complete data transfer, please use this format in the down the SDA line during this acknowledge pulse to following order: indicate that the data was correctly written. * Bits in the first byte: The first seven bits of the first bite 1. START condition make up the slave address. The eighth bit is the LSB (least 2. 34844A device address and Write instruction (R/W = 0) significant bit), which determines the direction of the 3. First data pack, it corresponds to the 34844A register message (Write = 0) that needs to be written. (refer to Table 13) For the 34844A device, when an address is sent, each of 4. Second data pack, it corresponds to the value that the devices in a system compares the first seven bits after should be written to that register. (refer to Table 13) the START condition with its address. If they match, the device considers itself addressed by the control unit as a 5. STOP condition slave-receiver. * STOP: this condition occurs when SDA changes from I2C variables description: LOW to HIGH while SCK is HIGH * START: this condition occurs when SDA changes from For more information about "I2C BUS SPECIFICATION" HIGH to LOW while SCK is HIGH. please refer to the following link: * ACKNOWLEDGE: The acknowledge clock pulse is generated by the Master (Control Unit). http://www.nxp.com/acrobat_download/literature/ * The transmitter releases the SDA line (HIGH) during the 9398/39340011.pdf acknowledge clock pulse.The receiver (34844A) must pull 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 49 MC34844A FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS Table 13. Write Registers reg / db D7 D6 OVP3 00 OVP2 D5 OVP1 D4 D3 OVP0 D2 NINEN 01 D1 D0 PINEN EN CLRI2C SETI2C 04 FPWM5 FPWM4 FPWM3 FPWM2 FPWM1 FPWM0 05 FPWM11 FPWM10 FPWM9 FPWM8 FPWM7 FPWM6 06 FPWM17 FPWM16 FPWM15 FPWM14 FPWM13 FPWM12 DPWM5 DPWM4 DPWM3 DPWM2 DPWM1 DPWM0 CHEN4 CHEN3 CHEN2 CHEN1 CHEN0 CHEN9 CHEN8 CHEN7 CHEN6 CHEN5 BST1 BST0 07 DPWM7 DPWM6 08 PWR_OFF 09 PWR_ON CLRFAIL ALL_OFF 14 F0 ICH0_7 ICH0_6 ICH0_5 ICH0_4 ICH0_3 ICH0_2 ICH0_1 ICH0_0 F1 ICH1_7 ICH1_6 ICH1_5 ICH1_4 ICH1_3 ICH1_2 ICH1_1 ICH1_0 F2 ICH2_7 ICH2_6 ICH2_5 ICH2_4 ICH2_3 ICH2_2 ICH2_1 ICH2_0 F3 ICH3_7 ICH3_6 ICH3_5 ICH3_4 ICHG_3 ICH3_2 ICH3_1 ICH3_0 F4 ICH4_7 ICH4_6 ICH4_5 ICH4_4 ICH4_3 ICH4_2 ICH4_1 ICH4_0 F5 ICH5_7 ICH5_6 ICH5_5 ICH5_4 ICH5_3 ICH5_2 ICH5_1 ICH5_0 F6 ICH6_7 ICH6_6 ICH6_5 ICH6_4 ICH6_3 ICH6_2 ICH6_1 ICH6_0 F7 ICH7_7 ICH7_6 ICH7_5 ICH7_4 ICH7_3 ICH7_2 ICH7_1 ICH7_0 F8 ICH8_7 ICH8_6 ICH8_5 ICH8_4 ICH8_3 ICH8_2 ICH8_1 ICH8_0 F9 ICH9_7 ICH9_6 ICH9_5 ICH9_4 ICH9_3 ICH9_2 ICH9_1 ICH9_0 FA ICHG_7 ICHG_6 ICHG_5 ICHG_4 ICHG_3 ICHG_2 ICHG_1 ICHG_0 All registers and POWER ON/OFF channels should be reconfigured every time the part gets recovered from a POR or shutdown condition. The configuration sequence every time the part is power up should be as follows: 1. Take the PWM pin low 2. Power up the part 3. Configure all registers For configuring the part once in operation it is recommended to follow this sequence: 1. Take the PWM pin low 2. Configure the registers 3. Take the PWM pin High Special considerations should be taken for re-configuring POWER ON/OFF functions, please refer to the POWER OFF and POWER ON LED CHANNELS section. 4. Take the PWM pin High Table 14. Register Description Register Name Default Value (Hex) EN 1 Chip Enable by software. PINEN 1 PIN pin enable (0=off, 1 =on) NINEN 1 NIN pin enable (0=off, 1 =on) OVP[3:0] F OVP voltage SETI2C 0 SET I2C communication (Disable SM Bus Mode) CLRI2C 0 Clear set I2C Description 34844A 50 Analog Integrated Circuit Device Data Freescale Semiconductor MC34844A FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 14. Register Description Register Name Default Value (Hex) FPWM[17:0] 300 PWM Frequency DPWM[7:0] FF PWM Duty Cycle (FFh =100%) CHEN[9:0] 3FF Channel Enable (0=off, 1=on) ALL_OFF 0 All 10 channels OFF at the same. In order to reactivate channels this bit should be clear. CLRFAIL 0 Clear fail if channels are re-enable. PWR_OFF 0 POWER OFF LED channels (0=disable, 1=enable) PWR_ON 0 POWER ON LED channels (0=disable, 1=enable) BST[1:0] 2 Boost Frequency (160,320,650,1300 kHz) [0h=160 Hz] ICH#[7:0] FF Channel Current Program (FFh = Maximum Current) ICHG[7:0] FF Global Current Program Description Table 15. Over-voltage Protection Register (hex) OVP Value (vOLTS) 2 11 3 15 4 19 5 23 6 27 7 31 8 35 9 39 A 43 B 47 C 51 D 55 E 59 F 62 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 51 MC34844A TYPICAL APPLICATIONS TYPICAL APPLICATIONS MANUAL MODE (Single Wire Control) 22uH VIN = 24V 1 2 1.0K 47uF 1 + 2.2uF 2.2uF 0 2.2uF 56pF 0 5.6K 309K 1.8nF VDC1 VDC2 VDC3 29 22 COMP SLOPE Master CK Output 24 7 0 0 CLK VOUT VIN 28 31 23 0 150K OVP = 55V 20K VDC1 5.1K VDC1 PWM 27 26 SCK SDA 6 30 A0/SEN M/~S 19 ISET 20 21 PIN NIN 0 SWA SWB 4 3 VOUT 32 D1 2 1 13.8uF + 5 2 PGNDA PGNDB CK EN 25 LED MATRIX (16S10P) VOUT U1 FAIL 18 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 8 9 10 11 12 13 14 15 16 17 GND 33 VCC 3.3K 0 34844 0 Figure 27. Manual Mode (Single Wire Control) Conditions: VIN = 24 V, VOUT = 47 V, Load = 16S10P, ILED = 60 mA, OVP = 53V, fSW = 300 kHz MANUAL MODE (Two Wire Control) 22uH VIN = 24V 1 2 VOUT U2 1.0K 47uF 1 + 2.2uF 2.2uF 0 2.2uF 56pF 0 Control 5.6K 309K 1.8nF 0 PWM Unit VOUT 150K 0 OVP = 55V 20K VDC1 5.1K VDC1 0 VDC1 VDC2 VDC3 29 22 COMP SLOPE Master CK Output 24 7 0 EN VIN 28 31 23 PWM 27 26 SCK SDA 6 30 A0/SEN M/~S 19 ISET 20 21 PIN NIN 4 3 32 PGNDA PGNDB CK EN 25 SWA SWB VOUT 34844 2 D5 1 LED MATRIX (16S10P) 13.8uF + 5 2 FAIL 18 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 8 9 10 11 12 13 14 15 16 17 GND 33 VCC 3.3K 0 0 Figure 28. Manual Mode (Two Wire Control) Conditions: VIN = 24 V, VOUT = 47 V, Load = 16S10P, ILED = 60 mA, OVP = 53V, fSW = 300 kHz 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 52 MC34844A TYPICAL APPLICATIONS I2C MODE (Master Mode) 1 VIN = 24V 1 + 10uF 2.2uF 2.2uF 0 5.6K OUTPUT 0 MASTER CK VDC1 0 24 7 25 CONTROL UNIT VDC1 4.64K ISET = 60mA VDC1 SCK SDA 6 30 A0/SEN M/~S 19 ISET 20 21 PIN NIN 0 8 9 10 11 12 13 14 15 16 17 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 4.7uF VCC 18 FAIL PWM 27 26 + 30uF 5 2 PGNDA PGNDB CK EN 1 32 VOUT COMP SLOPE D533 2 4 3 SWA SWB VDC1 VDC2 VDC3 29 22 100K 100pF EN_Master SCK SDA A0SEN_Master LED MATRIX (16S10P) VOUT VIN 28 31 23 4700pF 2.2uF 0 2 U9 1.0K 47uF 47uH 0 3.3K 220pF 33 GND MC34844A 220pF 0 220pF 220pF 220pF 220pF * FOR I2C MODE - SETI2C bit should be set High. * FOR SM-BUS MODE - EN pin should be connected to GND or taken low by the Control Unit. 220pF 220pF 220pF 220pF 0 Figure 29. I2C (Master Mode) Conditions: VIN = 24 V, VOUT = 47 V, Load = 16S10P, ILED = 60 mA, OVP = 53V, fSW = 300 kHz I2C MODE (Slave Mode) 1 VIN = 24V 1 + 10uF 2.2uF 0 2.2uF 28 31 23 4700pF 2.2uF 0 5.6K 100K 100pF EN_Slave SCK SDA A0SEN_Slave 2 LED MATRIX (16S10P) VOUT U11 1.0K 47uF 47uH 0 0 INPUT VDC1 MASTER CK 29 22 24 7 25 27 26 6 30 CONTROL UNIT 0 4.64K ISET = 60mA VDC1 0 19 20 21 VIN VDC1 VDC2 VDC3 COMP SLOPE SWA SWB VOUT PGNDA PGNDB CK EN FAIL PWM I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 SCK SDA A0/SEN M/~S ISET PIN NIN GND 4 3 2 D553 1 + 32 30uF 5 2 VCC 18 8 9 10 11 12 13 14 15 16 17 3.3K MC34844A 0 220pF 33 * FOR I2C MODE - SETI2C bit should be set High. * FOR SM-BUS MODE - EN pin should be connected to GND or taken low by the Control Unit. 4.7uF 0 220pF 220pF 220pF 220pF 220pF 220pF 220pF 220pF 220pF 0 Figure 30. I2C (Slave Mode) Conditions: VIN = 24 V, VOUT = 47 V, Load = 16S10P, ILED = 60 mA, OVP = 53V, fSW = 300 kHz 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 53 MC34844A TYPICAL APPLICATIONS LED MATRIX (40S8P) 1 150UH PDS3200 VIN = 60V to 72V 2 1 VDC2 1.0k 2.2uF EN_DLY 1 0 2.2uF 3.3nF 100pF 0 0 2.2uF 28 31 23 200k 0 EN_DLY 6.8K VOUT PWM = 200Hz (5V) 0 270K 4.64K OVP = 125V 18K 0 24 7 25 27K 0 29 22 ISET = 60mA VDC1 27 26 6 30 19 VDC1 20 21 VDC1 VDC2 VDC3 COMP SLOPE CK EN PWM SCK SDA A0/SEN M/~S ISET PIN NIN MC34844A SWA SWB VOUT PGNDA PGNDB FAIL I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 GND 1 2 82V MMSZ5268BT1G 10uF 250V + 10uF 250V + 10uF 250V + 220pF 220pF 1uF 250V 2 1 VIN 3 0 4 2 0.1UF 0.1UF 100V 2.2uF 8 10 FDS2572 47V 3SMBJ5941B-TP 0 7 10uF 100V + 6 5 7447709151 47uF 100V 10.0K VOUT = 120V 3 4 3 32 5 2 18 0 8 9 10 11 12 13 14 15 16 17 33 0 220pF 220pF 220pF 220pF 220pF 220pF 0 Figure 31. HIGH VOUT application (Manual Mode) Conditions: VIN = 60 to 72V, VOUT = 120 V, Load = 40S8P, ILED = 60 mA, OVP = 125 V, fSW = 300 kHz 34844A Analog Integrated Circuit Device Data Freescale Semiconductor 54 COMPONENTS CALCULATION COMPONENTS CALCULATION The following formulas are intended for the calculation of all external components related with the Boost converter and Network compensation. In order to calculate a Duty Cycle, the internal losses of the MOSFET and Diode should be taken into consideration. Vout + V D - Vin D = --------------------------------------------Vout + V D - V SW The average input current depends directly to the output current when the internal switch is off. Iout Iin avg = ------------1-D Inductor For calculating the Inductor we should consider the losses of the internal switch and winding resistance of the inductor. ( Vin - V SW - ( Iin avg x rw ) ) x D L = ---------------------------------------------------------------------------------Iin avg x r x F SW It is important to look for an inductor rated at least for the maximum input current. Iin max Vin x ( Vout - Vin ) = Iin avg + ------------------------------------------------2 x L x F SW x Vout Input Capacitor The input capacitor should handle at least the following RMS current. CSG = A CSA x R Sense R Comp x 5 x G M x Iout x L Cout = -------------------------------------------------------------------( 1 - D ) x Vout x CSG The output voltage ripple (VOUT) depends on the ESR of the Output capacitor, for a low output voltage ripple it is recommended to use Ceramic capacitors that usually have very low ESR. Since ceramic capacitor are expensive, Electrolytic or Tantalum capacitors can be mixed with ceramic capacitors to have a cheaper solution. Vout x Vout x F SW x L ESR Cout = --------------------------------------------------------------Vout x ( 1 - D ) The output capacitor should handle at least the following RMS current. Network Compensation Since this Boost converter is current controlled, Type II compensation is needed. D Irms Cout = Iout x -----------1-D I order to calculate the Network Compensation, first we need to calculate all Boost Converter components. For this type of compensations we need to push out the Right Half Plane Zero to higher frequencies where it can't affect the overall loop significantly. 2 Vout x ( 1 - D ) f RHPZ = ---------------------------------------Iout x 2 x x L The Crossover frequency must be set much lower than the location of the Right half plane zero Vin x ( Vout - Vin ) Irms Cin = ------------------------------------------------- x 0.3 2 x L x F SW x Vout Output Capacitor For the output capacitor selection the internal current sense gain (CSG) and the Transconductance should be taken in consideration. The CSG is the internal RSENSE times the current sense amplifier gain (ACSA). f RHPZ f Cross = --------------5 Since our system has a fixed Slope compensation set by RSLOPE, RCOMP should be fixed for all configurations. R Comp = 5.6kohm CCOMP1 and CCOMP2 should be calculated as follows: 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 55 COMPONENTS CALCULATION 3 2 C Comp1 = -------------------------------------------------------f Cross x R Comp x x 2 33 x10 R SLOPE = ----------------------------V SLOPE x 5 GM C Comp2 = --------------------------6.28 x F SW In order to improve the transient response of the boost, on the 34844A, a resistor divider has been implemented from the PWM pin to ground with a connection to the compensation network. This configuration should inject a 1.0 V signal to the COMP pin and the Thevenin-equivalent resistance of the divider is close to RCOMP, i.e. RCOMP = 6.8 k and RPCOMP= 27 k for a 5.0 V PWM signal. PWM CCOMP1 COMP PIN RPCOMP CCOMP2 RCOMP Slope Compensation Slope Compensation can be expressed either in terms of Ampers/Second or as Volts/Second, through the use of the transfer resistance. The following formula express the Slope Compensation in terms of V/s: ( Vout - Vin ) x CSG V SLOPE = ---------------------------------------------------Lx2 Variable Definition D= Boost Duty Cycle VOUT= Output Voltage VD= Diode Forward Voltage VIN= Input Voltage VSW= VDROP of Internal Switch VOUT= Output Voltage Ripple Ratio IINAVG= Average Input Current IOUT= Output Current r=Input Current Ratio IINMAX= Maximum input current IRMSCIN= RMS current for Input Capacitor IRMSCOUT= RMS current for Output Capacitor L= Inductor RW= Inductor winding DC Resistance fSW= Boost Switching Frequency CSG= Current Sense Gain = 0.2 V/A ACSA= Current Sense Amplifier Gain = 9 RSENSE= Current Sense Resistor = 22mohm COUT= Output Capacitor RCOMP= Compensation Resistor GM= OTA Transconductance ESRCOUT= ESR of Output Capacitor fRHPZ= Right Half Plane Zero Frequency fCROSS= Crossover Frequency CCOMP1= Compensation Capacitor CCOMP2= Shunt Compensation Capacitor VSLOPE= Slope Compensation (V/s) RSLOPE= External Resistor for Slope Compensation Where "L" is in H In order to have this slope compensation, the following resistor should be set. 34844 56 Analog Integrated Circuit Device Data Freescale Semiconductor LAYOUT GUIDELINES LAYOUT GUIDELINES RECOMMENDED STACK-UP SWITCHING NODE (SWA & SWB) The following table shows the recommended layer stackup for the signals to have good shielding and Thermal Dissipation. The components associated to this node must be placed as close as possible to each other to keep the switching loop small enough so that it does not contaminate other signals. However, care must be taken to ensure the copper traces used to connect these components together on this node are capable to handle the necessary current and voltage. As a reference, a 10 mils trace with a thickness of 1.0 oz. of copper is capable of handling one ampere. Traces for connecting the inductor, input and output caps should be as wide and short as possible to avoid adding inductance or resistance to the loop. The placement of these components should be selected far away from sensitive signals like compensation, feedback and internal regulators to avoid power noise coupling. Table 16. Layer Stacking Recommendations Stack-Up Layer 1 (Top) Signal Layer 2 (Inner 1) Ground Layer 3(Inner 2) Signal Layer 4 (Bottom) Ground DECOUPLING CAPS It is recommended to place decoupling caps of 100 pf at the beginning and at the end of any power signal traces to filter high frequency noise. Decoupling caps of 100 pf should be also placed at the end of any long trace to cancel antenna effects on it. These caps should be located as closed as possible to the point to be decoupled and the connection to GND should be as short as possible. SM-BUS/I2C COMMUNICATION AND CLOCK SIGNALS (SDA, SCK AND CK) COMPENSATION COMPONENTS Components related with COMP pin need to be placed as close as possible to the pin. FEEDBACK SIGNAL The trace of the feedback signal (VOUT) should be routed perpendicularly or at 45 on a different layer to avoid coupling noise, preferably between ground or power planes. To avoid contamination of these signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform through the whole signal trace length. IInnppuut Ca Capp ut C S Sw wiititcchhiin ingg N Noodde de DO Signal On State FFe dbaac ackk Feeeddb S Si Siggn gnaall C Coom mppeen enssa saattiiioonn Off State Signal O Caapp Ouuttppuutt C Ground Planes Ground Plane Figure 32. Recommended shielding for critical signals. These signals shall not run parallel to power signals or other clock signals in the same routing layer. If they have to cross or to be routed close to a power signal, it is a good practice to trace them perpendicularly or at 45 on a different layer to avoid coupling noise. Figure 33. Feedback Signal Tracing 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 57 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below. EP SUFFIX 32-PIN 98ASA10800D REVISION O 34844 58 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EP SUFFIX 32-PIN 98ASA10800D REVISION O 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 59 PACKAGING PACKAGE DIMENSIONS EP SUFFIX 32-PIN 98ASA10800D REVISION O 34844 60 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 3.0 11/2008 * Initial Release 4.0 3/2009 * * * * 5.0 5/2009 * Corrected Compensation Components paragraph on page 32. 6.0 9/2009 * Added Part Number MC34844AEP/R2. 7.0 3/2010 8.0 7/2010 9.0 3/2012 * Combined Complete Data sheet for Part Numbers MC34844 and MC34844A to this data sheet. * Removed OVP=4h, OVP=3h and OVP=2h rows from Table 11. * PWM and CK Frequency range changed in Electrical Characteristics table. * Added resistor between VDC1 and VDC3 on the application drawings. Added to notes for VDC3 on pages 9, 14, 37, and 42. Added PWM Pin to Maximum Voltages in Maximum Rating Table. Added Disabling LED Channels Rewrote Fail Pin section Added I2C Bus Specification 34844 Analog Integrated Circuit Device Data Freescale Semiconductor 61 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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