Document Number: MC34844
Rev. 9.0, 3/2012
Freescale Semiconductor
Advance Information
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
10 Channel LED Backlight Driver
with Integrated Power Supply
The 34844/A is a high efficiency, LED driver for use in backlighting
LCD displays from 10" to 20"+. Operating from supplies of 7.0 to 28 V,
the MC34844/A is capable of driving up to 160 LEDs in 10 parallel
strings. Current in the 10 strings is matched to within ±2%, and can be
programmed via the I2C/SM Bus interface.
The 34844/A also includes a Pulse Width Monitor (PWM) generator
for LED dimming. The LEDs can be dimmed to one of 256 levels,
programmed through the I2C/SM Bus interface. Up to 65,000:1 (256:1
PWM, 256:1 Current DAC) dimming ratio.
The integrated boost converter generates the minimum output
voltage required to keep all LEDs illuminated with the selected current,
providing the highest efficiency possible.
The 34844 has an integrated boost self-clocks at a default
frequency of 600 kHz, but may be programmed via I2C to 150/300/
600/1200 kHz. The PWM frequency can be set from 100 Hz to 25 kHz,
or can be synchronized to an external input. If not synchronized to
another source, the internal PWM rate outputs on the CK pin. This
enables multiple devices to be synchronized together.
The 34844A has a default boost frequency of 320 kHz, but may be
programmed via I2C to 160/320/650/1300 kHz. The PWM frequency
can be set from 110 Hz to 27 kHz, or can be synchronized to an
external input. If not synchronized to another source, the internal PWM
rate outputs on the CK pin. This enables multiple devices to be
synchronized together.
The 34844/A also supports optical/temperature closed loop
operation and also features LED over-temperature protection, LED
short protection, and LED open circuit protection. The IC also includes
over-voltage protection, over-current protection, and under-voltage
lockout.
Features
• Input voltage of 7.0 to 28 V
•2.5 A integrated boost FET
•Up to 50 mA on the 34844 LED current per channel
•Up to 80 mA on the 34844A LED current per channel
• 90% efficiency (DC:DC)
•I
2C/SM Bus interface
• 10 channel current mirror with ±2% current matching
• Boost output voltage up to 60V, with Dynamic Headroom Control (DHC)
• PWM frequency programmable or synchronizable from 100 to 25,000 Hz for the 34844
• PWM frequency programmable or synchronizable from 110 to 27,000 Hz for the 34844A
• 32-Ld 5x5x1.0mm TQFN Package
Applications
• Monitors and HDTV - up to 42 inch
• Personal Computer Notebooks
• GPS Screens
• Small screen Televisions
LED DRIVER
34844
34844A
EP SUFFIX (PB-FREE)
98ASA10800D
32-PIN QFN-EP
ORDERING INFORMATION
Device Temperature
Range (TA)Package
MC34844EP/R2 -40 °C to 105 °C 32 QFN-EP
MC34844AEP/R2
Analog Integrated Circuit Device Data
2Freescale Semiconductor
34844
Figure 1. MC34844 Simplified Application Diagram (SM Bus Mode)
Figure 2. MC34844A Simplified Application Diagram (Manual Mode)
7.0 to 28 V
FAIL
PGNDA
34844
SWA
SWB
VOUT
PGNDB
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
VCC
GND
SCK
SDA
A0/SEN
ISET
PIN
NIN
VIN
VDC1
VDC2
VDC3
COMP
SLOPE
CK
EN
PWM
Control Unit
M/~S
VDC1
VDC1
~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~
VDC1
7.0 to 28V
FAIL
PGNDA
34844A
SWA
SWB
VOUT
PGNDB
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
VCC
GND
SCK
SDA
A0/SEN
ISET
PIN
NIN
VIN
COMP
SLOPE
CK
EN
PWM
Control Unit
M/~S
VDC1
~
~~
~~
~~
~~
~~
~~
~~
~~
~~
~
VDC1
VOUT
VOUT
PWM
PWM
VDC1
VDC2
VDC3
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
34844
DEVICE VARIATIONS
DEVICE VARIATIONS
MC34844 is within the MC34844 Specifications Pages 4 to 31, MC34844A is within the MC34844A Specifications Pages 32
to 54
Table 1. Key Device Variations between the MC34844 and MC34844A
Electrical Parameter(1) Condition Value Unit
Maximum LED Current
34844
34844A
55
85
mA
LED Channel Sink Current
34844
34844A
RISET=5.1 kΩ ±0.1%
RISET=3.48 kΩ ±0.1%
(typ)
50
80
mA
Switching Frequency
34844
34844A
(BST [1:0]=0)
(BST [1:0]=1)
(BST [1:0]=2) [default]
(BST [1:0]=3)
(BST [1:0]=0)
(BST [1:0]=1)) [default]
(BST [1:0]=2)
(BST [1:0]=3)
(typ)
0.15
0.30
0.60
1.20
0.16
0.32
0.65
1.30
MHz
PWM Frequency Range
34844
34844A
This frequency range applies for Master
mode, Slave mode, and Manual mode 100 - 25000
110 - 27000
Hz
Notes
1. Refer to the respective Electrical Parameters for specific details
Analog Integrated Circuit Device Data
4Freescale Semiconductor
34844
MC34844 SPECIFICATIONS PAGES 4 TO 31
MC34844
MC34844 SPECIFICATIONS
PAGES 4 TO 31
Analog Integrated Circuit Device Data
5Freescale Semiconductor
34844
INTERNAL BLOCK DIAGRAM
MC34844
INTERNAL BLOCK DIAGRAM
Figure 3. 34844 Simplified Internal Block Diagram
VIN
VDC1
COMP
EN
CK
PWM
SCK
SDA
ISET
PIN
NIN
SWA
SWB
PGNDA
FAIL
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
TEMP/OPTO
LOOP CONTROL
CURRENT DAC
OCP/OTP/UVLO
PWM GENERATOR
10 CHANNEL
OVP
BOOST
CLOCK/PLL
CONTROLLER
50 mA CURRENT
MIRROR
V SENSE
GND
A0/SEN
PGNDB
LDO
VDC3
VDC2
SLOPE
I2C INTERFACE
VOUT
M/~S
Analog Integrated Circuit Device Data
Freescale Semiconductor 6
34844
PIN CONNECTIONS
MC34844
PIN CONNECTIONS
Figure 4. 34844 Pin Connections
Table 2. 34844 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.
Pin Number Pin Name Pin Function Formal Name Definition
1VIN Power Input voltage Input supply
2 PGNDB Power Power Ground Power ground
3SWB Input Switch node B Boost switch connection B
4SWA Input Switch node A Boost switch connection A
5 PGNDA Power Power Ground Power ground
6A0/SEN Input Device Select Address select, device select pin or OVP HW control
7EN Input Enable Enable pin (active high, internal pull-up)
8 - 17 I0-I9 Input LED Channel LED string connections
18 FAIL Open Drain Fault detection Fault detected pin (open drain):
No Failure = Low-impedance
Failure = High-impedance
19 ISET Passive Current set LED current setting resistor
20 PIN Input Positive current scale Positive input analog current control
21 NIN Input Negative current scale Negative input analog current control
22 SLOPE Passive Boost Slope Boost slope compensation Setting resistor
23 VDC3 Output Internal Regulator 3 Decoupling capacitor for internal phase locked loop power
24 CK Input/Output Clock signal Clock synchronization pin (input for M/~S = low - internal pull-up, output
for M/~S = high)
VIN
PGNDB
SWB
SWA
PGNDA
A0/SEN
EN
IO
CK
VDC3
SLOPE
NIN
PIN
ISET
FAIL
I9
VOUT
VDC2
M/~S
COMP
VDC1
SCK
SDA
PWM
I1 I2 I3 I4 I5 I6 I7 I8
2532 31 30 29 28 27 26
24
17
18
19
20
21
22
23
1
8
7
6
5
4
3
2
169 101112131415
QFN - EP
5.0 MM X 5.0 MM
32 LEAD
EP GND
EP = Exposed Pad
TRANSPARENT
TOP VIEW
Analog Integrated Circuit Device Data
7Freescale Semiconductor
34844
PIN CONNECTIONS
MC34844
25 PWM Input External PWM External PWM input (internal pull-down)
26 SDA Bidirectional I2C data I2C data Line
27 SCK Bidirectional I2C clock I2C clock line
28 VDC1 Output Internal Regulator 1 Decoupling capacitor for internal logic rail
29 COMP Passive Compensation pin Boost converter Type compensation pin
30 M/~S Input Master/Slave selector Selects Master mode (1) or Slave mode (0)
31 VDC2 Output Internal Regulator 2 Decoupling capacitor for internal regulator
32 VOUT Input Voltage Output Boost Output voltage sense pin
EP GND -Ground Ground Reference for all internal circuits other than Boost FET
Table 2. 34844 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.
Pin Number Pin Name Pin Function Formal Name Definition
Analog Integrated Circuit Device Data
Freescale Semiconductor 8
34844
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
MC34844
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
ELECTRICAL RATINGS
Maximum Pin Voltages
A0/SEN
I0, I1, I2, I3, I4, I5, I6, I7, I8, I9,EN(5)
VIN
SWA, SWB, VOUT
FAIL, PIN, NIN, ISET, M/~S, CK, PWM
VMAX
7.0
45
30
65
6.0
V
Maximum LED Current IMAX 55 mA
ESD Voltage(2)
Human Body Model (HBM)
Machine Model (MM)
VESD
+2000
+200
V
THERMAL RATINGS
Ambient Temperature Range TA-40 to 105 °C
Junction to Ambient Temperature(3) TθJA 32 °C/W
Junction to Case Temperature(3) TθJC 3.5 °C/W
Maximum junction temperature TJ150 °C
Storage temperature range TSTO -40 to 150 °C
Peak Package Reflow Temperature During Reflow(4) TPPRT 260 °C
Power Dissipation
TA = 25 °C
TA = 70 °C
TA = 85 °C
TA = 105 °C
3.9
2.5
2.0
1.4
W
Notes
2. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2), and the Machine Model (MM) (AEC-Q100-
003), RZAP = 0 Ω
3. Per JEDEC51 Standard for Multilayer PCB
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
5. 45 V is the Maximum allowable voltage on all LED channels in off-state.
Analog Integrated Circuit Device Data
9Freescale Semiconductor
34844
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Static and Dynamic Electrical Characteristics
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1,
PIN & NIN = VDC1, - 40 °C ≤ TA ≤ 105 °C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SUPPLY
Supply Voltage VIN 7.0 12 28 V
Supply Current when Shutdown Mode
Manual & SM Bus: EN = Low, SCK & SDA=Low
I2C: EN = Low, SETI2C bit = 1, CLRI2C bit = 0
ISHUTDOWN
-
-
2.0
17
-
-
μA
Supply Current when Sleep Mode
SM-Bus: EN = low, SCK & SDA= Active, SETI2C bit = 0, EN bit = 0
I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 0
ISLEEP -3.0 -mA
Supply Current when Operational Mode
Manual: EN= High, SCK & SDA=Low, PWM=Low
SM-Bus: EN= Low, SCK & SDA=Active, EN bit= 1, PWM=Low
I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 1, PWM=Low
IOPERATIONAL -10.0 -mA
Under-voltage Lockout
VIN Rising
UVLO 5.4 6.0 6.4 V
Under-voltage Hysteresis
VIN Falling
UVLOHYST 150 200 250 mV
VDC1 Voltage(6)
CVDC1 = 2.2 μF
VDC1 2.4 2.5 2.6 V
VDC2 Voltage(6)
CVDC2 = 2.2 μF
VDC2 5.5 6.0 6.5 V
VDC3 Voltage(6)
CVDC3 = 2.2 μF
VDC3 2.4 2.5 2.6 V
BOOST
Output Voltage Range(7)
VIN = 7.0 V
VIN = 28 V
VOUT1
VOUT2
8.0
31
-
-
43
60
V
Boost Switch Current Limit IFET 2.3 2.5 2.7 A
RDSON of Internal FET
IDRAIN= 1.0 A
RDSON -250 500 mΩ
Boost Switch Off-state Leakage Current
VSWA,SWB = 65 V
IBOOST_LEAK - - 10 μA
Peak Boost Efficiency(8) EFFBOOST -90 - %
Notes
6. This output is for internal use only and not to be used for other purposes. A 1.0 kΩ resistor between the VDC3 and VDC1 pin is
recommended for <-20 °C operation.
7. Minimum and Maximum output voltages are dependent on Min/Max duty cycle condition.
8. Guaranteed by design
Analog Integrated Circuit Device Data
Freescale Semiconductor 10
34844
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844
Line Regulation (9)
VIN=7.0 to 28 V
IOUT/VIN -0.2 -0.2 %/V
Load Regulation (9)
VLED = 8.0 to 65 V (all Channels)
IOUT/VLED -0.2 -0.2 %/V
Slope compensation voltage ramp
RSLOPE = 68 kΩ
VSLOPE -0.49 -V/μs
Current Sense Amplifier Gain ACSA -9.0 -
Current Sense Resistor RSENSE -22 - mΩ
OTA Transconductance GM-200 -μS
Transconductance Sink and Source Current Capability ISS -100 -μA
Output Voltage Precharge VHOLD 0.45 0.5 0.55 V
FAIL PIN
Off-state Leakage Current
VFAIL = 5.5 V
IFAIL_LEAK - - 5 μA
On-state Voltage Drop
ISINK = 4.0 mA
VOL - - 0.4 V
LED CHANNELS
Sink Current
ICHx Register = 255, RISET=5.1 kΩ 0.1%, PIN&NIN = Disabled,
TA=25 °C
ISINK 49 50 51 mA
Regulated minimum voltage across drivers
Pulse Width > 4.0 μs
VMIN 675 750 825 mV
Current Matching Accuracy IMATCH -2.0 -2.0 %
ISET Pin Voltage
RISET=5.1 kΩ 0.1%
VSET 2.017 2.048 2.079 V
LED Current Amplitude Resolution
1.0 mA < ILED < 50 mA
ILEDRES -1.5 - %
Off-state Leakage Current, All channels
(VCH = 45 V)
ICH_LEAK - - 10 μA
PIN INPUT
Voltage to Disable PIN mode VPIN_DIS 2.2 - - V
PIN Bias Current
PIN = VSET
IPIN -2.0 -2.0 μA
Analog Dimming Current
ICHx Register = 255, RISET=5.1 kΩ 0.1%
PIN = VSET/2
PIN = VSET
IDIM_PIN
23.75
47.50
25
50
26.25
52.50
mA
Notes
9. Guaranteed by design
Table 4. Static and Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1,
PIN & NIN = VDC1, - 40 °C ≤ TA ≤ 105 °C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
11 Freescale Semiconductor
34844
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844
NIN INPUT
Voltage to Disable NIN mode VNIN_DIS 2.2 - - V
NIN Bias Current
NIN = VSET
ININ -2.0 -2.0 μA
Analog Dimming Current
ICHx Register = 255, RISET=5.1 kΩ 0.1%
NIN = VSET/2
NIN = 0 V
IDIM_NIN
23.75
47.50
25
50
26.25
52.50
mA
OVER-TEMPERATURE PROTECTION
Over-temperature Threshold(10)
Rising
Hysteresis
OTT
150
-
165
25
175
-
°C
I2C/SM BUS PHYSICAL LAYER [SCK, SDA]
I2C Address ADRI2C -1110110 -Binary
SM-Bus Address ADRSMB -1110110 -Binary
Input Low Voltage VILI -0.3 -0.8 V
Input High Voltage VIHI 2.1 -5.5 V
Input Hysteresis VHYSI 0.3 - - V
Output Low Voltage
Sink Current < 4.0 mA
VOLI - - 0.4 V
Input Current IINI -5.0 -5.0 μA
Input Capacitance(10) CINI - - 10 ρF
LOGIC INPUTS / OUTPUTS (CK, M/~S, PWM, A0/SEN)
Input Low Voltage VILL -0.3 -0.5 V
Input High Voltage VIHL 1.5 -5.5 V
Input Hysteresis VHYSL -0.1 - V
Input Current IIIL -5.0 -5.0 μA
Output Low Voltage (CK)
ISINK < 2.0 mA
VOLL - - 0.2 V
Output High Voltage (CK)
ISOURCE < 2.0 mA
VOHL 2.2 -5.5 V
Input Capacitance(10) CINI - - 5.0 ρF
Notes
10. Guaranteed by design
Table 4. Static and Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1,
PIN & NIN = VDC1, - 40 °C ≤ TA ≤ 105 °C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 12
34844
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844
OVER-VOLTAGE PROTECTION
Over-voltage Clamp - OVP Register Table:
OVP = Fh OVPFH 60.5 62.5 64.5 V
OVP = Eh OVPEH 56.5 58 60 V
OVP = Dh OVPDH 53 54 56 V
OVP = Ch OVPCH 49 51 52.5 V
OVP = Bh OVPBH 45 47 48.5 V
OVP = Ah OVPAH 41 43 44.5 V
OVP = 9h OVP9H 38 39 40.5 V
OVP = 8h OVP8H 34 36 37.5 V
OVP = 7h OVP7H 30.5 32 33.5 V
OVP = 6h OVP6H 26 28 30 V
OVP = 5h OVP5H 23 24 25 V
OVP = 4h OVP4H 19 20 21 V
OVP = 3h OVP3H 15 16 17 V
OVP = 2h OVP2H 11 12 13 V
Over-voltage threshold,
Set by Hardware, Voltage at A0/SEN
OVPHW 6.15 6.5 6.85 V
A0/SEN Sink Current ISINK_OVP -100 -μA
BOOST
Switching Frequency (BST [1:0]=0) fSW0 0.14 0.15 0.17 MHz
Switching Frequency (BST [1:0]=1) fSW1 0.27 0.30 0.33 MHz
Switching Frequency (BST [1:0]=2) fSW2 0.54 0.60 0.66 MHz
Switching Frequency (BST [1:0]=3) fSW3 1.08 1.2 1.32 MHz
Minimum Duty Cycle DMIN -10 15 %
Maximum Duty Cycle DMAX 80 85 - %
Soft Start Period tSS -6.5 -ms
Boost Switch Rise Time(10) tTR -15 -ns
Boost Switch Fall Time(10) tF-25 -ns
Notes
11. Guaranteed by design
Table 4. Static and Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1,
PIN & NIN = VDC1, - 40 °C ≤ TA ≤ 105 °C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
13 Freescale Semiconductor
34844
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844
PWM GENERATOR
PWM Frequency Range (13)
M/~S = Low (Slave Mode)
fPWMS100 -25000 Hz
PWM Frequency
M/~S = High (Master Mode)
FPWM Register = 768
FPWM Register = 192,000
fPWMM
22500
90
25000
100
27500
110
Hz
PWM dimming resolution tfPWM -0.39 - %
PWM PIN (DIRECT PWM CONTROL)
Input PWM Pin Minimum Pulse(13) tPWM_IN 150 - - ns
Input PWM Frequency Range fPWM 100 -23000 Hz
PHASE LOCK LOOP
CK Slave Mode Frequency Lock Range(12)
M/~S = Low (Slave Mode)
fCKS100 -25000 Hz
CK Slave Mode Input Jitter(13)
M/~S = Low (Slave Mode)
fCKS_JITTER - - 0.1 %
Slave Mode Acquisition Time
M/~S = Low (Slave Mode)
FPWMS=25 kHz
FPWMS=100 Hz
TS_ACQ
-
-
-
2000
50
-
ms
ms
CK Frequency (Master Mode)
FPWM Register = 768
FPWM Register = 192,000
fCKMASTER
22500
90
25000
100
27500
110
Hz
I2C/SM BUS PHYSICAL LAYER [SCK, SDA]
Interface Frequency Range fSCK 400 kHz
SM Bus Power-on-Reset Time tRST - - 100 ms
Output fall time
10 ρF < CL < 400 ρF
tF40 -160 ns
Output rise time
10 ρF<CL<400 ρF
tR20 -80 ns
LOGIC OUTPUT (CK)
Output Rise and Fall time(12)
CL<100 ρF
tR/tF- - 25 ns
LED CHANNELS
Channels Rise and Fall Time(13) tR/tF-23 50 ns
Notes
12. Special considerations should be made for frequencies between 100 Hz to 1.0 KHz. Please refer to Functional Device Operation for
further details.
13. Guaranteed by design
Table 4. Static and Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, ILED = 50 mA, PWM = VDC1, M/~S = VDC1,
PIN & NIN = VDC1, - 40 °C ≤ TA ≤ 105 °C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 14
34844
FUNCTIONAL DESCRIPTION
INTRODUCTION
MC34844
FUNCTIONAL DESCRIPTION
INTRODUCTION
LED backlighting has become very popular for small and
medium LCDs, due to some advantages over other
backlighting schemes, such as the widely used cold cathode
fluorescent lamp (CCFL). The advantages of LED
backlighting are low cost, long life, immunity to vibration, low
operational voltage, and precise control over its intensity.
However, there is an important drawback of this method. It
requires more power than most of the other methods, and this
is a major problem if the LCD size is large enough.
To address the power consumption problem, solid state
optoelectronics technologies are evolving to create brighter
LEDs with lower power consumption. These new
technologies together with highly efficient power
management LED drivers are turning LEDs, a more suitable
solution for backlighting almost any size of LCD panel, with
really conservative power consumption.
One of the most common schemes for backlighting with
LED is the one known as “Array backlighting”. This creates a
matrix of LEDs all over the LCD surface, using defraction and
diffused layers to produce an homogenous and even light at
the LCD surface. Each row or column is formed by a number
of LEDs in series, forcing a single current to flow through all
LEDs in each string.
Using a current control driver, per row or column, helps the
system to maintain a constant current flowing through each
line, keeping a steady amount of light even with the presence
of line or load variations. They can also be use as a light
intensity control by increasing or decreasing the amount of
current flowing through each LED string.
To achieve enough voltage to drive a number of LEDs in
series, a boost converter is implemented, to produce a higher
voltage from a smaller one, which is typically used by the
logical blocks to do their function.
The 34844 implements a single channel boost converter
together with 10 input channels, for driving up to 16 LEDs per
string to create a matrix of more than 160 LEDs. Together
with its 90% efficiency and I2C programmable or external
current control, among other features, makes the 34844 a
perfect solution for backlighting small and medium size LCD
panels, on low power portable and high definition devices.
FUNCTIONAL PIN DESCRIPTION
INPUT VOLTAGE SUPPLY (VIN)
IC Power input supply voltage, is used internally to
produce internal voltage regulation (VDC1, VDC3) for logic
functioning, and also as an input voltage for the boost
regulator.
INTERNAL VOLTAGE REGULATOR 1 (VDC1)
This pin is for internal use only, and not to be used for other
purposes. A capacitor of 2.2 μF should be connected
between this pin and ground for decoupling purposes.
INTERNAL VOLTAGE REGULATOR 2 (VDC2)
This pin is for internal use only, and not to be used for other
purposes. A capacitor of 2.2 μF should be connected
between this pin and ground for decoupling purposes.
INTERNAL VOLTAGE REGULATOR 3 (VDC3)
This pin is for internal use only, and not to be used for other
purposes. A capacitor of 2.2 μF should be connected
between this pin and ground for decoupling purposes. A
1.0 kΩ resistor between the VDC3 and VDC1 pin is
recommended for <-20 °C operation.
BOOST COMPENSATION PIN (COMP)
Passive pin used to compensate the boost converter. Add
a capacitor and a resistor in series to GND to stabilize the
system.
IC ENABLE (EN)
The active high enable pin is internally pulled high through
pull-up resistors. Applying 0 V to this pin would stop the IC
from working.
INPUT/OUTPUT CLOCK SIGNAL (CK)
This pin can be used as an output clock signal (master
mode), or input clock signal (slave mode), to synchronize
more than one device.
MASTER/SLAVE MODE SELECTION (M/~S)
Setting this pin High puts the device into Master mode,
producing an output synchronization clock at the CK pin.
Setting this pin low, puts the device in Slave mode, using the
CK pin as an input clock.
EXTERNAL PWM INPUT (PWM)
This pin is internally pulled down. An external PWM signal
can be applied to modulate the LED channel directly in
absence of an I2C interface.
CLOCK I2C SIGNAL (SCK)
Clock line for I2C communication.
ADDRESS I2C SIGNAL (SDA)
Address line for I2C communication.
Analog Integrated Circuit Device Data
15 Freescale Semiconductor
34844
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
MC34844
A0/SEN
Address select, device select pin, or Hardware Over-
voltage Protection (OVP) Control.
CURRENT SET (ISET)
Each LED string can drive up to 50 mA. The maximum
current can be set by using a resistor from this pin to GND.
POSITIVE CURRENT SCALING (PIN)
Positive current scaling factor for the external analog
current control. Applying 0 V to this pin, scales the current to
near 0%, and in the same way, applying 2.048 V (Vset), the
scale factor is 100%. By applying a voltage higher than 2.2 V,
the scaling factor is disabled, and the internal pull-ups are
activated.
If PIN pin and NIN pin are used at the same time then by
applying 0 V to the PIN pin and 2.048 V to NIN pin, scales the
current to near 0%, and in the same way, applying 2.048 V to
the PIN pin and 0 V to NIN pin, scales the current to 100%.
By applying a voltage higher than 2.2 V, the scaling factor is
disabled and the internal pull-ups are activated in both pins.
NEGATIVE CURRENT SCALING (NIN)
Negative current scaling factor for the external analog
current control. Setting 0 V to this pin scales the current to
100%, in the same way, setting 2.048 V (Vset) the scale
factor is near 0%. By applying a voltage higher than 2.2 V, the
scaling factor is disabled and the internal pull-ups are
activated.
If PIN pin and NIN pin are used at the same time then by
applying 0 V to the PIN pin and 2.048 V to NIN pin, scales the
current near 0%, and in the same way, applying 2.048 V to
the PIN pin and 0 V to NIN pin, scales the current to 100%.
By applying a voltage higher than 2.2 V, the scaling factor is
disabled and the internal pull-ups are activated in both pins.
GROUND (GND)
Ground Reference for all internal circuits other than the
Boost FET.
The Exposed Pad (EP) should be used for thermal heat
dissipation.
I0-I9
Current LED driver, each line has the capability of driving
up to 50 mA.
FAULT DETECTION PIN (FAIL)
When a fault situation is detected, this pin goes into high
impedance.
BOOST SLOPE COMPENSATION SETTING
RESISTOR (SLOPE)
Use an external resistor of about 68 kΩ to configure the
Boost compensation slope.
POWER GROUND PINS (PGNDA, PGNDB)
Ground pin for the internal Boost FET.
OUTPUT VOLTAGE SENSE PIN (VOUT)
Input pin to monitor the output voltage. It also supplies the
input voltage for the internal regulator 2 (VDC2).
SWITCHING NODE PINS (SWA, SWB)
Switching node of boost converter.
Analog Integrated Circuit Device Data
Freescale Semiconductor 16
34844
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 5. Functional Internal Block Diagram
REGULATORS/ POWER DOWN
The 34844 is designed to operate from input voltages in
the 7.0 to 28 V range. This is stepped down internally by
LDOs to 2.5 V (VDC1 and VDC3) and 6 V (VDC3) for
powering internal circuitry. If the input voltage falls below the
UVLO threshold, the device automatically enters in power
down mode.
Operating Modes:
The device can be operated by the EN pin and/or SDA/
SCK bus lines, resulting in three distinct operation modes:
• Manual mode, there is no I2C capability, the bus line pins
must be tied low, and the EN pin controls the ON/OFF
operation.
• SM Bus mode, EN pin must be tied low and the device is
turned ON by any activity on the bus lines. The part shuts
down if the bus lines are held low for more than 27 ms, the
27 ms watchdog timer can be disabled by I2C (setting
SETI2C bit high) or tying the EN pin high. In Sleep mode
(EN bit=0) the device reduces the power consumption by
leaving “alive” only the blocks required for I2C
communication.
•I
2C mode, has to be configured by I2C communication
(SETI2C bit = 1) right after the IC is turned ON, it prevents
the part from being turned ON/OFF by the bus. Sleep
mode is also present and it is intended to save power, but
still keep the IC prepared to communicate by I2C. Turning
the EN pin OFF, the chip enters into a low power mode.
MC34844 - Functional Block Diagram
Regulator / Power down Protection / Failure Detection
LED Channels
LED Channels
Logic Control
Regulators / Power Down
3 Internal Regulators
Protection / Failure Detection
Logic Control
Serial Interface Control
Boost
Boost
Optical and Temperature Control
PWM Dimming
Over-temperature Protection
LED Open Protection
Over-current Protection
Under-voltage Protection
Over-voltage Protection
Analog Integrated Circuit Device Data
17 Freescale Semiconductor
34844
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844
BOOST
The integrated boost converter operates in non-
synchronous mode and integrates a 2.5 A FET. An integrated
sense circuit is used to sense the voltage at the LED current
mirror inputs and automatically sets the boost output voltage
(DHC) to the minimum voltage needed to keep all LEDs
biased with the required current. The DHC is designed to
operate under specific pulse width conditions in the LED
drivers. It operates for pulse widths higher than 4.0 μs
If the pulse widths are shorter than specified, the DHC
circuit will not operate and the voltage across the LED drivers
will increase to a value given by the OVP minus the total LED
voltage in the LED string. Therefore it is imperative to select
the proper OVP level to minimize power dissipation.
The OVP can be set from 11 to 62 V, ~4.0 V spaced, using
the I2C interface (OVP Register). If I2C capability is not
present, the OVP can be controlled by a resistor divider
connected from VOUT to GND with its mid point tied to A0/
SEN pin (threshold = 6.5 V). During an OVP condition, the
output voltage will go to the OVP level which is programmed
via the I2C interface or settled by a resistor divider on A0/SEN
pin, or by a zener diode. The formulas to calculate the
hardware OVP using any of the two methods are as follows:
HARDWARE OVP:
The OVP value should be set to greater than the maximum
LED voltage over the whole temperature range. A good
practice is to set it 5.0 V or so above the max LED voltage.
The boost converter also features internal Over-current
Protection (OCP) and has a user programmable Over-
voltage Protection (OVP).
The OCP operates on a cycle by cycle basis. However, if
the OCP condition remains for more than 10 ms then the
device turns off the LED Drivers, the Boost goes to Sleep
mode and the output FAULT pin goes into high-impedance.
The device can only be restarted by recycling the enable or
creating a Power On Reset (POR).
The user can program the boost frequency by I2C
(BST[1:0]) only after the IC is powered up and before the
boost circuit is turned ON for the first time (PWM pin low to
high). This sequence avoids boost frequency to be changed
inadvertently during operation. The first I2C command has to
wait for 5.0 ms after the part is turned ON, in order to allow
sufficient time for the device power up sequence to be
completed.
The boost controller has an integral track and hold
amplifier with indefinite hold time capability, to enable
immediate LED on cycles after extended off times. During
extended off times, the external LEDs cool down from their
normal quiescent operating temperature and thereby
experience a forward voltage change, typically an increase in
the forward voltage. This change can be significant for
applications with a large number of series LEDs in a string
operating at high current. If the boost controller did not track
this increased change, the potential on the LED drivers would
saturate for a few cycles once the LED channels are re-
enabled.
Table 5. Operation Current Consumption Modes
Mode EN Pin SCK/SDA Pins I2C Bit Command Current Consumption
Mode Comments
Manual Low Low N/A Shutdown
High Low N/A Operational
SM Bus
Low Low (> 27 ms) EN bit = X Shutdown
Low Active EN bit = 0 Sleep
Low Active EN bit = 1 Operational
I2C
Low X
SETI2C bit = 1
I2C Low Power
(Shutdown)
Part Doesn’t
Wake-up
CLRI2C bit = 0
EN bit = X
High X
SETI2C bit = 1
SleepCLRI2C bit = 0
EN bit = 0
High X
SETI2C bit = 1
OperationalCLRI2C bit = 0
EN bit = 1
VOUT
Method 1 Method 2
A0/SEN
A0/SEN
OVP = VZENER2 + 6.5 V
OVP = 6.5 V [(RUPPER / RLOWER) + 1] + (100E-6 x RUPPER)
RUPPER
RLOWER
VZENER2
Analog Integrated Circuit Device Data
Freescale Semiconductor 18
34844
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844
Also the device has a precharge voltage that add 0.5 Volts
to the Boost, cycle by cycle of the PWM. It helps the boost to
respond faster every time the load turns back on again.
CURRENT MIRROR
The programmable current mirror matches the current in
10 LED strings to within 2%. The maximum current is set
using a resistor to GND from the ISET pin. This can be scaled
down using the I2C interface to 255 levels.
Zero current is achieved by turning off the LED Driver by
I2C (registers CHENx = 0 h) for a duty cycle from 0% to 99%
or by pulling PWM pin low regardless of the duty cycle.
I2C capability allows the channels to be controlled
individually or in parallel.
Current on LED Channel (PIN and NIN mode disabled) Eqn. 1
In the off state, the LEDs current is set to 0 and the boost
converter stops switching.
This feature allows to drive more than 50 mA of current by
connecting the LED string to 2 or more LED channels in
parallel. For example; if the application requires to drive 5
channels at 100 mA, then the bottom of each LED string
should be connected to two channels in order to duplicate the
current capability (Example: CH0+CH1 = 100 mA).
PWM GENERATOR
The PWM generator can operate in either master or slave
modes, as set by the M/~S pin.
In master mode, the internal PWM generator frequency is
programmed through the I2C interface (registers FPWM).
The default programmed value set the number of 25 kHz
clocks (40 μs) in one PWM cycle. The 18-bit resolution allows
minimum PWM frequencies of 100 Hz to be programmed.
The resulting frequency is output on the CK pin.
PWM Frequency Eqn. 2
In slave mode, the CK pin acts as an input. The internal
digital PLL uses this frequency as the PWM frequency. By
setting one device as master, and connecting the CK output
to the input on a number of slave configured devices, all
PWM frequencies are synchronized together.
The duty cycle of the PWM waveform in both master and
slave modes is set using a second register on the I2C
interface (register DPWM), and can be controlled from 100%
duty cycle to 1/256 TPWM = 0.39%. Zero percent of duty cycle
is achieved by turning LED drivers off (register CHENx = 0h)
or pulling PWM pin low.
An external PWM can also be used. The PWM input is
'AND'ed with the internal signal. By setting the serial interface
to 100% duty cycle (default), the external pin has full control
of the PWM duty cycle. This pin can also be used to modulate
the LED at a lower frequency than the PWM dimming
frequency (Minimum pulse width = 150 ns).
A pulsed mode can also be programmed using the I2C
interface (STROBE bit = 1). In this mode, each rising edge of
the PWM signal turns on the next channel, while turning off
all other channels. The duration that the channel is
illuminated is set by the duty cycle of the PWM input pin. This
can be used to scan the output channels.
DISABLING LED CHANNELS
The 34844 allows the user to enable and disable each of
the 10 channels separately by writing the corresponding
CHENx bit on Registers 08 and 09 thru I2C.
When a channel is disabled thru the I2C prior the device
starts to operate, the corresponding LED driver is disabled
but the feedback circuit is still connected. This may interfere
with the operation of the dynamic headroom control (DHC)
which can lead to erratic output voltage regulation. For this
condition, the output voltage may ramp up to the OVP level if
the voltage on the LED driver is not substantially above the
DHC regulation voltage (0.75 V typ). Because of this
operation under I2C/SMBUS Mode, we recommend to
connect the unused channels to VDC2 thru a100 kohm
resistor and also follow the below powering up sequence:
1. PWM pin = Low.
2. Power up the part.
3. Program the I2C commands and disable the unused
channels.
4. Enable the Boost and current drivers by taking PWM
pin to HIGH.
This previous device's operation does not happen when all
channels are being used because the voltage across the LED
drivers is always equal or higher than the DHC regulation
voltage (0.75 V typ). For this condition, the user can disable/
enable any of the channels thru I2C without causing any
erratic behavior but the FAIL pin cannot be cleared. If FAIL
pin is to be cleared thru I2C, it will be necessary to use the
suggested configuration shown at the FAIL PIN session.
FAIL PIN
If a LED fails open in any of the LED strings, the voltage in
that particular LED channel will be close to ground and the
LED open failure is detected. When this happens, a failure is
registered, the FAIL pin is set to its high-impedance stage,
and the channel is turned off.
The FAIL pin cannot be cleared for manual mode unless a
complete power on reset is applied. However for I2C/SMBUS
mode, the FAIL pin is cleared by disabling the malfunction
channels (CHENx = 0) and clearing the failure bit (CLRFAIL
bit = 1).
If the application only requires clearing the failure for the
floating or unused channels, then the unused channels must
be connected to VDC2 thru a 100 kohm resistor to avoid
reach instability problems. This will allow detecting another
failure from the connected channels. (See Figure 6)
Current A[] ICH RegisterValue[]
RSET ohms[]
-----------------------------------------------------------=
PWMFrequency Hz[] 19.2Mhz
FPWM RegisterValue[]
--------------------------------------------------------------------=
Analog Integrated Circuit Device Data
19 Freescale Semiconductor
34844
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844
Figure 6. Single Channel Disconnect Circuit.
For applications where multiple failure detection is
required, then one 100 kohm resistor must be placed from
each channel to a diode (D2) connected to VDC2. The
resistor will provide a pull up voltage to the disconnected
channels so that they do not interfere with the DHC circuit.
The diode (D2) ensures that when the connected channels
are in PWM off state the LED strings do no conduct current
to VDC2. (See Figure 7)
Figure 7. Resistor/Diode placement for multiple open
circuit detection
If the fail pin cannot be cleared by software then it indicates
that the failure is because of t an over-current in the Boost.
Since this is a critical failure the only way to clear it is by
releasing the part from the over-current condition and then
shutdown the part (Refer to Table 5)
If I2C communication is not present, FAIL condition should
be reset by removing the failure and re-enabling the device
thru the EN pin.
OPTICAL AND TEMPERATURE CONTROL LOOP
The 34844 supports both optical and temperature loop
control.
For temperature loop control, the LED brightness can be
adjusted depending on the temperature of the LEDs.
For optical loop control, the 34844 supports both optical
closed loop backlight control, where the brightness of the
backlight is maintained at a required level by adjusting the
light output, until the desired level is achieved, or with
ambient light control, where the backlight brightness
increases as ambient light increases.
Both temperature and optical loops are supported through
the PIN and NIN pins. Each pin supports a 0-2.048 V input
range which affects the current through the LEDs. The PIN
pin increases current as the voltage rises from 0-2.048 V.
The NIN pin reduces current as the voltage rises from 0-
2.048 V.
A 10.2 k resistor or higher value must be used at the ISET
pin if the part is configured to use PIN+NIN control loop
functionality, the 50 mA maximum current is achieved at the
higher allowed level of PIN/NIN pins, ensuring the maximum
current of the LED Drivers are not exceeded.
The optical and temperature control loop can be disabled
by I2C setting bits (PINEN & NINEN), or by tying PIN and NIN
pins high (>2.2 V) it is called VSET mode, and the LED Driver
maximum current is set to 50 mA by using a 5.1 k resistor at
the ISET pin.
Current on LED Channel (PIN mode) Eqn. 3
Current on LED Channel (NIN mode) Eqn. 4
Current on LED Channel (PIN+NIN mode) Eqn. 5
LED FAILURE PROTECTION
Open LED Protection
If LED fails open in any of the LED strings, the voltage in
that channel will be pulled close to zero, which will cause the
channel to be disabled. As a result, the boost output voltage
will go to the OVP level and then come down to the regulation
level to continue powering the rest of the LED strings.
Short LED Protection
If an LED shorted in any of the LED strings, the device will
continue to operate without interruption. However, if the
Current A[] VPIN ICH RegisterValue[]
×()
RSET ohms[]
2×
----------------------------------------------------------------------------------------=
Current A[] 2.048 VNIN–()ICH RegisterValue[]
×
RSET ohms[]2×
-------------------------------------------------------------------------------------------------------------=
Current A[] 2.048 VNIN–VPIN+()ICH RegisterValue[]
×
RSET ohms[]2×
-----------------------------------------------------------------------------------------------------------------------------------=
Analog Integrated Circuit Device Data
Freescale Semiconductor 20
34844
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844
shorted LED happens to be in the LED string with the highest
forward voltage, the DHC circuit will automatically regulate
the output voltage with respect to the new highest LED
voltage. If more LEDs are shorted in the same LED string, it
may cause excessive power dissipation in the channel which
may cause the OTT circuit to trip which will completely
shutdown the device.
OVER-TEMPERATURE PROTECTION
The 34844 has an on-chip temperature sensor that
measures die temperature. If the IC temperature exceeds the
OTT threshold, the IC will turn off all power sources inside the
IC (LED drivers, boost and internal regulators) until the
temperature falls below the falling OTT threshold. Once it
comes back on, it will operate with the default configuration
(refer to Table 7).
SERIAL INTERFACE CONTROL
The 34844 uses an I2C interface capable of operating in
standard (100 kHz) or fast (400 kHz) modes.
The A0/SEN pin can be used an address select pin to
allow more than 2 devices in the system. The A0/SEN pin
should be held low on all chips expect the one to be
addressed, where it is taken HIGH.
Analog Integrated Circuit Device Data
21 Freescale Semiconductor
34844
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
MC34844
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
NORMAL MODE
In normal operation the 34844 is programed via I2C to
drive up to 50 mA of current through each one of the LED
channels. The 34844 can be configured in master or slave
mode as set by the M/~S pin.
In Master mode, the internal PWM generator frequency is
programmed through the I2C interface. The programmed
value sets the number of 25 kHz clocks (40μs) in one PWM
cycle. The 18-bit resolution allows minimum PWM
frequencies of 100 Hz to be programmed. The resulting
frequency is output on the CK pin.
In slave mode, the CK pin acts as an input. The internal
digital PLL uses this frequency as the PWM frequency.
By setting one device as a master, and connecting the CK
output to the input on a number of slave configured devices,
all PWM frequencies are synchronized together. For this
application A0/SEN pin indicates which device is enable for
I2C control.
In Slave mode, an internal phase lock loop will lock the
internal PWM generator period to the period of the signal
present at the CK pin. The PLL can lock to any frequency
from 100 Hz to 25 KHz provided the jitter is below 1000 ppm.
At frequencies above 1.0 KHz, the PLL will maintain lock
regardless of the transient power conditions imposed by the
user (i.e. going from 0% duty cycle to 100% at 20W LED
display power). Below 1.0 kHz, thermal time constants on the
die are such that the PLL may momentarily lose lock if the die
temperature changes substantially during a large load power
step. As explained below, this anomaly can be avoided by
controlling the rate of change in PWM duty cycle.
To better understand this issue, consider that the on chip
PLL uses a VCO that is subject to thermal drift on the order
of 1000 ppm/C. Further consider that the thermal time
constant of the chip is on the order of single digit
milliseconds. Therefore, if a large power load step is imposed
by the user (i.e. going from 0% duty cycle to 100% duty cycle
with a load power of 20 W), the die will experience a large
temperature wave gradient that will propagate across the
chip surface and thereby affect the instantaneous frequency
of the VCO. As long as such changes are within the
bandwidth of the PLL, the PLL will be able to track and
maintain lock. Exceeding this rate of change may cause the
PLL to lose lock and the backlight will momentarily be
blanked until lock is reacquired.
At 100 Hz lock, the PLL has a bandwidth of approximately
10 Hz. This means that temperature changes on the order of
100 ms are tolerable without losing lock. But full load power
changes on the order of 10 ms (i.e. 100 Hz PWM) are not
tracked out and the PLL can momentarily lose lock. If this
happens, as stated above, the LED drivers are momentarily
disabled until lock is reacquired. This will be manifested as a
perceivable short flash on the backlight immediately after the
load change.
To avoid this problem, one can simply limit large
instantaneous changes in die temperature by invoking only
small power steps when raising or lowering the display power
at low PWM frequencies. For example, to maintain lock while
transitioning from 0% to 100% duty cycle at 20 W load power
and a PWM frequency of 100 Hz would entail stepping the
power at a rate not to exceed 1% per 10 ms. If a load of less
than 20 W is used, then the rate of rise can be increased. As
the locked PWM frequency increases (i.e. use 600 Hz
instead of 100 Hz), the step rate can be further increased to
approximately 4% per 2.0 ms. The exact step rate to avoid
loss of PLL lock is a function of essentially three things: (a)
the composite thermal resistance of the user's PCB
assembly, (b) the load power, and (c) the PWM frequency.
For all cases below 1.0 KHz, simply using a rate of 1% duty
cycle change per PWM period will be adequate. If this is too
slow, the value can be optimized experimentally once the
hardware design is complete. At PWM rates above 1.0 KHz,
it is not necessary to control the rate of change in PWM duty
cycle.
It is important to point out that when operating in the
master mode, one does not need to concern themselves with
loss of lock since the reference clock and the VCO clock are
collocated on the die, and therefore experience the same
thermal shift. Hence in master mode, once lock is initially
acquired, it is not lost and no blanking of the display occurs.
The duty cycle of the PWM in both master and slave mode
is set using a second register on the I2C interface.
An external PWM signal can also be applied in the PWM
pin. This pin is AND’ed with the internal signal, giving the
ability to control the duty cycle either via I2C or externally by
setting any of the 2 signals to 100% duty cycle.
STROBE MODE
A strobe mode can be programmed via I2C.
In this mode, each rising edge of the PWM signal turns on
the next channel, while turning off all other channels. The
duration that the channel is illuminated is set by the duty cycle
of the PWM input pin.
This mode can be also programmed by controlling the ON
and OFF state of each LED channel via I2C.
MANUAL MODE
The 34844 can also be used in Manual mode without using
the I2C interface. By setting the pin M/~S High, the LED
dimming will be controlled by the external PWM signal. The
over-voltage protection limit can be settled by a resistor
divider on A0/SEN pin.
Analog Integrated Circuit Device Data
Freescale Semiconductor 22
34844
FUNCTIONAL DEVICE OPERATION
I2C BUS SPECIFICATION
MC34844
During manual mode, all internal Registers are in Default
Configuration, refer Table 7, under this configuration the PIN
and NIN pins are enabled to scale the current capability per
string and may be disable by setting 2.2 V in the
corresponding pin.
Also in this mode, the device can be enabled as follows:
+ EN pin + PWM signal (Two Signals): In this
configuration, the PWM signal applied to PWM pin will be in
charge of controlling the LED dimming and a second signal
will enable or disable the chip through the EN pin. Figure 21
+ PWM Signal tied to SDA pin (Just ONE signal): In this
configuration the PWM pin should be tied to SDA pin. The
PWM signal applied to PWM pin will be in charge of
controlling LED dimming and enable the device every time
the PWM is active. For this configuration EN pin should be
LOW.
POWER DOWN MODE
If the input voltage falls below the UVLO threshold, the
device enters automatically into power down mode. When in
power down, the supply current is reduced below 2.0 μA
when there is no I2C activity, and it rises up when I2C
interface is enabled.
I2C BUS SPECIFICATION
The 34844 is a unidirectional device that can only be written by an external control unit. Since the device is a 7 bit address
device (1110110), the control unit needs to follow a specific data transfer format which is shown in Figure 8.
Figure 8. A Complete Data Transfer
For a complete data transfer, please use this format in the
following order:
1. START condition
2. The 34844 device address and Write instruction
(R/W = 0)
3. First data pack, it corresponds to the 34844 Register
that needs to be written. (refer to Table )
4. Second data pack, it corresponds to the value that
should be written to that register. (refer to Table )
5. STOP condition
I2C variables description:
• START: this condition occurs when SDA changes from
HIGH to LOW while SCK is HIGH.
• ACKNOWLEDGE: The acknowledge clock pulse is
generated by the Master (Control Unit).
• The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse.
The receiver (34844) must pull down the SDA line during
this acknowledge pulse to indicate that the data was
correctly written.
• Bits in the first byte: The first seven bits of the first bite
make up the slave address. The eighth bit is the LSB (least
significant bit), which determines the direction of the
message (Write = 0)
For the 34844 device, when an address is sent, each of the
devices in a system compares the first seven bits after the
START condition with its address. If they match, the
device considers itself addressed by the control unit as a
slave-receiver.
• STOP: this condition occurs when SDA changes from
LOW to HIGH while SCK is HIGH
For more information about “I2C BUS SPECIFICATION”
please refer to the following link:
http://www.nxp.com/acrobat_download/literature/
9398/39340011.pdf
Analog Integrated Circuit Device Data
23 Freescale Semiconductor
34844
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MC34844
LOGIC COMMANDS AND REGISTERS
Table 6. Write Registers
reg / db D7 D6 D5 D4 D3 D2 D1 D0
00 OVP3 OVP2 OVP1 OVP0 NINEN PINEN EN
01 CLRI2C SETI2C
04 FPWM5 FPWM4 FPWM3 FPWM2 FPWM1 FPWM0
05 FPWM11 FPWM10 FPWM9 FPWM8 FPWM7 FPWM6
06 FPWM17 FPWM16 FPWM15 FPWM14 FPWM13 FPWM12
07 DPWM7 DPWM6 DPWM5 DPWM4 DPWM3 DPWM2 DPWM1 DPWM0
08 CHEN4 CHEN3 CHEN2 CHEN1 CHEN0
09 STRB CLRFAIL ALL_OFF CHEN9 CHEN8 CHEN7 CHEN6 CHEN5
14 BST1 BST0
F0 ICH0_7 ICH0_6 ICH0_5 ICH0_4 ICH0_3 ICH0_2 ICH0_1 ICH0_0
F1 ICH1_7 ICH1_6 ICH1_5 ICH1_4 ICH1_3 ICH1_2 ICH1_1 ICH1_0
F2 ICH2_7 ICH2_6 ICH2_5 ICH2_4 ICH2_3 ICH2_2 ICH2_1 ICH2_0
F3 ICH3_7 ICH3_6 ICH3_5 ICH3_4 ICHG_3 ICH3_2 ICH3_1 ICH3_0
F4 ICH4_7 ICH4_6 ICH4_5 ICH4_4 ICH4_3 ICH4_2 ICH4_1 ICH4_0
F5 ICH5_7 ICH5_6 ICH5_5 ICH5_4 ICH5_3 ICH5_2 ICH5_1 ICH5_0
F6 ICH6_7 ICH6_6 ICH6_5 ICH6_4 ICH6_3 ICH6_2 ICH6_1 ICH6_0
F7 ICH7_7 ICH7_6 ICH7_5 ICH7_4 ICH7_3 ICH7_2 ICH7_1 ICH7_0
F8 ICH8_7 ICH8_6 ICH8_5 ICH8_4 ICH8_3 ICH8_2 ICH8_1 ICH8_0
F9 ICH9_7 ICH9_6 ICH9_5 ICH9_4 ICH9_3 ICH9_2 ICH9_1 ICH9_0
FA ICHG_7 ICHG_6 ICHG_5 ICHG_4 ICHG_3 ICHG_2 ICHG_1 ICHG_0
Table 7. Register Description
Register Name Default Value
(Hex) Description
EN 1Chip Enable by software. This signal is ‘OR’ed with external EN (0=off, 1 =on)
PINEN 1PIN pin enable (0=off, 1 =on)
NINEN 1NIN pin enable (0=off, 1 =on)
OVP[3:0] FOVP voltage
SETI2C 0SET I2C communication (Disable SM Bus Mode)
CLRI2C 0Clear set I2C
FPWM[17:0] 300 PWM Frequency
DPWM[7:0] FF PWM Duty Cycle (FFh =100%)
CHEN[9:0] 3FF Channel Enable (0=off, 1=on)
ALL_OFF 0All 10 channels OFF at the same. In order to reactivate channels this bit should be clear.
CLRFAIL 0Clear fail if channels are re-enable.
STRB 0Strobe MODE (0=Parallel, 1=Strobe)
Analog Integrated Circuit Device Data
Freescale Semiconductor 24
34844
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MC34844
BST[1:0] 2Boost Frequency (150,300,600,1200 kHz) [0h=150 Hz]
ICH#[7:0] FF Channel Current Program (FFh = Maximum Current)
ICHG[7:0] FF Global Current Program
Table 8. Over-voltage Protection
REGISTER (HEX) OVP VALUE (VOLTS)
211
315
419
523
627
731
835
939
A43
B47
C51
D55
E59
F62
Table 7. Register Description
Register Name Default Value
(Hex) Description
Analog Integrated Circuit Device Data
25 Freescale Semiconductor
34844
FUNCTIONAL DEVICE OPERATION
TYPICAL PERFORMANCE CURVES (TA=25°C)
MC34844
TYPICAL PERFORMANCE CURVES (TA=25°C)
Figure 9. Boost efficiency vs Input Voltage
Figure 10. Line Regulation, VIN Changing
85%
86%
87%
88%
89%
90%
91%
92%
93%
94%
95%
10 12 14 16 18 20 22 24 26 28 30
Vin, volts
Efficiency (%)
Fs = 600KHz
L=22uH, DCR=52mO
Schottky V12P10-E3/86A
COUT = 2x4.7µF, 2x2.2µF/100V
FPWM=600Hz, 100% duty
Load = 16 LEDs, 50mA/channel
V
LED = 48V, ±1V /channel
50.00
50.05
50.10
50.15
50.20
50.25
50.30
50.35
50.40
50.45
50.50
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Vin, volts
ILED (highest VLED channel), mA
Fs = 600KHz
L=22uH, DCR=52mO
Schottky V12P10-E3/86A
COUT = 2x4.7µF, 2x2.2µF/100V
FPWM=600Hz, 100% duty
Load = 16 LEDs, 50mA/channel
VLED = 48V, ±1V /channel
Analog Integrated Circuit Device Data
Freescale Semiconductor 26
34844
FUNCTIONAL DEVICE OPERATION
TYPICAL PERFORMANCE CURVES (TA=25°C)
MC34844
Figure 11. PWM Dimming Linearity
Figure 12. Bias Current vs Input Voltage (Operational Mode)
12.46 mA
0.14 mA
50.01 m
A
37.59 mA
25.03 m
A
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
0.4% 25.0% 50.0% 75.0% 99.6%
PWM Duty Cycle (%)
LED Current, mA
FPWM=25KHz
9.90
9.92
9.94
9.96
9.98
10.00
10.02
10.04
10.06
10.08
10.10
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Vin, volts
Bias Current, mA
I2C Mo de
SM_Bus Mode
Manual Mode
Analog Integrated Circuit Device Data
27 Freescale Semiconductor
34844
FUNCTIONAL DEVICE OPERATION
TYPICAL PERFORMANCE CURVES (TA=25°C)
MC34844
Figure 13. Bias Current vs Input Voltage (Sleep Mode)
Figure 14. Boost Soft Start
2.98
3.00
3.02
3.04
3.06
3.08
3.10
3.12
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Vin, volts
Bias Current, mA
I2C Mode
SM_Bus Mode
VOUT
COMP
INDUC TOR
CURRENT
Vin=24V
Load=16 L ED s, 5 0mA/channe l
VLED = 47V, ±1V
VOUT
COMP
INDUC TOR
CURRENT
Vin=24V
Load=16 L ED s, 5 0mA/channe l
VLED = 47V, ±1V
Analog Integrated Circuit Device Data
Freescale Semiconductor 28
34844
FUNCTIONAL DEVICE OPERATION
TYPICAL PERFORMANCE CURVES (TA=25°C)
MC34844
Figure 15. Typical Operation Waveforms for FPWM=600 Hz, 40% Duty
Figure 16. Typical Operation Waveforms for FPWM=600 Hz, 100% Duty
ILED, CH1
INDUCTOR
CURRENT
VCH1
VOUT
(ac coupled)
ISET=40mA (all channels)
FPWM=600Hz, 40% duty
Precharge
ILED, CH1
INDUCTOR
CURRENT
SWA
SWB
ISET=50mA (all channels)
FPWM=600Hz, 100% duty
(ac coupled)
VOUT
ILED, CH1
INDUCTOR
CURRENT
SWA
SWB
ISET=50mA (all channels)
FPWM=600Hz, 100% duty
(ac coupled)
VOUT
Analog Integrated Circuit Device Data
29 Freescale Semiconductor
34844
FUNCTIONAL DEVICE OPERATION
TYPICAL PERFORMANCE CURVES (TA=25°C)
MC34844
Figure 17. Low Duty Dimming Operation Waveforms (FPWM=20 kHz, 2LSB)
Figure 18. Low Duty Dimming Operation Waveforms (FPWM=20 kHz, 1LSB)
ISET = 20mA,
FPWM=20KHz, Duty=0.78% (2LSB)
VCh1
ILED1
ISET = 20mA,
FPWM=20KHz, Duty=0.78% (2LSB)
VCh1
ILED1
ISET = 20mA,
FPWM=20KHz, Duty=0.78% (2LSB)
VCh1
ILED1
ISET = 20mA,
FPWM=20KHz, Duty=0.39% (1LSB)
VCh1
ILED1
ISET = 20mA,
FPWM=20KHz, Duty=0.39% (1LSB)
VCh1
ILED1
ISET = 20mA,
FPWM=20KHz, Duty=0.39% (1LSB)
VCh1
ILED1
Analog Integrated Circuit Device Data
Freescale Semiconductor 30
34844
TYPICAL APPLICATIONS
MC34844
TYPICAL APPLICATIONS
Figure 19. Manual Mode (Single Wire Control)
Figure 20. Manual Mode (Two Wire Control)
VIN = 24V
0
0
0
VOUT
0
0
0
0
VDC1
VDC1
VCC
0
VOUT
Master CK
LED MATRIX (16S10P)
MANUAL MODE (Single Wire Control)
Output
OVP = 55V
5.6K5.6K
+
47uF
+
47uF
2.2uF2.2uF
3.3K3.3K
20K20K
309K309K
5.1K5.1K
+
13.8uF
+
13.8uF
150K150K
1.8nF1.8nF
U1
34844
U1
34844
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
56pF56pF
CLKCLK
D1D1
2 1
2.2uF2.2uF
22uH22uH
1 2
2.2uF2.2uF
1.0K
VIN = 24V
0
0
0
0
VCC
VOUT
VOUT
0
VDC1
VDC1
0
0
0
Master CK
Output
LED MATRIX (16S10P)
OVP = 55V
MANUAL MODE (Two Wire Control)
Unit
Control
EN
PWM
2.2uF2.2uF
D5D5
2 1
22uH22uH
1 2
1.8nF1.8nF
2.2uF2.2uF
3.3K3.3K
150K150K
+
13.8uF
+
13.8uF
U2
34844
U2
34844
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
2.2uF2.2uF
20K20K
5.1K5.1K
5.6K5.6K
56pF56pF
+
47uF
+
47uF
309K309K
1.0K
Analog Integrated Circuit Device Data
31 Freescale Semiconductor
34844
TYPICAL APPLICATIONS
MC34844
Figure 21. SM Bus Mode
Figure 22. Master - Slave Connection
VIN = 24V
0
0
0
0
VCC
VOUT
0
VDC1
VDC1
0
0
VDC1
0
Master CK
LED MATRIX (16S10P)
Unit
Control
SCK
SDA
+
47uF
+
47uF
309K309K
2.2uF2.2uF
D8D8
2 1
22uH22uH
1 2
1.8nF1.8nF
2.2uF2.2uF
3.3K3.3K
+
13.8uF
+
13.8uF
U3
34844
U3
34844
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
2.2uF2.2uF
5.1K5.1K
5.6K5.6K
56pF56pF
1.0K
VIN = 24V
0
0
0
0
VCC
VOUT
0
VDC1
VDC1
0
0
VDC1
VIN = 24V
0
0
0
0
VCC
VOUT
0
VDC1
0
0
VDC1
Master CK
Master CK
LED MATRIX (16S10P)
Unit
Control
SCK
SDA
A0/SEN (Master)
MASTER - SLAVE Connection
MASTER Device
SLAVE Device
Input
LED MATRIX (16S10P)
A0/SEN (Slave)
56pF56pF
2.2uF2.2uF
U5
34844
U5
34844
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
3.3K3.3K
5.1K5.1K
309K309K
U4
34844
U4
34844
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
2.2uF2.2uF
+
47uF
+
47uF
22uH22uH
1 2
5.6K5.6K
22uH22uH
1 2
2.2uF2.2uF
D1D1
2 1
56pF56pF
+
13.8uF
+
13.8uF
3.3K3.3K
309K309K
5.1K5.1K
+
47uF
+
47uF
2.2uF2.2uF
1.8nF1.8nF
2.2uF2.2uF
D2D2
2 1
+
13.8uF
+
13.8uF
1.8nF1.8nF
2.2uF2.2uF
5.6K5.6K
1.0K
1.0K
Analog Integrated Circuit Device Data
Freescale Semiconductor 32
34844A
MC34844A SPECIFICATIONS PAGES 32 TO 54
MC34844A
MC34844A SPECIFICATIONS
PAGES 32 TO 54
Analog Integrated Circuit Device Data
Freescale Semiconductor 33
34844A
INTERNAL BLOCK DIAGRAM
MC34844A
INTERNAL BLOCK DIAGRAM
Figure 23. 34844A Simplified Internal Block Diagram
VIN
VDC1
COMP
EN
CK
PWM
SCK
SDA
ISET
PIN
NIN
SWA
SWB
PGNDA
FAIL
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
TEMP/OPTO
LOOP CONTROL
CURRENT DAC
OCP/OTP/UVLO
PWM GENERATOR
10 CHANNEL
OVP
BOOST
CLOCK/PLL
CONTROLLER
80 mA CURRENT
MIRROR
V SENSE
GND
A0/SEN
PGNDB
LDO
VDC3
VDC2
SLOPE
I2C INTERFACE
VOUT
M/~S
Analog Integrated Circuit Device Data
34 Freescale Semiconductor
34844A
PIN CONNECTIONS
MC34844A
PIN CONNECTIONS
Figure 24. 34844A Pin Connections
Table 9. 34844A Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 42.
Pin Number Pin Name Pin Function Formal Name Definition
1VIN Power Input voltage Input supply
2 PGNDB Power Power Ground Power ground
3SWB Input Switch node B Boost switch connection B
4SWA Input Switch node A Boost switch connection A
5 PGNDA Power Power Ground Power ground
6A0/SEN Input Device Select Address select, device select pin or OVP HW control
7EN Input Enable Enable pin (active high, internal pull-up)
8 - 17 I0-I9 Input LED Channel LED string connections
18 FAIL Open Drain Fault detection Fault detected pin (open drain):
No Failure = Low-impedance
Failure = High-impedance
19 ISET Passive Current set LED current setting resistor
20 PIN Input Positive current scale Positive input analog current control
21 NIN Input Negative current scale Negative input analog current control
22 SLOPE Passive Boost Slope Boost slope compensation Setting resistor
23 VDC3 Output Internal Regulator 3 Decoupling capacitor for internal phase locked loop power
24 CK Input/Output Clock signal Clock synchronization pin (input for M/~S = low - internal pull-up, output
for M/~S = high)
25 PWM Input External PWM External PWM input (internal pull-down)
VIN
PGNDB
SWB
SWA
PGNDA
A0/SEN
EN
IO
CK
VDC3
SLOPE
NIN
PIN
ISET
FAIL
I9
VOUT
VDC2
M/~S
COMP
VDC1
SCK
SDA
PWM
I1 I2 I3 I4 I5 I6 I7 I8
2532 31 30 29 28 27 26
24
17
18
19
20
21
22
23
1
8
7
6
5
4
3
2
169 101112131415
QFN - EP
5MM X 5MM
32 LEAD
EP GND
EP = Exposed Pad
TRANSPARENT
TOP VIEW
Analog Integrated Circuit Device Data
Freescale Semiconductor 35
34844A
PIN CONNECTIONS
MC34844A
26 SDA Bidirectional I2C data I2C data Line
27 SCK Bidirectional I2C clock I2C clock line
28 VDC1 Output Internal Regulator 1 Decoupling capacitor for internal logic rail
29 COMP Passive Compensation pin Boost converter Type compensation pin
30 M/~S Input Master/Slave selector Selects Master mode (1) or Slave mode (0)
31 VDC2 Output Internal Regulator 2 Decoupling capacitor for internal regulator
32 VOUT Input Voltage Output Boost Output voltage sense pin
EP GND -Ground Ground Reference for all internal circuits other than Boost FET
Table 9. 34844A Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 42.
Pin Number Pin Name Pin Function Formal Name Definition
Analog Integrated Circuit Device Data
36 Freescale Semiconductor
34844A
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
MC34844A
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 10. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
ELECTRICAL RATINGS
Maximum Pin Voltages
A0/SEN
I0, I1, I2, I3, I4, I5, I6, I7, I8, I9(17)
EN, VIN
SWA, SWB, VOUT
FAIL, PIN, NIN, ISET, M/~S, CK, PWM
VMAX
7.0
45
30
65
6.0
V
Maximum LED Current IMAX 85 mA
ESD Voltage(14)
Human Body Model (HBM)
Machine Model (MM)
VESD
+2000
+200
V
THERMAL RATINGS
Ambient Temperature Range TA-40 to 105 °C
Junction to Ambient Temperature(15) TθJA 32 °C/W
Junction to Case Temperature(15) TθJC 3.5 °C/W
Maximum junction temperature TJ150 °C
Storage temperature range TSTO -40 to 150 °C
Peak Package Reflow Temperature During Reflow(16) TPPRT 260 °C
Power Dissipation
TA = 25°C
TA = 70°C
TA = 85°C
TA = 105°C
3.9
2.5
2.0
1.4
W
Notes
14. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2), and the Machine Model (MM) (AEC-Q100-
003), RZAP = 0 Ω
15. Per JEDEC51 Standard for Multilayer PCB
16. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
17. 45 V is the Maximum allowable voltage on all LED channels in off-state.
Analog Integrated Circuit Device Data
Freescale Semiconductor 37
34844A
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844A
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
Table 11. Static and Dynamic Electrical Characteristics
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1,
-40°C ≤ TA ≤ 105°C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SUPPLY
Supply Voltage(20) VIN 7.0 12 28 V
Supply Current when Shutdown Mode
Manual: PWM = Low, EN = Low, SCK & SDA=Low
SM Bus: EN bit = 0, SCK & SDA=Low, EN pin= Low
I2C: SETI2Cbit=1, CLRI2C=0, EN bit= 0, EN pin = Low
ISHUTDOWN
-
-
2.0
17
-
-
μA
Supply Current when Sleep Mode
SM-Bus: EN = low, SCK & SDA= Active, SETI2C bit = 0, EN bit = 0
I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 0
ISLEEP
-4.0 -mA
Supply Current when Operational Mode
Manual: EN= High, SCK & SDA=Low, PWM=Low
SM-Bus: EN= Low, SCK & SDA=Active, EN bit= 1, PWM=Low
I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 1, PWM=Low
IOPERATIONAL
-13.0 -mA
Under-voltage Lockout (VIN Rising) UVLO 5.4 6.0 6.4 V
Under-voltage Hysteresis (VIN Falling) UVLOHYST -300 -mV
VDC1 Voltage(18)
CVDC1 = 2.2 μF
VDC1 2.3 2.5 2.75 V
VDC2 Voltage(18)
CVDC2 = 2.2 μF
VDC2 5.5 6.0 6.5 V
VDC3 Voltage(18)
CVDC3 = 2.2 μF
VDC3 2.3 2.5 2.75 V
BOOST
Output Voltage Range(19)(20)
VIN = 7.0 V
VIN = 28 V
VOUT1
VOUT2
8.0
32
-
-
28
60
V
Boost Switch Current Limit IFET 2.3 2.5 2.7 A
Boost Switch Current Limit Timeout tBOOST_TIME -10 -ms
RDSON of Internal FET (IDRAIN= 1.0 A) RDSON -250 500 mΩ
Boost Switch Off-state Leakage Current
VSWA,SWB = 65 V
IBOOST_LEAK - - 10 μA
Feedback pin Off-state Leakage Current (VOUT = 65 V ) VOUTLEAK -500 700 μA
Peak Boost Efficiency(20) EFFBOOST -90 - %
Notes
18. This output is for internal use only and not to be used for other purposes. A 1.0 kΩ resistor between the VDC3 and VDC1 pin is
recommended for <-20 °C operation.
19. Minimum and Maximum output voltages are dependent on Min/Max duty cycle and current limit condition.
20. Guaranteed by design
Analog Integrated Circuit Device Data
38 Freescale Semiconductor
34844A
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844A
Line Regulation (21) - VIN=7.0 to 28 V IOUT/VIN -0.2 -0.2 %/V
Load Regulation (21) - VLED = 8.0 to 65 V (all Channels) IOUT/VLED -0.2 -0.2 %/V
Slope compensation voltage ramp - RSLOPE = 68 kΩVSLOPE -0.49 -V/μs
Current Sense Amplifier Gain ACSA -9.0 -
Current Sense Resistor RSENSE -22 - mΩ
OTA Transconductance GM-200 -μS
Transconductance Sink and Source Current Capability ISS -100 -μA
FAIL PIN
Off-state Leakage Current - VFAIL = 5.5 V IFAIL_LEAK - - 50 μA
On-state Voltage Drop - ISINK = 4.0 mA VOL - - 0.4 V
LED CHANNELS
Sink Current
ICHx Register = 255, PIN&NIN = Disabled, TA=25 °C
RISET=3.48 kΩ, 0.1%
ISINK
78.4 80 81.6
mA
Regulated minimum voltage across drivers
Pulse Width > 400 ns
VMIN
625 700 775
mV
Current Matching Accuracy IMATCH -2.0 -2.0 %
ISET Pin Voltage
RISET=3.48 kΩ, 0.1%
VSET
2.007 2.048 2.069
V
LED Current Amplitude Resolution
1.0 mA < ILED < 80 mA
ILEDRES
-1.5 -
%
Off-state Leakage Current, All channels - (VCH = 45 V) ICH_LEAK - - 10 μA
PIN INPUT
Voltage to Disable PIN mode VPIN_DIS 2.2 - - V
PIN Bias Current
PIN = VSET
IPIN -2.0 -2.0 μA
Analog Dimming Current
ICHx Register = 255, RISET=3.48 kΩ 0.1%
PIN = VSET/2
PIN = VSET
IDIM_PIN
36
76
40
80
44
84
mA
Notes
21. Guaranteed by design
Table 11. Static and Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1,
-40°C ≤ TA ≤ 105°C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 39
34844A
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844A
NIN INPUT
Voltage to Disable NIN mode VNIN_DIS 2.2 - - V
NIN Bias Current
NIN = VSET
ININ -2.0 -2.0 μA
Analog Dimming Current
ICHx Register = 255, RISET=3.48 kΩ 0.1%
NIN = VSET/2
NIN = 0 V
IDIM_NIN
36
76
40
80
44
84
mA
OVER-TEMPERATURE PROTECTION
Over-temperature Threshold(22)
Rising
Hysteresis
OTT
150
-
165
25
175
-
°C
I2C/SM BUS PHYSICAL LAYER [SCK, SDA]
I2C Address ADRI2C -1110110 -Binary
SM-Bus Address ADRSMB -1110110 -Binary
Input Low Voltage VILI -0.3 -0.8 V
Input High Voltage VIHI 2.1 -5.5 V
Input Hysteresis VHYSI -0.3 - V
Output Low Voltage
Sink Current < 4.0 mA
VOLI - - 0.4 V
Input Current IINI -5.0 -5.0 μA
Input Capacitance(22) CINI - - 10 ρF
LOGIC INPUTS / OUTPUTS (CK, M/~S, PWM, A0/SEN, EN)
Input Low Voltage VILL -0.3 -0.5 V
Input High Voltage VIHL 1.5 -5.5 V
Input Hysteresis VHYSL -0.1 - V
Input Low Voltage (EN) VILL -0.3 -0.5 V
Input High Voltage (EN) VIHL 2.1 -28 V
Output Low Voltage (CK)
ISINK < 2.0 mA
VOLL - - 0.45 V
Output High Voltage (CK)
ISOURCE < 2.0 mA
VOHL 2.2 -5.5 V
Input Current IIIL -5.0 -5.0 μA
Input Capacitance(22) CINI - - 5.0 ρF
Notes
22. Guaranteed by design
Table 11. Static and Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1,
-40°C ≤ TA ≤ 105°C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
40 Freescale Semiconductor
34844A
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844A
OVER-VOLTAGE PROTECTION
Over-voltage Clamp - OVP Register Table:
OVP = Fh (Default) OVPFH 60.5 62.5 64.5 V
OVP = Eh OVPEH 56.5 58 60 V
OVP = Dh OVPDH 53 54 56 V
OVP = Ch OVPCH 49 51 52.5 V
OVP = Bh OVPBH 45 47 48.5 V
OVP = Ah OVPAH 41 43 44.5 V
OVP = 9h OVP9H 38 39 40.5 V
OVP = 8h OVP8H 34 36 37.5 V
OVP = 7h OVP7H 30.5 32 33.5 V
OVP = 6h OVP6H 26 28 30 V
OVP = 5h OVP5H 23 24 25 V
Over-voltage threshold,
Set by Hardware, Voltage at A0/SEN
OVPHW 6.15 6.5 6.85 V
A0/SEN Sink Current, TA=25°C ISINK_OVP 70 100 130 μA
BOOST
Switching Frequency (BST [1:0]=0) fSW0 0.14 0.16 0.18 MHz
Switching Frequency (BST [1:0]=1) (Default) fSW1 0.29 0.32 0.35 MHz
Switching Frequency (BST [1:0]=2) fSW2 0.59 0.65 0.72 MHz
Switching Frequency (BST [1:0]=3) fSW3 1.17 1.30 1.42 MHz
Boost Switching Frequency fSW 0.29 0.32 0.35 MHz
Minimum Duty Cycle DMIN -10 15 %
Maximum Duty Cycle DMAX 80 85 - %
Soft Start Period tSS -6.5 -ms
Boost Switch Rise Time(23) tTR -15 -ns
Boost Switch Fall Time(23) tF-25 -ns
Notes
23. Guaranteed by design
Table 11. Static and Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1,
-40°C ≤ TA ≤ 105°C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 41
34844A
ELECTRICAL CHARACTERISTICS
STATIC AND DYNAMIC ELECTRICAL CHARACTERISTICS
MC34844A
PWM GENERATOR
PWM Frequency Range (25)
M/~S = Low (Slave Mode)
fPWMS110 -27000 Hz
PWM Frequency
M/~S = High (Master Mode)
FPWM Register = 768
FPWM Register = 192,000
fPWMM
25000
103
27000
110
29000
112
Hz
PWM dimming resolution tfPWM -0.39 - %
PWM PIN (DIRECT PWM CONTROL)
Input PWM Pin Minimum Pulse(25) tPWM_IN 150 - - ns
Input PWM Frequency Range fPWM 110 -27000 Hz
PHASE LOCK LOOP
CK Slave Mode Frequency Lock Range(24)
M/~S = Low (Slave Mode)
fCKS110 -27000 Hz
CK Slave Mode Input Jitter(25)
M/~S = Low (Slave Mode)
fCKS_JITTER - - 0.1 %
Slave Mode Acquisition Time
M/~S = Low (Slave Mode)
FPWMS=27 kHz
FPWMS=110 Hz
TS_ACQ
-
-
50
2000
-
-
ms
ms
CK Frequency (Master Mode)
FPWM Register = 768
FPWM Register = 192,000
fCKMASTER
25000
103
27000
110
29000
112
Hz
I2C/SM BUS PHYSICAL LAYER [SCK, SDA]
Interface Frequency Range fSCK 400 kHz
SM Bus Power-on-Reset Time tRST -100 -ms
SM Bus Shut down mode Timeout tSHUTDOWN -30 -ms
Output fall time(25)
10 ρF < CL < 400 ρF
tF40 -160 ns
Output rise time(25)
10 ρF<CL<400 ρF
tR20 -80 ns
LOGIC OUTPUT (CK)
Output Rise and Fall time
CL<100 ρF
tR/tF-25 -ns
LED CHANNELS
Channels Rise and Fall Time(25) tR/tF-23 50 ns
Notes
24. Special considerations should be made for frequencies between 110 Hz to 1.0 KHz. Please refer to Functional Device Operation for
further details.
25. Guaranteed by design
Table 11. Static and Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 12 V, VOUT = 42 V, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1,
-40°C ≤ TA ≤ 105°C, PGND = 0 V, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
42 Freescale Semiconductor
34844A
FUNCTIONAL DESCRIPTION
INTRODUCTION
MC34844A
FUNCTIONAL DESCRIPTION
INTRODUCTION
LED backlighting has become very popular for small and
medium LCDs, due to some advantages over other
backlighting schemes, such as the widely used cold cathode
fluorescent lamp (CCFL). The advantages of LED
backlighting are low cost, long life, immunity to vibration, low
operational voltage, and precise control over its intensity.
However, there is an important drawback of this method. It
requires more power than most of the other methods, and this
is a major problem if the LCD size is large enough.
To address the power consumption problem, solid state
optoelectronics technologies are evolving to create brighter
LEDs with lower power consumption. These new
technologies together with highly efficient power
management LED drivers are turning LEDs, a more suitable
solution for backlighting almost any size of LCD panel, with
really conservative power consumption.
One of the most common schemes for backlighting with
LED is the one known as “Array backlighting”. This creates a
matrix of LEDs all over the LCD surface, using defraction and
diffused layers to produce an homogenous and even light at
the LCD surface. Each row or column is formed by a number
of LEDs in series, forcing a single current to flow through all
LEDs in each string.
Using a current control driver, per row or column, helps the
system to maintain a constant current flowing through each
line, keeping a steady amount of light even with the presence
of line or load variations. They can also be use as a light
intensity control by increasing or decreasing the amount of
current flowing through each LED string.
To achieve enough voltage to drive a number of LEDs in
series, a boost converter is implemented, to produce a higher
voltage from a smaller one, which is typically used by the
logical blocks to do their function.
The 34844A implements a single channel boost converter
together with 10 input channels, for driving up to 16 LEDs per
string to create a matrix of more than 160 LEDs. Together
with its 90% efficiency and I2C programmable or external
current control, among other features, makes the 34844A a
perfect solution for backlighting small and medium size LCD
panels, on low power portable and high definition devices.
FUNCTIONAL PIN DESCRIPTION
INPUT VOLTAGE SUPPLY (VIN)
IC Power input supply voltage, is used internally to
produce internal voltage regulation (VDC1, VDC3) for logic
functioning, and also as an input voltage for the boost
regulator.
INTERNAL VOLTAGE REGULATOR 1 (VDC1)
This pin is for internal use only, and not to be used for other
purposes. A capacitor of 2.2 μF should be connected
between this pin and ground for decoupling purposes.
INTERNAL VOLTAGE REGULATOR 2 (VDC2)
This pin is for internal use only, and not to be used for other
purposes. A capacitor of 2.2 μF should be connected
between this pin and ground for decoupling purposes.
INTERNAL VOLTAGE REGULATOR 3 (VDC3)
This pin is for internal use only, and not to be used for other
purposes. A capacitor of 2.2 μF should be connected
between this pin and ground for decoupling purposes. A
1.0 kΩ resistor between the VDC3 and VDC1 pin is
recommended for <-20 °C operation.
BOOST COMPENSATION PIN (COMP)
Passive terminal used to compensate the boost converter.
Add a capacitor and a resistor in series to GND to stabilize
the system.
IC ENABLE (EN)
The active high enable terminal is internally pulled high
through pull-up resistors. Applying 0V to this terminal would
stop the IC from working.
INPUT/OUTPUT CLOCK SIGNAL (CK)
This terminal can be used as an output clock signal
(master mode), or input clock signal (slave mode), to
synchronize more than one device.
MASTER/SLAVE MODE SELECTION (M/~S)
Setting this pin High puts the device into Master mode,
producing an output synchronization clock at the CK terminal.
Setting this pin low, puts the device in Slave mode, using the
CK pin as an input clock.
EXTERNAL PWM INPUT (PWM)
This terminal is internally pulled down. An external PWM
signal can be applied to modulate the LED channel directly in
absence of an I2C interface.
CLOCK I2C SIGNAL (SCK)
Clock line for I2C communication.
ADDRESS I2C SIGNAL (SDA)
Address line for I2C communication.
Analog Integrated Circuit Device Data
Freescale Semiconductor 43
34844A
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
MC34844A
A0/SEN
Address select, device select pin, or Hardware Over-
voltage Protection (OVP) Control.
CURRENT SET (ISET)
Each LED string can drive up to 50 mA. The maximum
current can be set by using a resistor from this pin to GND.
POSITIVE CURRENT SCALING (PIN)
Positive current scaling factor for the external analog
current control. Applying 0 V to this pin, scales the current to
near 0%, and in the same way, applying VSET (2.048 V Typ.),
the scale factor is 100%. By applying a voltage higher than
2.2 V, the scaling factor is disabled, and the internal pull-ups
are activated.
If PIN pin and NIN pin are used at the same time then by
applying 0 V to the PIN pin and VSET to NIN pin, scales the
current to near 0%, and in the same way, applying VSET to
the PIN pin and 0 V to NIN pin, scales the current to 100%.
By applying a voltage higher than 2.2 V, the scaling factor is
disabled and the internal pull-ups are activated in both pins.
NEGATIVE CURRENT SCALING (NIN)
Negative current scaling factor for the external analog
current control. Setting 0 V to this pin scales the current to
100%, in the same way, setting VSET (2.048 V Typ.) the scale
factor is near 0%. By applying a voltage higher than 2.2 V, the
scaling factor is disabled and the internal pull-ups are
activated.
If PIN pin and NIN pin are used at the same time then by
applying 0 V to the PIN pin and VSET to NIN pin, scales the
current to near 0%, and in the same way, applying VSET to the
PIN pin and 0 V to NIN pin, scales the current to 100%. By
applying a voltage higher than 2.2 V, the scaling factor is
disabled and the internal pull-ups are activated in both pins.
GROUND (GND)
Ground Reference for all internal circuits other than the
Boost FET.
The Exposed Pad (EP) should be used for thermal heat
dissipation.
I0-I9
Current LED driver, each line has the capability of driving
up to 50 mA.
FAULT DETECTION PIN (FAIL)
When a fault situation is detected, this pin goes into high
impedance.
BOOST SLOPE COMPENSATION SETTING
RESISTOR (SLOPE)
The resistor to be used for the SLOPE depends on the
Input and Output voltage difference as well as the inductor
value. Please use the formula shown in the Components
Calculation section to calculate the value accordingly.
POWER GROUND TERMINALS (PGNDA, PGNDB)
Ground terminal for the internal Boost FET.
OUTPUT VOLTAGE SENSE TERMINAL (VOUT)
Input terminal to monitor the output voltage. It also
supplies the input voltage for the internal regulator 2 (VDC2).
SWITCHING NODE TERMINALS (SWA, SWB)
Switching node of boost converter.
Analog Integrated Circuit Device Data
44 Freescale Semiconductor
34844A
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844A
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 25. Functional Internal Block Diagram
REGULATORS
The 34844A is designed to operate from input voltages in
the 7.0 to 28 V range. This is stepped down internally by
LDOs to 2.5 V (VDC1 and VDC3) and 6 V (VDC3) for
powering internal circuitry. If the input voltage falls below the
UVLO threshold, the device automatically enters in shut
down mode.
Power UP Sequence:
The power up sequence for applying VIN, with respect to
the ENABLE and PWM signals, is very important to assure a
good performance of the part.
It is recommended to follow this sequence:
1. Apply VIN first
2. Wait for a couple of milliseconds (~2.0 ms) to let the
logic and internal regulators get settled
3. Take the EN pin high, or keep it low depending on the
operating mode
4. Apply the PWM signal
Operating Modes:
The device can be operated by the EN pin and/or SDA/
SCK bus lines, resulting in three distinct operation modes:
• Manual mode, there is no I2C capability, the bus line pins
must be tied low, and the EN pin controls the ON/OFF
operation. To shutdown the part in Manual mode, first the
PWM pin should be taken low followed by the EN pin. The
part will not shut down unless VOUT collapses to a voltage
below 30 V.
• SM Bus mode, EN pin must be tied low and the device is
turned ON by any activity on the bus lines. The part shuts
down if the bus lines are held low for more than 30 ms, the
30 ms watchdog timer can be disabled by I2C (setting
SETI2C bit high) or tying the EN pin high. In Sleep mode
(EN bit=0) the device reduces the power consumption by
leaving “alive” only the blocks required for I2C
communication.To shutdown the part in SM Bus mode, the
EN bit should first be a '0', then the SCK and SDA should
be taken low.
•I
2C mode, has to be configured by I2C communication
(SETI2C bit = 1) right after the IC is turned ON, it prevents
the part from being turned ON/OFF by the bus. Sleep
mode is also present and it is intended to save power, but
still keep the IC prepared to communicate by I2C. By
taking the EN bit low and then the EN pin low, the part
enters into a shutdown mode.
MC34844 - Functional Block Diagram
Regulator / Power down Protection / Failure Detection
LED Channels
LED Channels
Logic Control
Regulators / Power Down
3 Internal Regulators
Protection / Failure Detection
Logic Control
Serial Interface Control
Boost
Boost
Optical and Temperature Control
PWM Dimming
Over-temperature Protection
LED Open Protection
Over-current Protection
Under-voltage Protection
Over-voltage Protection
Analog Integrated Circuit Device Data
Freescale Semiconductor 45
34844A
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844A
BOOST
The integrated boost converter operates in non-
synchronous mode and integrates a 2.5 A FET. An integrated
sense circuit is used to sense the voltage at the LED current
mirror inputs and automatically sets the boost output voltage
(DHC) to the minimum voltage needed to keep all LEDs
biased with the required current. The DHC is designed to
operate for pulse widths > 400 ns in the LED drivers.
If the pulse widths are shorter than specified, the DHC
circuit will not operate and the voltage across the LED drivers
will increase to a value given by the OVP minus the total LED
voltage in the LED string. Therefore it is imperative to select
the proper OVP level to minimize power dissipation.
The user can program the boost frequency by I2C
(BST[1:0]) only after the IC is powered up and before the
boost circuit is turned ON for the first time (PWM pin low to
high). This sequence avoids boost frequency to be changed
inadvertently during operation. The first I2C command has to
wait for 5.0 ms after the part is turned ON, in order to allow
sufficient time for the device power up sequence to be
completed.
Please follow this sequence in order to change the Boost
frequency thru I2C:
1. Take PWM pin low
2. Disable the part by software (EN bit = low)
3. Write the new Boost frequency data (BST[1:0])
4. Enable the part by software (EN bit = high)
5. Reconfigure all registers
6. Take PWM pin High
The boost controller has an integral track and hold
amplifier with indefinite hold time capability, to enable
immediate LED on cycles after extended off times. During
extended off times, the external LEDs cool down from their
normal quiescent operating temperature and thereby
experience a forward voltage change, typically an increase in
the forward voltage. This change can be significant for
applications with a large number of series LEDs in a string
operating at high current. If the boost controller did not track
this increased change, the potential on the LED drivers would
saturate for a few cycles once the LED channels are re-
enabled.
HARDWARE AND SOFTWARE OVP:
The OVP value should be set to a higher value than the
maximum LED voltage over the whole temperature range. A
good practice is to set it 5.0 V or so above the max LED
voltage.
The OVP can be set from 11 to 62 V, ~4.0 V spaced, using
the I2C interface (OVP Register). If the I2C capability is not
present, the OVP can be controlled either by a resistor divider
connected from VOUT to GND, with its mid point tied to the
A0/SEN pin, or by a zener diode from VOUT to the A0/SEN
pin (threshold = 6.5 V). During an OVP condition, the output
voltage will go to the OVP level, which is programmed via the
I2C interface or settled by a resistor divider on A0/SEN pin, or
by a zener diode. The formulas to calculate the hardware
OVP using any of the two methods are as follows:
Table 12. Operation Current Consumption Modes
MODE EN Pin SCK/SDA Pins I2C Bit Command Current Consumption
Mode Comments
Manual Low Low N/A Shutdown PWM pin = Low
High Low N/A Operational
SM Bus
Low Low (> 27 ms) EN bit = 0 Shutdown
Low Active EN bit = 0 Sleep
Low Active EN bit = 1 Operational
I2C
Low X
SETI2C bit = 1
I2C Low Power
(Shutdown)
Part Doesn’t
Wake-up
CLRI2C bit = 0
EN bit = 0
High X
SETI2C bit = 1
SleepCLRI2C bit = 0
EN bit = 0
High X
SETI2C bit = 1
OperationalCLRI2C bit = 0
EN bit = 1
VOUT
Method 1 Method 2
A0/SEN
A0/SEN
OVP = VZENER2 + 6.5 V
OVP = 6.5 V [(RUPPER / RLOWER) + 1] + (100E-6 x RUPPER)
RUPPER
RLOWER
VZENER2
VOUT
Analog Integrated Circuit Device Data
46 Freescale Semiconductor
34844A
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844A
OVER-CURRENT PROTECTION (OCP)
The boost converter also features internal Over-current
Protection (OCP) and has a user programmable Over-
voltage Protection (OVP).
The OCP operates on a cycle by cycle basis. However, if
the OCP condition remains for more than 10ms then the
device turns off the LED Drivers, the Boost goes to Sleep
mode and the output FAULT pin goes into high-impedance.
The device can only be restarted by recycling the enable or
creating a Power On Reset (POR).
CURRENT MIRROR
The programmable current mirror matches the current in
10 LED strings to within 2%. The maximum current is set
using a resistor to GND from the ISET pin. This can be scaled
down using the I2C interface to 255 levels.
Zero current is achieved by turning off the LED Driver by
I2C (registers CHENx = 0h) for a duty cycle from 0% to 99%,
or by pulling PWM pin low regardless of the duty cycle.
I2C capability allows the channels to be controlled
individually or in parallel.
Current on LED Channel (PIN and NIN mode disabled) Eqn. 6
Default ICH[RegisterValue]=255
In the off state, the LEDs current is set to 0 and the boost
converter stops switching.
This feature allows to drive more than 80 mA of current by
connecting the LED string to 2 or more LED channels in
parallel. For example; if the application requires to drive a
channels at 160 mA, then the bottom of each LED string
should be connected to two channels in order to duplicate the
current capability (Example: CH0+CH1 = 160 mA).
PWM GENERATOR
The PWM generator can operate in either master or slave
modes, as set by the M/~S pin.
In master mode, the internal PWM generator frequency is
programmed through the I2C interface (registers FPWM).
The default programmed value set the number of 27 kHz
clocks (40 μs) in one PWM cycle. The 18-bit resolution allows
minimum PWM frequencies of 110 Hz to be programmed.
The resulting frequency is output on the CK pin.
PWM Frequency Eqn. 7
In slave mode, the CK pin acts as an input. The internal
digital PLL uses this frequency as the PWM frequency. By
setting one device as master, and connecting the CK output
to the input on a number of slave configured devices, all
PWM frequencies are synchronized together.
The duty cycle of the PWM waveform in both master and
slave modes is set using a second register on the I2C
interface (register DPWM), and can be controlled from 100%
duty cycle to 1/256 Tpwm = 0.39%. Zero percent of duty cycle
is achieved by turning LED drivers off (register CHENx = 0h)
or pulling PWM pin low.
An external PWM can also be used. The PWM input is
'AND'ed with the internal signal. By setting the serial interface
to 100% duty cycle (default), the external pin has full control
of the PWM duty cycle. This pin can also be used to modulate
the LED at a lower frequency than the PWM dimming
frequency (DHC Minimum pulse width = 400 ns).
POWER OFF AND POWER ON LED CHANNELS
The 34844A allows the user to Power OFF and Power ON
any channel independently thru I2C/SM-BUS mode.
The POWER ON function reconnects the LED driver and
the feedback circuit to the channel to allow functionality to
that channel again.
On an opposite way when the channel is POWER OFF,
the LED driver and feedback circuit are disconnected to the
channels.
This function is very useful for applications where one or
more channel has to be shutdown to avoid the output
voltages goes to OVP during the start up of the part.
The sequence to make these functions work is the
following:
To POWER ON LED channels:
1. Take PWM pin low
2. Set POWER ON bit high (MSB of Register 09)
3. Set high all Channels that should be power on by
writing “1” on CHENx bits (Registers 08 & 09)
4. Clear POWER ON bit
5. Take PWM pin high
To POWER OFF LED channels:
1. Take PWM pin low
2. Set POWER OFF bit high (MSB of Register 08)
3. Clear all Channels that should be power off by writing
“0” on CHENx bits (Registers 08 & 09)
4. Clear POWER OFF bit
5. Take PWM pin high
POWER ON bit and POWER OFF bit shouldn’t be set at
the same time in order to avoid damage to the part.
POWER ON/OFF channels should be reconfigured every
time the part gets recovered from a POR or shutdown
condition. This also apply if the part is reenabled by software.
If the part is reenabled by software, it is recommended to
take PWM pin low, reenable the part and then follow the
corresponding sequence shown above.
ISINK A[] VSET V[] 136
×
RISET Ω[]
-------------------------------------------- ICH RegisterValue[]
255
-----------------------------------------------------------
×=
FPWM Hz[] 20.736Mhz
FPWM RegisterValue[]
--------------------------------------------------------------------=
Analog Integrated Circuit Device Data
Freescale Semiconductor 47
34844A
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844A
DISABLING LED CHANNELS
The 34844A allows the user to enable and disable each of
the 10 channels separately by writing the corresponding
CHENx bit on Registers 08 and 09 thru I2C.
Since the enable and disable functions reconnects the
feedback circuit of the LED drivers, this shouldn’t be used on
any channel that shuts down either because an open LED
channel condition or because is was previously POWER
OFF. This could cause instability issues since the voltage on
this open LED driver is not substantially above the DHC
regulation voltage (0.75 V typ) and may interfere with the
operation of the dynamic headroom control (DHC) which can
lead to erratic output voltage regulation
FAIL PIN
If a LED fails open in any of the LED strings, the voltage in
that particular LED channel will be close to ground and the
LED open failure is detected. When this happens, a failure is
registered, the FAIL pin is set to its high-impedance stage,
and the channel is shut down.
The FAIL pin cannot be cleared for manual mode unless a
complete power on reset is applied.
However for I2C/SMBUS mode, the FAIL pin can be
cleared by cycling the clear fail bit (CLRFAIL bit = 0 - 1 - 0).
This allows the user to waive any known failure and set the
device for being able to detect any other failure during
operation.
If the fail pin cannot be cleared by software then it indicates
that the failure is because of an over-current in the Boost.
Since this is a critical failure the only way to clear it is by
releasing the part from the over-current condition and then
shutdown the part (Refer to Table 12)
If I2C communication is not present, FAIL condition should
be reset by removing the failure and re-enabling the device
thru the EN pin.
OPTICAL AND TEMPERATURE CONTROL LOOP
The 34844A supports both optical and temperature loop
control.
For temperature loop control, the LED brightness can be
adjusted depending on the temperature of the LEDs.
For optical loop control, the 34844A supports both optical
closed loop backlight control, where the brightness of the
backlight is maintained at a required level by adjusting the
light output, until the desired level is achieved, or with
ambient light control, where the backlight brightness
increases as ambient light increases.
Both temperature and optical loops are supported through
the PIN and NIN pins. Each pin supports a 0 V to VSET
(2.048 V typ.) input range which affects the current through
the LEDs. The PIN pin increases current as the voltage rises
from 0 to VSET. The NIN pin reduces current as the voltage
rises from 0 - VSET.
A 6.98 kohm resistor or higher value must be used at the
ISET pin if the part is configured to use PIN+NIN control loop
functionality, the 80 mA maximum current is achieved at the
higher allowed level of PIN/NIN pins, ensuring the maximum
current of the LED Drivers are not exceeded.
The optical and temperature control loop can be disabled
by I2C setting bits (PINEN & NINEN), or by tying PIN and NIN
pins high (>2.2 V). The LED Driver maximum current is set to
80 mA by using a 3.48 kohm resistor at the ISET pin.
Current on LED Channel (PIN mode) Eqn. 8
Current on LED Channel (NIN mode) Eqn. 9
Current on LED Channel (PIN+NIN mode) Eqn. 10
VPIN and VNIN is the voltage applied on PIN and NIN pins
correspondingly.
For ISINK formula please refer to Equation 1.
LED FAILURE PROTECTION
Open LED Protection
If LED fails open in any of the LED strings, the voltage in
that channel will be pulled close to zero, which will cause the
channel to be disabled. As a result, the boost output voltage
will go to the OVP level and then come down to the regulation
level to continue powering the rest of the LED strings.
Short LED Protection
If an LED shorted in any of the LED strings, the device will
continue to operate without interruption. However, if the
shorted LED happens to be in the LED string with the highest
forward voltage, the DHC circuit will automatically regulate
the output voltage with respect to the new highest LED
voltage. If more LEDs are shorted in the same LED string, it
may cause excessive power dissipation in the channel which
may cause the OTT circuit to trip which will completely
shutdown the device.
OVER-TEMPERATURE PROTECTION
The 34844A has an on-chip temperature sensor that
measures die temperature. If the IC temperature exceeds the
OTT threshold, the IC will turn off all power sources inside the
IC (LED drivers, boost and internal regulators) until the
temperature falls below the falling OTT threshold. Once it
comes back on, it will operate with the default configuration
(refer to Table 14).
SERIAL INTERFACE CONTROL
The 34844A uses an I2C interface capable of operating in
standard (100 kHz) or fast (400 kHz) modes.
The A0/SEN pin can be used an address select pin to
allow more than 2 devices in the system. The A0/SEN pin
should be held low on all chips expect the one to be
addressed, where it is taken HIGH.
IDIM A[] ISINK A[] VPIN V[]
2
------------------------
×=
IDIM A[] ISINK A[] VSET VNIN–()V[]
2
----------------------------------------------------
×=
IDIM A[] ISINK A[] VSET VPIN VNIN–+()V[]
2
--------------------------------------------------------------------------
×=
Analog Integrated Circuit Device Data
48 Freescale Semiconductor
34844A
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
MC34844A
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
NORMAL MODE
In normal operation the 34844A is programed via I2C to
drive up to 50 mA of current through each one of the LED
channels. The 34844A can be configured in master or slave
mode as set by the M/~S pin.
In Master mode, the internal PWM generator frequency is
programmed through the I2C interface. The programmed
value sets the number of 27 kHz clocks (37μs) in one PWM
cycle. The 18-bit resolution allows minimum PWM
frequencies of 110 Hz to be programmed. The resulting
frequency is output on the CK pin.
In slave mode, the CK pin acts as an input. The internal
digital PLL uses this frequency as the PWM frequency.
By setting one device as a master, and connecting the CK
output to the input on a number of slave configured devices,
all PWM frequencies are synchronized together. For this
application A0/SEN pin indicates which device is enable for
I2C control.
In Slave mode, an internal phase lock loop will lock the
internal PWM generator period to the period of the signal
present at the CK pin. The PLL can lock to any frequency
from 110 Hz to 27 KHz provided the jitter is below 1000 ppm.
At frequencies above 1.0 KHz, the PLL will maintain lock
regardless of the transient power conditions imposed by the
user (i.e. going from 0% duty cycle to 100% at 20W LED
display power). Below 1.0 kHz, thermal time constants on the
die are such that the PLL may momentarily lose lock if the die
temperature changes substantially during a large load power
step. As explained below, this anomaly can be avoided by
controlling the rate of change in PWM duty cycle.
To better understand this issue, consider that the on chip
PLL uses a VCO that is subject to thermal drift on the order
of 1000 ppm/C. Further consider that the thermal time
constant of the chip is on the order of single digit
milliseconds. Therefore, if a large power load step is imposed
by the user (i.e. going from 0% duty cycle to 100% duty cycle
with a load power of 20 W), the die will experience a large
temperature wave gradient that will propagate across the
chip surface and thereby affect the instantaneous frequency
of the VCO. As long as such changes are within the
bandwidth of the PLL, the PLL will be able to track and
maintain lock. Exceeding this rate of change may cause the
PLL to lose lock and the backlight will momentarily be
blanked until lock is reacquired.
At 110 Hz lock, the PLL has a bandwidth of approximately
10 Hz. This means that temperature changes on the order of
100 ms are tolerable without losing lock. But full load power
changes on the order of 10 ms (i.e. 110 Hz PWM) are not
tracked out and the PLL can momentarily lose lock. If this
happens, as stated above, the LED drivers are momentarily
disabled until lock is reacquired. This will be manifested as a
perceivable short flash on the backlight immediately after the
load change.
To avoid this problem, one can simply limit large
instantaneous changes in die temperature by invoking only
small power steps when raising or lowering the display power
at low PWM frequencies. For example, to maintain lock while
transitioning from 0% to 100% duty cycle at 20 W load power
and a PWM frequency of 110 Hz would entail stepping the
power at a rate not to exceed 1% per 10 ms. If a load of less
than 20 W is used, then the rate of rise can be increased. As
the locked PWM frequency increases (i.e. use 600 Hz
instead of 110 Hz), the step rate can be further increased to
approximately 4% per 2.0 ms. The exact step rate to avoid
loss of PLL lock is a function of essentially three things: (a)
the composite thermal resistance of the user's PCB
assembly, (b) the load power, and (c) the PWM frequency.
For all cases below 1.0 KHz, simply using a rate of 1% duty
cycle change per PWM period will be adequate. If this is too
slow, the value can be optimized experimentally once the
hardware design is complete. At PWM rates above 1.0 KHz,
it is not necessary to control the rate of change in PWM duty
cycle.
It is important to point out that when operating in the
master mode, one does not need to concern themselves with
loss of lock since the reference clock and the VCO clock are
collocated on the die, and therefore experience the same
thermal shift. Hence in master mode, once lock is initially
acquired, it is not lost and no blanking of the display occurs.
The duty cycle of the PWM in both master and slave mode
is set using a second register on the I2C interface.
An external PWM signal can also be applied in the PWM
pin. This pin is AND’ed with the internal signal, giving the
ability to control the duty cycle either via I2C or externally by
setting any of the 2 signals to 100% duty cycle.
MANUAL MODE
The 34844A can also be used in Manual mode without
using the I2C interface. By setting the pin M/~S High, the LED
dimming will be controlled by the external PWM signal. The
over-voltage protection limit can be settled by a resistor
divider or a zener diode on A0/SEN pin.
During manual mode, all internal Registers are in Default
Configuration, refer Table 14, under this configuration the
PIN and NIN pins are enabled to scale the current capability
per string and may be disable by setting 2.2 V in the
corresponding terminal.
Also in this mode, the device can be enabled as follows:
• EN pin + PWM signal (Two Signals):
In this configuration, the PWM signal applied to PWM pin
will be in charge of controlling the LED dimming and a second
signal will enable or disable the chip through the EN pin.
• PWM Signal tied to SDA pin (Just ONE signal):
In this configuration the PWM pin should be tied to the
SDA pin. The PWM signal applied to PWM pin will be in
Analog Integrated Circuit Device Data
Freescale Semiconductor 49
34844A
FUNCTIONAL DEVICE OPERATION
I2C BUS SPECIFICATION
MC34844A
charge of controlling LED dimming and enabling the device
every time the PWM is active. For this configuration the EN
pin should be LOW.
I2C BUS SPECIFICATION
The 34844A is a unidirectional device that can only be written by an external control unit. Since the device is a 7 bit address
device (1110110), the control unit needs to follow a specific data transfer format which is shown in Table 26.
Figure 26. A Complete Data Transfer
For a complete data transfer, please use this format in the
following order:
1. START condition
2. 34844A device address and Write instruction (R/W = 0)
3. First data pack, it corresponds to the 34844A register
that needs to be written. (refer to Table 13)
4. Second data pack, it corresponds to the value that
should be written to that register. (refer to Table 13)
5. STOP condition
I2C variables description:
• START: this condition occurs when SDA changes from
HIGH to LOW while SCK is HIGH.
• ACKNOWLEDGE: The acknowledge clock pulse is
generated by the Master (Control Unit).
• The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse.The receiver (34844A) must pull
down the SDA line during this acknowledge pulse to
indicate that the data was correctly written.
• Bits in the first byte: The first seven bits of the first bite
make up the slave address. The eighth bit is the LSB (least
significant bit), which determines the direction of the
message (Write = 0)
For the 34844A device, when an address is sent, each of
the devices in a system compares the first seven bits after
the START condition with its address. If they match, the
device considers itself addressed by the control unit as a
slave-receiver.
• STOP: this condition occurs when SDA changes from
LOW to HIGH while SCK is HIGH
For more information about “I2C BUS SPECIFICATION”
please refer to the following link:
http://www.nxp.com/acrobat_download/literature/
9398/39340011.pdf
Analog Integrated Circuit Device Data
50 Freescale Semiconductor
34844A
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MC34844A
LOGIC COMMANDS AND REGISTERS
All registers and POWER ON/OFF channels should be
reconfigured every time the part gets recovered from a POR
or shutdown condition.
The configuration sequence every time the part is power
up should be as follows:
1. Take the PWM pin low
2. Power up the part
3. Configure all registers
4. Take the PWM pin High
For configuring the part once in operation it is
recommended to follow this sequence:
1. Take the PWM pin low
2. Configure the registers
3. Take the PWM pin High
Special considerations should be taken for re-configuring
POWER ON/OFF functions, please refer to the POWER OFF
and POWER ON LED CHANNELS section.
Table 13. Write Registers
reg / db D7 D6 D5 D4 D3 D2 D1 D0
00 OVP3 OVP2 OVP1 OVP0 NINEN PINEN EN
01 CLRI2C SETI2C
04 FPWM5 FPWM4 FPWM3 FPWM2 FPWM1 FPWM0
05 FPWM11 FPWM10 FPWM9 FPWM8 FPWM7 FPWM6
06 FPWM17 FPWM16 FPWM15 FPWM14 FPWM13 FPWM12
07 DPWM7 DPWM6 DPWM5 DPWM4 DPWM3 DPWM2 DPWM1 DPWM0
08 PWR_OFF CHEN4 CHEN3 CHEN2 CHEN1 CHEN0
09 PWR_ON CLRFAIL ALL_OFF CHEN9 CHEN8 CHEN7 CHEN6 CHEN5
14 BST1 BST0
F0 ICH0_7 ICH0_6 ICH0_5 ICH0_4 ICH0_3 ICH0_2 ICH0_1 ICH0_0
F1 ICH1_7 ICH1_6 ICH1_5 ICH1_4 ICH1_3 ICH1_2 ICH1_1 ICH1_0
F2 ICH2_7 ICH2_6 ICH2_5 ICH2_4 ICH2_3 ICH2_2 ICH2_1 ICH2_0
F3 ICH3_7 ICH3_6 ICH3_5 ICH3_4 ICHG_3 ICH3_2 ICH3_1 ICH3_0
F4 ICH4_7 ICH4_6 ICH4_5 ICH4_4 ICH4_3 ICH4_2 ICH4_1 ICH4_0
F5 ICH5_7 ICH5_6 ICH5_5 ICH5_4 ICH5_3 ICH5_2 ICH5_1 ICH5_0
F6 ICH6_7 ICH6_6 ICH6_5 ICH6_4 ICH6_3 ICH6_2 ICH6_1 ICH6_0
F7 ICH7_7 ICH7_6 ICH7_5 ICH7_4 ICH7_3 ICH7_2 ICH7_1 ICH7_0
F8 ICH8_7 ICH8_6 ICH8_5 ICH8_4 ICH8_3 ICH8_2 ICH8_1 ICH8_0
F9 ICH9_7 ICH9_6 ICH9_5 ICH9_4 ICH9_3 ICH9_2 ICH9_1 ICH9_0
FA ICHG_7 ICHG_6 ICHG_5 ICHG_4 ICHG_3 ICHG_2 ICHG_1 ICHG_0
Table 14. Register Description
Register Name Default Value
(Hex) Description
EN 1Chip Enable by software.
PINEN 1PIN pin enable (0=off, 1 =on)
NINEN 1NIN pin enable (0=off, 1 =on)
OVP[3:0] FOVP voltage
SETI2C 0SET I2C communication (Disable SM Bus Mode)
CLRI2C 0Clear set I2C
Analog Integrated Circuit Device Data
Freescale Semiconductor 51
34844A
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MC34844A
FPWM[17:0] 300 PWM Frequency
DPWM[7:0] FF PWM Duty Cycle (FFh =100%)
CHEN[9:0] 3FF Channel Enable (0=off, 1=on)
ALL_OFF 0All 10 channels OFF at the same. In order to reactivate channels this bit should be clear.
CLRFAIL 0Clear fail if channels are re-enable.
PWR_OFF 0POWER OFF LED channels (0=disable, 1=enable)
PWR_ON 0POWER ON LED channels (0=disable, 1=enable)
BST[1:0] 2Boost Frequency (160,320,650,1300 kHz) [0h=160 Hz]
ICH#[7:0] FF Channel Current Program (FFh = Maximum Current)
ICHG[7:0] FF Global Current Program
Table 15. Over-voltage Protection
Register (hex) OVP Value (vOLTS)
211
315
419
523
627
731
835
939
A43
B47
C51
D55
E59
F62
Table 14. Register Description
Register Name Default Value
(Hex) Description
Analog Integrated Circuit Device Data
Freescale Semiconductor 52
34844A
TYPICAL APPLICATIONS
MC34844A
TYPICAL APPLICATIONS
Figure 27. Manual Mode (Single Wire Control)
Conditions: VIN = 24 V, VOUT = 47 V, Load = 16S10P, ILED = 60 mA, OVP = 53V, fSW = 300 kHz
Figure 28. Manual Mode (Two Wire Control)
Conditions: VIN = 24 V, VOUT = 47 V, Load = 16S10P, ILED = 60 mA, OVP = 53V, fSW = 300 kHz
VIN = 24V
0
0
0
VOUT
0
0
0
0
VDC1
VDC1
VCC
0
VOUT
Master CK
LED MATRIX (16S10P)
MANUAL MODE (Single Wire Control)
Output
OVP = 55V
5.6K5.6K
+
47uF
+
47uF
2.2uF2.2uF
3.3K3.3K
20K20K
309K309K
5.1K5.1K
+
13.8uF
+
13.8uF
150K150K
1.8nF1.8nF
U1
34844
U1
34844
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
56pF56pF
CLKCLK
D1D1
2 1
2.2uF2.2uF
22uH22uH
1 2
2.2uF2.2uF
1.0K
VIN = 24V
0
0
0
0
VCC
VOUT
VOUT
0
VDC1
VDC1
0
0
0
Master CK
Output
LED MATRIX (16S10P)
OVP = 55V
MANUAL MODE (Two Wire Control)
Unit
Control
EN
PWM
2.2uF2.2uF
D5D5
2 1
22uH22uH
1 2
1.8nF1.8nF
2.2uF2.2uF
3.3K3.3K
150K150K
+
13.8uF
+
13.8uF
U2
34844
U2
34844
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
2.2uF2.2uF
20K20K
5.1K5.1K
5.6K5.6K
56pF56pF
+
47uF
+
47uF
309K309K
1.0K
Analog Integrated Circuit Device Data
Freescale Semiconductor 53
34844A
TYPICAL APPLICATIONS
MC34844A
Figure 29. I2C (Master Mode)
Conditions: VIN = 24 V, VOUT = 47 V, Load = 16S10P, ILED = 60 mA, OVP = 53V, fSW = 300 kHz
Figure 30. I2C (Slave Mode)
Conditions: VIN = 24 V, VOUT = 47 V, Load = 16S10P, ILED = 60 mA, OVP = 53V, fSW = 300 kHz
SDA
SCK
A0SEN_Master
EN_Master
0
0
0
VCC
VOUT
0
VDC1
VDC1
0
0
0
VIN = 24V
0
VDC1
MASTER CK
I2C MODE (Master Mode)
OUTPUT
ISET = 60mA
LED MATRIX (16S10P)
CONTROL UNIT
* FOR I2C MODE - SETI2C bit should be set High.
* FOR SM-BUS MODE - EN pin should be connected to
GND or taken low by the Control Unit.
4.64K4.64K
100pF100pF
100K100K
220pF220pF 220pF220pF
2.2uF2.2uF
220pF220pF
2.2uF2.2uF
3.3K3.3K
10uF10uF
5.6K5.6K
4.7uF4.7uF
220pF220pF
220pF220pF
+
30uF
+
30uF
220pF220pF
U9
MC34844A
U9
MC34844A
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
D533D533
2 1
47uH47uH
1 2
+
47uF
+
47uF
4700pF4700pF
220pF220pF 220pF220pF
2.2uF2.2uF
220pF220pF 220pF220pF
1.0K
EN_Slave
SDA
SCK
A0SEN_Slave
0
0
0
VCC
VOUT
0
VDC1
0
0
0
VIN = 24V
0
VDC1
0
MASTER CK
I2C MODE (Slave Mode)
INPUT
ISET = 60mA
LED MATRIX (16S10P)
CONTROL UNIT
* FOR I2C MODE - SETI2C bit should be set High.
* FOR SM-BUS MODE - EN pin should be connected to
GND or taken low by the Control Unit.
220pF220pF
100pF100pF
3.3K3.3K
47uH47uH
12
220pF220pF
220pF220pF
220pF220pF
220pF220pF
2.2uF2.2uF
220pF220pF
+
30uF
+
30uF
D553D553
2 1
5.6K5.6K
2.2uF2.2uF
4.7uF4.7uF
2.2uF2.2uF
4.64K4.64K
4700pF4700pF
10uF10uF
220pF220pF
100K100K
220pF220pF
U11
MC34844A
U11
MC34844A
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
220pF220pF
+
47uF
+
47uF
220pF220pF
1.0K
Analog Integrated Circuit Device Data
Freescale Semiconductor 54
34844A
TYPICAL APPLICATIONS
MC34844A
Figure 31. HIGH VOUT application (Manual Mode)
Conditions: VIN = 60 to 72V, VOUT = 120 V, Load = 40S8P, ILED = 60 mA, OVP = 125 V, fSW = 300 kHz
EN_DLY
VDC2
EN_DLY
PWM = 200Hz (5V)
0
VIN = 60V to 72V
0
0
0
0
VOUT = 120V
VOUT
0
VDC1
VDC1
0
0
0
0
0
0
ISET =
60mA
LED MATRIX (40S8P)
OVP = 125V
1010
PDS3200PDS3200
1
3
2
4.64K4.64K
220pF220pF220pF220pF 220pF220pF
0.1UF0.1UF3SMBJ5941B-TP
47V
3SMBJ5941B-TP
47V
2 1
18K18K
6.8K6.8K
27K27K
100pF100pF 200k200k
270K270K
+
10uF
250V
+
10uF
250V
2.2uF2.2uF
MMSZ5268BT1G
82V
MMSZ5268BT1G
82V
2 1
10uF
100V
10uF
100V
FDS2572FDS2572
1
2
3
5
8
6
4
7
2.2uF2.2uF
150UH
7447709151
150UH
7447709151
220pF220pF
3.3nF3.3nF
+
47uF
100V
+
47uF
100V
220pF220pF
+
10uF
250V
+
10uF
250V
+
10uF
250V
+
10uF
250V
220pF220pF
10.0K10.0K
0.1UF
100V
0.1UF
100V
MC34844AMC34844A
VIN
1
VDC1
28
COMP
29
EN
7CK
24
M/~S
30
PWM
25
SCK
27
SDA
26
A0/SEN
6
ISET
19
PIN
20
NIN
21
SWA 4
SWB 3
VOUT 32
PGNDA 5
PGNDB 2
VDC2
31
FAIL 18
I0 8
I1 9
I2 10
I3 11
I4 12
I5 13
I6 14
I7 15
I8 16
I9 17
VDC3
23
SLOPE
22
GND 33
220pF220pF
2.2uF2.2uF
2.2uF2.2uF
1uF
250V
1uF
250V
220pF220pF
1.0k
Analog Integrated Circuit Device Data
Freescale Semiconductor 55
34844
COMPONENTS CALCULATION
COMPONENTS CALCULATION
The following formulas are intended for the calculation of
all external components related with the Boost converter and
Network compensation.
In order to calculate a Duty Cycle, the internal losses of the
MOSFET and Diode should be taken into consideration.
The average input current depends directly to the output
current when the internal switch is off.
Inductor
For calculating the Inductor we should consider the losses
of the internal switch and winding resistance of the inductor.
It is important to look for an inductor rated at least for the
maximum input current.
Input Capacitor
The input capacitor should handle at least the following
RMS current.
Output Capacitor
For the output capacitor selection the internal current
sense gain (CSG) and the Transconductance should be
taken in consideration.
The CSG is the internal RSENSE times the current sense
amplifier gain (ACSA).
The output voltage ripple (ΔVOUT) depends on the ESR of
the Output capacitor, for a low output voltage ripple it is
recommended to use Ceramic capacitors that usually have
very low ESR. Since ceramic capacitor are expensive,
Electrolytic or Tantalum capacitors can be mixed with
ceramic capacitors to have a cheaper solution.
The output capacitor should handle at least the following
RMS current.
Network Compensation
Since this Boost converter is current controlled, Type II
compensation is needed.
I order to calculate the Network Compensation, first we
need to calculate all Boost Converter components.
For this type of compensations we need to push out the
Right Half Plane Zero to higher frequencies where it can’t
affect the overall loop significantly.
The Crossover frequency must be set much lower than the
location of the Right half plane zero
Since our system has a fixed Slope compensation set by
RSLOPE, RCOMP should be fixed for all configurations.
CCOMP1 and CCOMP2 should be calculated as follows:
DVout VDVin–+
Vout VDVSW
–+
---------------------------------------------
=
Iinavg
Iout
1D–
-------------
=
LVin VSW
–Iin
avg rw×()–()D×
Iinavg r×FSW
×
----------------------------------------------------------------------------------
=
Iinmax Iinavg
Vin Vout Vin–()×
2LF
SW Vout×××
-------------------------------------------------
+=
IrmsCin
Vin Vout Vin–()×
2LF
SW Vout×××
-------------------------------------------------
⎝⎠
⎛⎞
0.3×=
CSG ACSA RSense
×=
Cout RComp 5G
M
×Iout L×××
1D–()Vout CSG××
--------------------------------------------------------------------
=
ESRCout
Vout Vout FSW L××Δ×
Vout 1 D–()×
---------------------------------------------------------------
=
IrmsCout Iout D
1D–
-------------×=
fRHPZ
Vout 1 D–()
2
×
Iout 2 πL×××
----------------------------------------
=
fCross
fRHPZ
5
---------------
=
RComp 5.6kohm=
Analog Integrated Circuit Device Data
56 Freescale Semiconductor
34844
COMPONENTS CALCULATION
In order to improve the transient response of the boost, on
the 34844A, a resistor divider has been implemented from
the PWM pin to ground with a connection to the
compensation network. This configuration should inject a
1.0 V signal to the COMP pin and the Thevenin-equivalent
resistance of the divider is close to RCOMP, i.e. RCOMP = 6.8 k
and RPCOMP= 27 k for a 5.0 V PWM signal.
Slope Compensation
Slope Compensation can be expressed either in terms of
Ampers/Second or as Volts/Second, through the use of the
transfer resistance.
The following formula express the Slope Compensation in
terms of V/μs:
In order to have this slope compensation, the following
resistor should be set.
Variable Definition
D= Boost Duty Cycle
VOUT= Output Voltage
VD= Diode Forward Voltage
VIN= Input Voltage
VSW= VDROP of Internal Switch
ΔVOUT= Output Voltage Ripple Ratio
IINAVG= Average Input Current
IOUT= Output Current
r=Input Current Ratio
IINMAX= Maximum input current
IRMSCIN= RMS current for Input Capacitor
IRMSCOUT= RMS current for Output Capacitor
L= Inductor
RW= Inductor winding DC Resistance
fSW= Boost Switching Frequency
CSG= Current Sense Gain = 0.2 V/A
ACSA= Current Sense Amplifier Gain = 9
RSENSE= Current Sense Resistor = 22mohm
COUT= Output Capacitor
RCOMP= Compensation Resistor
GM= OTA Transconductance
ESRCOUT= ESR of Output Capacitor
fRHPZ= Right Half Plane Zero Frequency
fCROSS= Crossover Frequency
CCOMP1= Compensation Capacitor
CCOMP2= Shunt Compensation Capacitor
VSLOPE= Slope Compensation (V/μs)
RSLOPE= External Resistor for Slope Compensation
CComp1
2
fCross RComp π2×××
--------------------------------------------------------
=
CComp2
GM
6.28 FSW
×
---------------------------
=
PWM
COMP PIN
R
PCOMP
R
COMP
C
COMP1
C
COMP2
VSLOPE
Vout Vin–()CSG×
L2×
----------------------------------------------------
=
Where “L” is in μH
RSLOPE
33 3
×10
VSLOPE 5×
-----------------------------
=
Analog Integrated Circuit Device Data
Freescale Semiconductor 57
34844
LAYOUT GUIDELINES
LAYOUT GUIDELINES
RECOMMENDED STACK-UP
The following table shows the recommended layer stack-
up for the signals to have good shielding and Thermal
Dissipation.
DECOUPLING CAPS
It is recommended to place decoupling caps of 100 pf at
the beginning and at the end of any power signal traces to
filter high frequency noise.
Decoupling caps of 100 pf should be also placed at the
end of any long trace to cancel antenna effects on it.
These caps should be located as closed as possible to the
point to be decoupled and the connection to GND should be
as short as possible.
SM-BUS/I2C COMMUNICATION AND CLOCK
SIGNALS (SDA, SCK AND CK)
To avoid contamination of these signals by nearby high
power or high frequency signals, it is a good practice to shield
them with ground planes placed on adjacent layers. Make
sure the ground plane is uniform through the whole signal
trace length.
Figure 32. Recommended shielding for critical signals.
These signals shall not run parallel to power signals or
other clock signals in the same routing layer. If they have to
cross or to be routed close to a power signal, it is a good
practice to trace them perpendicularly or at 45° on a different
layer to avoid coupling noise.
SWITCHING NODE (SWA & SWB)
The components associated to this node must be placed
as close as possible to each other to keep the switching loop
small enough so that it does not contaminate other signals.
However, care must be taken to ensure the copper traces
used to connect these components together on this node are
capable to handle the necessary current and voltage.
As a reference, a 10 mils trace with a thickness of 1.0 oz.
of copper is capable of handling one ampere.
Traces for connecting the inductor, input and output caps
should be as wide and short as possible to avoid adding
inductance or resistance to the loop. The placement of these
components should be selected far away from sensitive
signals like compensation, feedback and internal regulators
to avoid power noise coupling.
COMPENSATION COMPONENTS
Components related with COMP pin need to be placed as
close as possible to the pin.
FEEDBACK SIGNAL
The trace of the feedback signal (VOUT) should be routed
perpendicularly or at 45° on a different layer to avoid coupling
noise, preferably between ground or power planes.
Figure 33. Feedback Signal Tracing
Table 16. Layer Stacking Recommendations
Stack-Up
Layer 1 (Top) Signal
Layer 2 (Inner 1) Ground
Layer 3(Inner 2) Signal
Layer 4 (Bottom) Ground
Signal
Ground Plane
Ground Planes
Signal
DO
S
S
S
w
w
w
i
i
it
t
t
c
c
ch
h
hi
i
in
n
ng
g
gN
N
No
o
od
d
de
e
e
I
I
In
n
np
p
pu
u
u
t
t
t
C
C
Ca
a
ap
p
p
O
O
Ou
u
ut
t
t
p
p
pu
u
u
t
t
tC
C
Ca
a
ap
p
p
On State
Off State
C
C
C
o
o
om
m
mp
p
pe
e
en
n
ns
s
sa
a
a
t
t
ti
iio
o
on
n
n
F
F
Fe
e
ee
e
ed
d
db
b
ba
a
ac
c
ck
k
k
S
S
Si
i
ig
g
gn
n
na
a
al
ll
Analog Integrated Circuit Device Data
Freescale Semiconductor 59
34844
PACKAGING
PACKAGE DIMENSIONS
EP SUFFIX
32-PIN
98ASA10800D
REVISION O
Analog Integrated Circuit Device Data
60 Freescale Semiconductor
34844
PACKAGING
PACKAGE DIMENSIONS
EP SUFFIX
32-PIN
98ASA10800D
REVISION O
Analog Integrated Circuit Device Data
Freescale Semiconductor 61
34844
REVISION HISTORY
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES
3.0 11/2008 • Initial Release
4.0 3/2009 • Added PWM Pin to Maximum Voltages in Maximum Rating Table.
• Added Disabling LED Channels
• Rewrote Fail Pin section
• Added I2C Bus Specification
5.0 5/2009 • Corrected Compensation Components paragraph on page 32.
6.0 9/2009 • Added Part Number MC34844AEP/R2.
7.0 3/2010 • Combined Complete Data sheet for Part Numbers MC34844 and MC34844A to this data
sheet.
8.0 7/2010 • Removed OVP=4h, OVP=3h and OVP=2h rows from Table 11.
• PWM and CK Frequency range changed in Electrical Characteristics table.
9.0 3/2012 • Added resistor between VDC1 and VDC3 on the application drawings. Added to notes
for VDC3 on pages 9, 14, 37, and 42.
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or +1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Freescale and the Freescale logo are trademarks of Freescale
Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Qorivva, S12 MagniV,
SMARTMOS and Xtrinsic are trademarks of Freescale
Semiconductor, Inc. ARM is the registered trademark of ARM
Limited. The Power Architecture and Power.org word marks and the
Power and Power.org logos and related marks are trademarks and
service marks licensed by Power.org. All other product or service
names are the property of their respective owners. ©2012 Freescale
Semiconductor, Inc.
MC34844
Rev. 9.0
3/2012
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
to products herein. Freescale Semiconductor makes no warranty,
representation or regarding the suitability of its products for any particular
purpose, nor does Freescale Semiconductor assume any liability arising out
of the or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale Semiconductor data
sheets and/or specifications can and do vary in different applications and
actual performance may vary over time. All operating parameters, including
“Typicals”, be validated for each customer application by technical experts.
Freescale Semiconductor does not convey any license under its patent rights
nor the rights of others. Freescale Semiconductor products are designed,
intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the Freescale
Semiconductor product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Freescale Semiconductor
products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Freescale Semiconductor and its officers, employees,
subsidiaries, affiliates, and harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Freescale Semiconductor
was negligent regarding the design or manufacture of the part.
