i.MX27 and i.MX27L Data Sheet, Rev. 1.8
Freescale Semiconductor 11
Functional Description and Application Information
The ARM926EJ-S processor is a fully synthesizable macrocell, with a configurable memory system. Both
instruction and data caches will be 16 kbytes on the platform. The cache is virtually accessed and virtually
tagged. The data cached has physical tags as well. The MMU provides virtual memory facilities which are
required to support various platform operating systems such as Symbian OS, Windows CE, and Linux. The
MMU contains eight fully associative TLB entries for lockdown and 64 set associative entries. Refer to
the ARM926E J-S Technical Reference Manual for mo re info r m a tion .
2.3.5 Advanced Technology Attachment (ATA)
The Advanced Technology Attachment (ATA) host controller complies with the ATA/ATAPI-6
specification. The primary use of the ATA host controller is to interface with IDE hard disc drives and
Advanced T echnology Attachment Packet Interface (AT API) optical disc drives. It interfaces with the AT A
device over a number of ATA signals.
This host contro ller supports inte rface protocols as specified in ATA/AT API-6 standard, as follows:
• PIO mode 0, 1, 2, 3, and 4
• Multiword DMA mode 0, 1, and 2
• Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher
• Ultra DMA mode 5 with bus clock of 80 MHz or higher
Before a ccessing the ATA bus, the host must program the timing parameters to be used on the ATA bus.
The timing parameters control the timing on the ATA bus. Most ti ming parameters are progr ammable as a
number of clock cycles (1 to 255). Some are implied. All of the ATA device- internal registers are visible
to users, and they are defined as mirror registers in ATA host controller. As specified in ATA/ATAPI-6
standard, all the features/functions are implemented by reading/writing to the device’s internal registers.
There are basically two protocols that can be active at the s ame time on the ATA bus, as follows:
• The first and simplest protocol (PIO mode acc ess) can be started at any time by the ARM926 to
the AT A bus. The PIO mo de is a slow protocol, mainly intended to be used to program an ATA disc
drive, but also can be used to transfer data to/from the disc drive.
• The second protocol is the DMA mode access. DMA mode is started by t he ATA interface after
receiving a DMA request from the drive, and only if the ATA interface has been programmed to
accept the DMA reque st. In DMA mode, either multiword-DMA or ultra- DMA protocol is used
on the ATA bus. All transfers between FIFO and the host IP or DMA IP bus are zero wait states
transfer, so a high-speed transf er between FIFO and DMA/host bus is pos sible.
2.3.6 Digital Audio MUX (AUDMUX)
The Digital Audio MUX (AUDMUX) provides programmable interconnecting for voice, audio, and
synchronous data routing between host s erial interfaces—for example, SSI, SAP, and peripheral serial
interfaces—suc h as, audio and voice codecs. The AUDMU X allows audio sys tem connectivity to be
modified through programming, as opposed to altering the design of the system into which the chip is
designed. The design of the AUDMUX allows multiple simultaneous audio/ voice/data flows between the
ports in point-to-point or point-to-multipoint configurations.