POWER MANAGEMENT
1
SC2598
Low Voltage DDR
Termination Regulator
Features
Input to linear regulator (VIN): 1.0V to 3.6V
Output (VTT): 0.5V to 1.8V
Bias Voltage (VDD): 2.35V to 3.6V
Up to 3A sink or source from VTT for DDR through
DDR4
+ 1% over temperature (with respect to VDDQ/2, in-
cluding internal resistor divider variation) VREF and
VTT
Logic-level enable input
Built in soft-start
Thermal shutdown with auto-restart
Over current protection
Minimal output capacitance
Package: SOIC8-EDP
Applications
DDR Memory Termination
Description
The SC2598 is designed to meet the latest JEDEC speci-
cation for low power DDR3 and DDR4, while also support-
ing DDR and DDR2. The SC2598 regulates up to + 3A for
VTT and up to + 40mA for VREF.
The SC2598 also provides an accuracy of +1% over tem-
perature (which takes into account the internal resistor
divider) for VREF and VTT for the memory controller and
DRAM.
SC2598 protection features include thermal shutdown
with auto-restart for VTT and over-current limit for both
VTT and VREF.
Under-Voltage-Lock-Out circuits are included to ensure
that the output is o when the bias voltage falls below its
threshold, and that the part behaves elegantly in power-
up or power-down.
The low external parts count combined with industry
leading specications make SC2598 an attractive solution
for DDR through DDR4 termination.
VINVDD
GND
VREF
VTTS
VTTVDDQ
EN
VDDQ
C
VDD
C
IN
C
VTT
C
VREF (1)
1µF
0.1µF
2x10µF
3x10µF
Typical Application Circuit
Rev. 2.1
Note:
(1) This component is optional.
© 2016 Semtech Corporation
SC2598
2
Pin Conguration
1
2
3
4 5
6
7
8
GND
EN
VTTS
VREF VDDQ
VDD
VIN
VTT
Thermal
PAD
Ordering Information
Marking Information
SC2598
yyww
xxxxx
Notes:
(1) Available in tape and reel only. A reel contains 2500 devices.
(2) Lead-free packaging only. Device is WEEE and RoHS compliant
and halogen-free.
Device Package
SC2598SETRC(1)(2) SOIC8-EDP
SC2598EVB Evaluation Board
yyww = Date Code
xxxxx = Semtech Lot Number
SC2598
3
Exceeding the above specications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specied in the Electrical Characteristics section is not recommended.
Notes:
(1) HBM: tested according to ANSI/ESDA/JEDEC JS-001.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
(3) Based upon lab measurement on EVB board: 3 x 2 (in), 4 layer FR4 PCB with thermal vias under the exposed pad.
Absolute Maximum Ratings
VIN (V) ..................................... -0.3 to 4.3
VDD to GND (V) ............................ -0.3 to 4.3
VTT to GND (V) ............................ -0.3 to VDD
EN (V) ..................................... -0.3 to 6.0
Other pins ................................. -0.3 to 4.3
ESD Protection Level(1) (kV) ................. 4
Thermal Information
Thermal Resistance, Junction to Ambient(2) (°C/W) ... 46
Thermal Resistance, Junction to Ambient(3) (°C/W) ... 38
Maximum Junction Temperature (°C) ..............+150
Storage Temperature Range (°C) ............ -65 to +150
Peak IR Reflow Temperature (10s to 30s) (°C) ....... +260
Unless otherwise noted TJ = -40 to +125°C, VIN = 1.2V, VDD = 3.3V, VDD Q= 1.2V . Typical values are at TA = 25°C.
Parameter Symbol Conditions Min Typ Max Units
Input Supplies
LDO Supply Voltage VIN 1 3.6 V
VDD Supply Voltage VDD 2.35 3.6 V
VDD UVLO Threshold
Measured at VDD pin, rising edge 2.0 2.25
V
Measured at VDD pin, falling edge 1.95 2.15
VDD UVLO Hysteresis 0.1 V
Quiescent Current for VDD IQLoad =0A, EN = High, VVDDQ > 1V 415 700 µA
Shutdown Current for VDD IQSD
Load =0A, EN = Low, VVDDQ > 1V, IREF = 0A 160 400 µA
Load =0A, EN = Low, VVDDQ = 0V, IREF = 0A 100 160 µA
Quiescent Current for VIN IIN Load =0A, EN = High 3 30 µA
Shutdown Current for VIN IINSD Load =0A, EN = Low 3 20 µA
VTT Output
Output Voltage Range VTT 0.5 1.8 V
Output Voltage Tolerance with
respect to VDDQ/2 Load = 0A, VTT = 0.5V to 1.8V -1 +1 %
Electrical Characteristics
SC2598
4
Parameter Symbol Conditions Min Typ Max Units
Load Regulation -2A < Load < 2A -25 +25 mV
On-Resistance
High-Side MOSFET (source), Load = 0.1A 50 100 150
mΩ
Low-Side MOSFET (sink), Load = 0.1A 40 140 300
Discharge MOSFET On-Resistance EN = Low 8 Ω
Reference Input/Output
VDDQ Voltage Range 1 3.6 V
VDDQ Input Bias Current 0 10 μA
Tolerance with respect to VDDQ/2 Load = 0A, VREF = 0.5V to 1.8V -1 1 %
VREF Source Current Limit 40
mA
VREF Sink Current Limit - 40
Protection
Thermal Shutdown Threshold 160 0C
Thermal Restart Hysteresis 20 0C
Output Current Limit Threshold Ambient Temperature: 25 0C 3.7 4.3 A
Soft-Start
VTT Soft-Start Time From EN = High to VTT = 90% VREF 40 μs
Logic
EN Logic Threshold
EN = High 1.7
V
EN = Low 0.3
EN Input Current -1 1 μA
Electrical Characteristics (continued)
SC2598
5
Block Diagram
DRIVER
LOGIC
VIN
7
VTT
8
GND
1
VDD 6
UVLO
Soft-Start
EN 2
VTTS3
VDDQ 5+
-
+
-
VREF 4
EN\
R
R
Thermal
Shutdown
Pin # Pin Name Pin Function
1 GND Ground reference for the IC.
2 EN Logic input to enable or disable the VTT output. If EN pin is grounded to shut down the linear regulator,
VREF remains active.
3VTTS VTT output sense input. Connect VTTS to the output at the output capacitor to implement remote sense.
4 VREF The reference output, equal to one half of VDDQ. Connect a 100nF capacitor from this pin to GND.
5 VDDQ External reference input.
6 VDD Input bias voltage. Connect a ceramic capacitor from this pin to GND.
7 VIN LDO input. Connect ceramic capacitors from this pin to GND.
8VTT Output of the linear regulator. Connect ceramic capacitors from this pin to GND.
PAD NC Thermal pad. Not electrically connected. Connect to the GND plane using multiple vias for optimal heat
sinking.
Pin Descriptions
SC2598
6
Detailed Application Circuit
VIN
1GND
EN
VTTS
VREF VDDQ
VDD
VIN
VTT
6
5
7
8
2
3
4
C
1
C
2
C
5
C
8
C
7
VTT
3.3V
VREF
EN
C
3
C
4
R
1
100 Ohm
C
6
Reference Designator Description Value Part Number Manufacture
C1, C2, C3, C4, C5, Ceramic Capacitor 10uF/0805/X7R GRM21BR71A106KE51 Murata
C6Ceramic Capacitor 1uF/0603/X7R GRM188R71A105KA61D Murata
C7, C8Ceramic Capacitor 0.1uF/0603/X7R GRM188R71H104KA93D Murata
Bill Of Materials
SC2598
7
Typical Characteristics
0.6V VTT Regulation Sink/Source
0.580
0.590
0.600
0.610
0.620
-3 -2 -1 0 1 2 3
Sink Source
250C
850C
-400C
Characteristics in this section are based upon the detailed application circuit on page 6.
0.75V VTT Regulation Sink/Source
0.9V VTT Regulation Sink/Source
0.6V VREF Regulation Sink/Source
0.75V VREF Regulation Sink/Source
0.9V VREF Regulation Sink/Source
VTT Current (A)
VTT Regulation (V)
0.730
0.740
0.750
0.760
0.770
-3 -2 -1 0 1 2 3
Sink Source
250C
850C
-400C
VTT Current (A)
VTT Regulation (V)
0.880
0.890
0.900
0.910
0.920
-3 -2 -1 0 1 2 3
Sink Source
250C
850C
-400C
VTT Current (A)
VTT Regulation (V)
0.580
0.590
0.600
0.610
0.620
-0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05
25
0
C
85
0
C
-40
0
C
SourceSink
VREF Current (A)
VREF Regulation (V)
0.730
0.740
0.750
0.760
0.770
-0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05
Sink Source
25
0
C
85
0
C
-40
0
C
VREF Current (A)
VREF Regulation (V)
0.880
0.890
0.900
0.910
0.920
-0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05
Sink Source
25
0
C
85
0
C
-40
0
C
VREF Current (A)
VREF Regulation (V)
VIN = 1.2V, VDDQ = 1.2V, VDD = 3.3V VIN = 1.2V, VDDQ = 1.2V, VDD = 3.3V
VIN = 1.5V, VDDQ = 1.5V, VDD = 3.3V VIN = 1.5V, VDDQ = 1.5V, VDD = 3.3V
VIN = 1.8V, VDDQ = 1.8V, VDD = 3.3V VIN = 1.8V, VDDQ = 1.8V, VDD = 3.3V
SC2598
8
Typical Characteristics
Start-Up and Shutdown Using EN
Characteristics in this section are based upon the detailed application circuit on page 6.
Start-Up Using VDDQ
VIN = 1.2V, VDD = 3.3V, VREF = 0A, VTT = 0A
Load Transient Source and Sink: -1A to +1A
VTT (200mV/div)
VREF (200mV/div)
VDDQ (200mV/div)
EN (2V/div)
500us/div
2ms/div
VREF (200mV/div)
VTT (200mV/div)
VDDQ (200mV/div)
VDD (1V/div)
Source Current Load (1A/div)
VTT (20mV/div)
200us/div
Shutdown Using VDD
VDDQ = 1.2V, VIN = 1.2V, VDD = 3.3V
VREF = 0A, VTT = 0A, VIN = 1.2V
VREF = 40mA, VTT = 1A
VDD (1V/div)
VREF (200mV/div)
VTT (200mV/div)
5ms/div
VIN = VDDQ (200mV/div)
Sink Current Load (1A/div)
Current Limit with VTT Shorted
VDDQ = 1.2V, VIN = 1.2V, VDD = 3.3V
10ms/div
VTT (100mV/div)
Input Current (1A/div)
Start-Up Using VDD
VTT (200mV/div)
1ms/div
VIN = VDDQ (200mV/div)
VREF (200mV/div)
VDD (1V/div)
VREF = 40mA, VTT = 1A
7mV
SC2598
9
VTT Output
VTT starts to ramp up when EN and VDD meet their startup
thresholds. SC2598 regulates VTT to the voltage at VREF
and can support up to 3A for sourcing or sinking
capability.
To achieve tight regulation and fast dynamic response at
VTT, it is recommended to connect the VTTS sense signal
to VTT at the ceramic output capacitors.
VREF Output
VREF starts to ramp up when VDD meets the UVLO thresh-
old. SC2598 regulates VREF to one-half of VDDQ. To
reduce the component count and provide a good accu-
racy reference for VTT, SC2598 includes an internal resistor
divider network. SC2598 is capable of sinking or sourcing
up to 40mA at VREF. To reduce the component count
further, SC2598 does not require the user to have a local
ceramic capacitor at the VREF pin - but it is recommended
to layout with a capacitor place holder.
EN Input
The EN pin is used to enable and disable VTT only; it does
not control VREF. When EN is pulled low, the VTT output is
discharged internally to ground through an 8Ω FET.
Protection
SC2598 has thermal protection with auto-restart. When
the junction temperature is above the thermal shutdown
threshold (160OC), SC2598 disables VTT, while VREF
remains present. When the junction temperature drops
below the hysteretic window, typically at 140OC, SC2598
will be enabled again.
SC2598 has a built-in current limit feature to prevent
damage to the sink and source FETs. If VTT is shorted to
VDD or ground, SC2598 will sink or source current up to
the current limit threshold.
Input Capacitor
The primary purpose of input capacitance is to provide the
charge to the VTT output capacitor when there is a load
transient at VTT. In the typical application circuit, VDDQ
equals VIN, and VTT equals one-half of VDDQ. As a result,
theory tells us that the input capacitance can be chosen to
be half of the output capacitance.
Ceramic capacitors have a capacitance value that degrades
with temperature, DC and AC bias, and their chemistry.
Usually, ceramic capacitors need to be derated by 50%
when operated at their rated DC voltage. Therefore, it is
recommended to use capacitors with a voltage rating of
6.3V or higher for 3.3V or lower applications.
Stability and VTT Capacitor
Figure 1 shows the small signal model for the sourcing
current loop stability. The low frequency pole is formed by
COUT and RL. Since this pole depends on those variables, it
is recommended to have at least one 10uF ceramic capaci-
tor at COUT for stability. Additional 10uF capacitors can be
added to improve the transient response. SC2598 has an
internal compensation network to ensure the stability as
the load changes.
Figure 2 shows the bode plot with the crossover frequency
at around 0.8MHz and 36 degree phase margin. Another
parameter aecting the loop stability is parasitic induc-
tance in the PCB layout and output capacitor (ESL). The
gain plot shows a peaking around 2.5 MHz after the cross-
over frequency due to the eect of ESL. Minimizing the
ESL reduces this peaking and shifts it to a higher fre-
quency. In addition to following the layout guidelines
below, it is recommended that any VTT capacitor have a
self-resonant frequency (SRF) greater than 1 MHz. This
Applications Information
R
L
VIN
VREF
VTT
gm*V
GS
V
GS
+-
+
-
C
OUT
C
IN
Z
C
Figure 1 — Small Signal Model
SC2598
10
criteria is met by selecting a capacitor with capacitance C
and ESL satisfying the following condition:
The capacitor manufacturer should provide an ESL or SRF
value or an impedance vs frequency curve where the
minimum value occurs at the SRF. In general, a larger
capacitor will have more ESL and therefore higher SRF, so
a ceramic capacitor sized 0805 or smaller is
recommended.
PCB Layout
The SC2598 requires minimal external components to
provide a VTT solution. Figure 3 shows the component
placement and layout for the application circuit on page
6. The SC2598 thermal pad is not electrically connected
internally and does not require to be connected to GND.
For optimal thermal performance, connect to the GND
plane using multiple vias.
PGND on top and bottom layers
C6
C7
C8
R1
C4
C5
Route VTT sense
trace on inner layer
VTT copper pour on top
and bottom layers
VIN copper pour on top
and/or bottom layer
C3
C2
C1
C4,C5 shown located
on bottom side
Thermal pad connecting to the ground plane is
optional, and will improve thermal performance.
Figure 3 — Component Placement and Layout
Figure 2 — Gain and Phase Bode Plot
Fc = 810KHz, PM = 36 degree at 1A Source
Critical Layout Guidelines
Bias and Reference Capacitors:
A 1μF capacitor must be placed as close as possible to the
IC and connected between pin 6 (VDD) and the ground
plane.
A place holder for a 0.1μF capacitor should be placed as
close as possible to the IC and connected between pin 4
(VREF) and the ground plane. This capacitor is optional,
but it is recommended to layout with a capacitor place
holder.
VDDQ Reference Capacitor:
An R-C lter from the supply used for VDDQ consisting of
a 100 Ω resistor and a 0.1μF capacitor should be placed as
close as possible to the IC and connected between pin 5
(VDDQ) and the ground plane, as shown on page 6.
VTT and VIN Capacitors:
Since SC2598 provides both sink and source capabilities,
the loop impedance through the input and VTT capacitors
plays an important role in circuit stability. Figure 4 shows
both sink and source current loops. Close attention to
board layout is needed to reduce ESL in these loops.
SC2598
11
VIN
VTT
GND Q
T
C
VTT
C
VIN
Sourcing Current
Loop
VIN
VTT
GND
Q
B
C
VTT
C
VIN
Sinking Current Loop
Figure 4 — Small AC Signal Current Loops
During a bode plot measurement for the sourcing current
loop, an injected small AC signal ows around the loop
from CIN to QT through CVTT and then returns to CVIN through
the ground plane. Therefore, it is recommended to keep
the CIN and CVTT capacitors as close as possible to reduce
the ESL impedance between them. Similarly in the
sinking current loop, an injected small AC signal flows
from CVTT through QB and then returns to CVTT through the
GND plane. Therefore, it is recommended to keep ESL
small for this loop. Balancing the ESL of those loops gives
the best-case for stability.
SC2598
12
Outline Drawing — SOIC8-EDP
SC2598
13
Land Pattern — SOIC8-EDP
SC2598
14
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Contact Information
Semtech Corporation
Power Mangement Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com