A6986 38 V, 2 A synchronous step-down switching regulator with 30 A quiescent current Datasheet - production data Description HTSSOP16 (RTH = 40 C/W) Features AECQ100 qualification 2 A DC output current 4 V to 38 V operating input voltage Low consumption mode or low noise mode 30 A IQ at light-load (LCM VOUT = 3.3 V) 8 A IQ-SHTDWN Adjustable fSW (250 kHz - 2 MHz) Output voltage adjustable from 0.85 V to VIN Embedded output voltage supervisor Synchronization Adjustable soft-start time Internal current limiting The A6986 device is a step-down monolithic switching regulator able to deliver up to 2 A DC. The output voltage adjustability ranges from 0.85 V to VIN. The 100% duty cycle capability to withstand the cold crank event and the wide input voltage range make the A6986 device ideal for battery powered automotive systems. The "Low Consumption Mode" (LCM) is designed for applications active during car parking, so it maximizes the efficiency at the light-load with the controlled output voltage ripple. The "Low Noise Mode" (LNM) makes the switching frequency constant and minimizes the output voltage ripple overload current range, meeting the low noise application specification like car audio. The output voltage supervisor manages the reset phase for any digital load (C, FPGA). The RST open collector output can also implement output voltage sequencing during the power-up phase. The synchronous rectification, designed for high efficiency at the medium - heavy load, and the high switching frequency capability makes the size of the application compact. Pulse-by-pulse current sensing on both power elements implements effective constant current protection. Overvoltage protection Output voltage sequencing Peak current mode architecture RDSON HS = 180 m, RDSON LS = 150 m Thermal shutdown Applications Designed for automotive systems Battery powered applications Car body applications (LCM) Car audio and low noise applications (LNM) November 2015 This is information on a product in full production. DocID026211 Rev 6 1/67 www.st.com Contents A6986 Contents 1 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Datasheet parameters over the temperature range . . . . . . . . . . . . . . . 13 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 Soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.1 Ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.2 Output voltage sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6 5.7 5.5.1 Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5.2 Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6.1 LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6.2 LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OCP and switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/67 5.8 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.9 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID026211 Rev 6 A6986 6 7 Contents Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.4 Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.5 Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1 Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3 MLF pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.4 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5 Synchronization (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.5.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.5.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8 Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9 Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.1 HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DocID026211 Rev 6 3/67 67 Application schematic 1 A6986 Application schematic Figure 1. Application schematic 9,1 & 9%,$6 3:5*1' *1' 9 Q) 567 & 9 & 9,1 & Q) & Q) 3*1' /; 3*1' /; 5 9287 / 5 $ 0/) & 9&& 66,1+ )% '(/$< &203 )6: 6*1' (3 6<1&+ 5 & 5 *1' 6LJQDO*1' S) 3:5*1' $09 4/67 DocID026211 Rev 6 A6986 Pin settings 2 Pin settings 2.1 Pin connection Figure 2. Pin connection (top view) 2.2 567 9%,$6 9&& 9,1 66,1+ /; 6<1&+ /; )6: 3*1' 0/) 3*1' &203 6*1' '(/$< (;326(' 3$'72 6*1' )% Pin description Table 1. Pin description No. Pin Description 1 RST The RST open collector output is driven low when the output voltage is out of regulation. The RST is released after an adjustable time DELAY once the output voltage is over the active delay threshold. 2 VCC Connect a ceramic capacitor ( 470 nF) to filter internal voltage reference. This pin supplies the embedded analog circuitry. 3 SS/INH An open collector stage can disable the device clamping this pin to GND (INH mode). An internal current generator (2 A typ.) charges the external capacitor to implement the soft-start. 4 SYNCH Master / slave synchronization 5 FSW A pull up resistor (E24 series only) to VCC or pull down to GND selects the switching frequency. Pinstrapping is active only before the soft-start phase to minimize the IC consumption. 6 MLF A pull up resistor (E24 series only) to VCC or pull down to GND selects the low noise mode/low consumption mode and the active RST threshold. Pinstrapping is active only before the soft-start phase to minimize the IC consumption. 7 COMP Output of the error amplifier. The designed compensation network is connected at this pin. 8 DELAY An external capacitor connected at this pin sets the time DELAY to assert the rising edge of the RST o.c. after the output voltage is over the reset threshold. If this pin is left floating, RST is like a power good. 9 FB 10 SGND Signal GND 11 PGND Power GND Inverting input of the error amplifier DocID026211 Rev 6 5/67 67 Pin settings A6986 Table 1. Pin description (continued) No. Pin 12 PGND 13 LX Switching node 14 LX Switching node 15 VIN DC input voltage 16 VBIAS Typically connected to the regulated output voltage. An external voltage reference can be used to supply part of the analog circuitry to increase the efficiency at light-load. Connect to GND if not used. - E. p. Exposed pad must be connected to SGND 2.3 Description Power GND Maximum ratings Stressing the device above the rating listed in Table 2: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 2. Absolute maximum ratings Symbol Description Min. Max. VIN 40 V DELAY -0.3 VCC + 0.3 V PGND SGND - 0.3 SGND + 0.3 V SGND Unit V VCC -0.3 (VIN + 0.3) or (max. 4) V SS / INH -0.3 VIN + 0.3 V -0.3 VCC + 0.3 V -0.3 VCC + 0.3 V FB -0.3 VCC + 0.3 V FSW -0.3 VCC + 0.3 V SYNCH -0.3 VIN + 0.3 V VBIAS -0.3 (VIN + 0.3) or (max. 6) V RST -0.3 VIN + 0.3 V LX -0.3 VIN + 0.3 V -40 150 C MLF COMP See Table 1 TJ Operating temperature range TSTG Storage temperature range -65 to 150 C TLEAD Lead temperature (soldering 10 sec.) 260 C IHS, ILS High-side / low-side switch current 2 A 6/67 DocID026211 Rev 6 A6986 2.4 Pin settings Thermal data Table 3. Thermal data Symbol 2.5 Parameter Value Unit Rth JA Thermal resistance junction ambient (device soldered on the STMicroelectronics(R) demonstration board) 40 C/W Rth JC Thermal resistance junction to exposed pad for board design (not suggested to estimate TJ from power losses) 5 C/W Value Unit HBM 2 KV MM 150 V CDM 500 V ESD protection Table 4. ESD protection Symbol ESD Test condition DocID026211 Rev 6 7/67 67 Electrical characteristics 3 A6986 Electrical characteristics TJ = -40 to 135 C, VIN = 12 V unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter VIN Operating input voltage range VINH VINL IPK IVY ISKIP IVY_SNK Test condition 4 38 VCC UVLO rising threshold 2.7 3.5 VCC UVLO falling threshold 2.5 3.5 Peak current limit Duty cycle < 40% 2.6 Duty cycle = 100% closed loop operation 2.1 Valley current limit Reverse current limit RDSON LS Low-side RDSON 0.8 1 2 ISW = 1 A 0.18 0.36 0 ISW = 1 A 0.30 0.15 0 LNM or VOUT overvoltage Selected switching frequency FSW pinstrapping before SS IFSW FSW biasing current SS ended D TON MIN MLF biasing current A 0.6 fSW Low noise mode / LCM/LNM Low consumption mode selection V 2.7 (1) Skip current limit RDSON HS High-side RDSON IMLF Note Min. Typ. Max. Unit 0.5 see Table 6: fSW selection 0 500 nA see Table 7: LNM / LCM selection on page 12 MLF pinstrapping before SS SS ended 0 (2) Duty cycle 0 Minimum On time 500 nA 100 % 100 ns VCC regulator VCC SWO 8/67 LDO output voltage VBIAS threshold VBIAS = GND (no switchover) 2.9 3.3 3.6 VBIAS = 5 V (switchover) 2.9 3.3 3.6 Switch internal supply from VIN to VBIAS 2.85 3.2 Switch internal supply from VBIAS to VIN 2.8 3.15 DocID026211 Rev 6 V A6986 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Note Min. Typ. Max. Unit Power consumption ISHTDWN Shutdown current from VIN VSS/INH = GND LCM - SWO VREF < VFB < VOVP (SLEEP) VBIAS = 3.3 V IQ OPVIN Quiescent current from VIN IQ OPVBIAS Quiescent current from VBIAS LCM - NO SWO VREF < VFB < VOVP (SLEEP) VBIAS = GND (3) 4 8 15 4 10 15 A A (3) 35 70 120 LNM - SWO VFB = GND (NO SLEEP) VBIAS = 3.3 V 0.5 1.5 5 LNM - NO SWO VFB = GND (NO SLEEP) VBIAS = GND 2 2.8 6 20 50 115 A LNM - SWO VFB = GND (NO SLEEP) VBIAS = 3.3 V 0.5 1.2 5 mA SS rising 200 460 700 LCM - SWO VREF < VFB < VOVP (SLEEP) VBIAS = 3.3 V mA (3) Soft-start VINH VSS threshold VINH HYST VSS hysteresis ISS CH CSS charging current 60 VSS < VINH OR t < TSS SETUP OR VEA+ > VFB t > TSS SETUP AND VEA+ < VFB VSS CLMP SS discharge voltage VSS START VCC < VCCH OR t < TSS SETUPOR thermal fail Start of internal error amplifier ramp SSGAIN SS/INH to internal error amplifier gain VSS END SS/INH voltage at the end of SS phase (2) mV 1 A (2) 4 855 900 945 mV 0.995 1.1 1.15 0 V 3.6 V 3 2.5 DocID026211 Rev 6 9/67 67 Electrical characteristics A6986 Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Note Min. Typ. Max. Unit Error amplifier VFB Voltage feedback IFB FB biasing current Gm Transconductance AV Error amplifier gain ICOMP 0.85 9 V 50 500 nA 90 155 210 70 155 210 0.841 0.85 (4) (2) 100 6 EA output current capability (4) 12 S dB 25 4 A Inner current loop gCS Current sense transconductance (VCOMP to inductor current gain) Ipk = 1 A (5) (5) V PP g CS Slope compensation 2.5 A/V 0.4 0.75 1.0 1.15 1.2 1.25 1 2 6 A Overvoltage protection VOVP Overvoltage trip (VOVP/VREF) VOVP Overvoltage hysteresis HYST % Synchronization (fan out: 6 slave devices typ.) fSYN MIN VSYN TH ISYN VSYN OUT Synchronization frequency LNM; fSW = VCC 266.5 SYNCH input threshold LNM, SYNCH rising 0.70 SYNCH pulldown current LNM, VSYN = 1.2 V high level output LNM, 5 mA sinking load low level output LNM, 0.7 mA sourcing load Selected RST threshold MLF pinstrapping before SS kHz 1.2 0.7 V mA 1.40 0.6 V Reset VTHR (2) VTHR HYST RST hysteresis VRST RST open collector output see Table 7 2 % VIN > VINH AND VFB < VTH 4 mA sinking load 0.4 2 < VIN < VINH 4 mA sinking load 0.8 V Delay VTHD RST open collector released as soon as VDELAY > VTHD VFB > VTHR 1.19 ID CH CDELAY charging current VFB > VTHR 1 10/67 DocID026211 Rev 6 1.23 1.25 4 8 2 3 V A A6986 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Note Min. Typ. Max. Unit Thermal shutdown TSHDWN THYS Thermal shutdown temperature (2) Thermal shutdown hysteresis (2) 165 C 30 1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition. 2. Not tested in production. 3. LCM enables SLEEP mode at light-load. 4. TJ = -40 C. 5. Measured at fSW = 250 kHz. All the population tested at TJ = -40 to 135 C, VIN = 12 V unless otherwise specified. Table 6. fSW selection Symbol fSW RVCC (E24 series) RGND (E24 series) fSW min. fSW typ. fSW max. Note 0 NC 225 250 275 (1) 1.8 k NC 285 3.3 k NC 330 5.6 k NC 380 10 k NC 435 NC 0 18 k NC 575 33 k NC 660 56 k NC 755 NC 1.8 k 870 NC 3.3 k NC 5.6 k 1150 NC 10 k 1310 NC 18 k 1500 NC 33 k 1575 1750 1925 NC 56 k 1800 2000 2200 450 900 500 1000 Unit (2) 550 (1) (2) kHz 1100 (2) (2), (3) (3) 1. Preferred codifications don't require any external resistor. 2. Not tested in production. 3. No synchronization as slave in LNM. DocID026211 Rev 6 11/67 67 Electrical characteristics A6986 All the population tested at TJ = -40 to 135 C, VIN = 12 V unless otherwise specified. . Symbol VRST Table 7. LNM / LCM selection RVCC (E24 series) RGND (E24 series) 0 NC 8.2 k 1% NC 18 k 1% NC 39 k 1% Operating mode VRST/VOUT (tgt value) VRST min. VRST typ. VRST max. Unit 93% 0.779 0.791 0.802 80% 0.670 0.680 0.690 87% 0.728 0.740 0.751 NC 96% 0.804 0.816 0.828 NC 0 93% 0.779 0.791 0.802 NC 8.2 k 1% 80% 0.670 0.680 0.690 NC 18 k 1% 87% 0.728 0.740 0.751 NC 39 k 1% 96% 0.804 0.816 0.828 LCM LNM VRST = 0.791 V typical, LNM and LCM preferred codifications don't require any external resistor. 12/67 DocID026211 Rev 6 V A6986 4 Datasheet parameters over the temperature range Datasheet parameters over the temperature range The 100% of the population in the production flow is tested at three different ambient temperatures (-40 C, +25 C, +135 C) to guarantee the datasheet parameters inside the junction temperature range (-40 C, +135 C). The device operation is guaranteed when the junction temperature is inside the (-40 C, +150 C) temperature range. The designer can estimate the silicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation. However the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the TSHTDWN (+165 C typ.) temperature. All the datasheet parameters can be guaranteed to a maximum junction temperature of +135 C to avoid triggering the thermal shutdown protection during the testing phase because of self-heating. DocID026211 Rev 6 13/67 67 Functional description 5 A6986 Functional description The A6986 device is based on a "peak current mode", constant frequency control. As a consequence, the intersection between the error amplifier output and the sensed inductor current generates the PWM control signal to drive the power switch. The device features LNM (low noise mode) that is forced PWM control, or LCM (low consumption mode) to increase the efficiency at light-load. The main internal blocks shown in the block diagram in Figure 3 are: 14/67 Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the device features low dropout operation A fully integrated sawtooth oscillator with adjustable frequency A transconductance error amplifier The high-side current sense amplifier to sense the inductor current A "Pulse Width Modulator" (PWM) comparator and the driving circuitry of the embedded power elements The soft-start blocks to ramp the error amplifier reference voltage and so decreases the inrush current at power-up. The SS/INH pin inhibits the device when driven low. The switchover capability of the internal regulator to supply a portion of the quiescent current when the VBIAS pin is connected to an external output voltage The synchronization circuitry to manage master / slave operation and the synchronization to an external clock The current limitation circuit to implement the constant current protection, sensing pulse-by-pulse high-side / low-side switch current. In case of heavy short-circuit the current protection is fold back to decrease the stress of the external components A circuit to implement the thermal protection function The OVP circuitry to discharge the output capacitor in case of overvoltage event MLF pin strapping sets the LNM/LCM mode and the thresholds of the RST comparator FSW pinstrapping sets the switching frequency The RST open collector output DocID026211 Rev 6 A6986 Functional description Figure 3. Internal block diagram &203 6<1& )6: 9,1 66,1+ 66,1+ 766 3($. &/ ($ )% 293 32:(5 30266 6(16( 3026 26&,//$ 725 95() /223 /223 &21752/ &21752/ 6/23( *1' '5,9(5 '5,9(5 /; '(/$< /1/& 5677+ 6(16( 9FF 1026 =(52 &5266,1* 32:(5 1026 *1' 567 9$ //(< &/ '(/ $< 0/) *1' $0 5.1 Power supply and voltage reference The internal regulator block consists of a start-up circuit, the voltage pre-regulator that provides current to all the blocks and the bandgap voltage reference. The starter supplies the startup current when the input voltage goes high and the device is enabled (SS/INH pin over the inhibits threshold). The pre-regulator block supplies the bandgap cell and the rest of the circuitry with a regulated voltage that has a very low supply voltage noise sensitivity. Switchover feature The switchover scheme of the pre-regulator block features to derive the main contribution of the supply current for the internal circuitry from an external voltage (3 V < VBIAS < 5.5 V is typically connected to the regulated output voltage). This helps to decrease the equivalent quiescent current seen at VIN. (please refer to Section 5.6: Switchover feature on page 28). 5.2 Voltages monitor An internal block continuously senses the VCC, VBIAS and VBG. If the monitored voltages are good, the regulator starts operating. There is also a hysteresis on the VCC (UVLO). DocID026211 Rev 6 15/67 67 Functional description A6986 Figure 4. Internal circuit 9&& 67$57(5 35(5(*8/$725 95(* %$1'*$3 ,&%,$6 95() ',1 5.3 Soft-start and inhibit The soft-start and inhibit features are multiplexed on the same pin. An internal current source charges the external soft-start capacitor to implement a voltage ramp on the SS/INH pin. The device is inhibited as long as the SS/INH pin voltage is lower than the VINH threshold and the soft-start takes place when SS/INH pin crosses VSS START. (see Figure 5: Soft-start phase). The internal current generator sources 1 A typ. current when the voltage of the VCC pin crosses the UVLO threshold. The current increases to 4 A typ. as soon as the SS/INH voltage is higher than the VINH threshold. This feature helps to decrease the current consumption in inhibit mode. An external open collector can be used to set the inhibit operation clamping the SS/INH voltage below VINH threshold. The startup feature minimizes the inrush current and decreases the stress of the power components during the power-up phase. The ramp implemented on the reference of the error amplifier has a gain three times higher (SSGAIN) than the external ramp present at SS/INH pin. 16/67 DocID026211 Rev 6 A6986 Functional description Figure 5. Soft-start phase The CSS is dimensioned accordingly with Equation 1: Equation 1 I SSCH T SS 4A T SS C SS = SS GAIN -------------------------------- = 3 --------------------------V FB 0.85V where TSS is the soft-start time, ISS CH the charging current and VFB the reference of the error amplifier. The soft-start block supports the precharged output capacitor. DocID026211 Rev 6 17/67 67 Functional description A6986 Figure 6. Soft-start phase with precharged COUT During normal operation a new soft-start cycle takes place in case of: Thermal shutdown event UVLO event The device is driven in INH mode The soft-start capacitor is discharged with a 0.6 mA typ. current capability for 1 msec time max. For complete and proper capacitor discharge in case of fault condition, a maximum CSS = 67 nF value is suggested. The application example in Figure 7 shows how to enable the A6986 and perform the softstart phase driven by an external voltage step, for example the signal from the ignition switch in automotive applications. Figure 7. Enable the device with external voltage step ISS CH Ignition switch RUP 1PA typ in INHIBIT 4PA typ in SS SS/INH UVLO VSTEP 18/67 RDWN DocID026211 Rev 6 CSS Thermal shutdown ISS DISCH = 600PA typ A6986 Functional description The maximum capacitor value has to be limited to guarantee the device can discharge it in case of thermal shutdown and UVLO events (see Figure 9), so restart the switching activity ramping the error amplifier reference voltage. Equation 2 - 1 msec C SS ------------------------------------------------------------------------------------------V SS_FINAL - 0.9 V R SS_EQ ln 1 - ---------------------------------------------- 600 A - R SS_EQ where: Equation 3 R UP R DWN R SS_EQ = --------------------------------R UP + R DWN R DWN V SS_FINAL = V STEP - V DIODE ---------------------------------R UP + R DWN The optional diode prevents to disable the device if the external source drops to ground. RUP value is selected in order to make the capacitor charge at first approximation independent from the internal current generator (4 A typ. current capability, see Table 5 on page 8), so: Equation 4 V STEP - V DIODE - V SS END ----------------------------------------------------------------------- I SS CHARGE 4 A R UP where: Equation 5 V FB V SS END = V SS START + --------------------SS GAIN represents the SS/INH voltage correspondent to the end of the ramp on the error amplifier (see Figure 5); refer to Table 5 for VSS START, VFB and SSGAIN parameters. As a consequence the voltage across the soft-start capacitor can be written as: Equation 6 1 v SS t = V SS_FINAL ----------------------------------------t 1-e - --------------------------------C SS R SS_EQ RSS_DOWN is selected to guarantee the device stays in inhibit mode when the internal generator sources 1 A typ. out of the SS/INH pin and VSTEP is not present: Equation 7 R DWN I SS INHIBIT R DWN 1 A V INH 200 mV so: Equation 8 R DWN 100 k DocID026211 Rev 6 19/67 67 Functional description A6986 RUP and RDWN are selected to guarantee: Equation 9 V SS_FINAL 2 V V SS_END The time to ramp the internal voltage reference can be calculated from Equation 10: Equation 10 V SS_FINAL - V SS START T SS = C SS R SS_EQ ln ----------------------------------------------------------- V SS_FINAL - V SS END that is the equivalent soft-start time to ramp the output voltage. Figure 8 shows the soft-start phase with the following component selection: RUP = 180 k, RDWN = 33 k, CSS = 200 nF, the 1N4148 is a small signal diode and VSTEP = 13 V. Figure 8. External soft-start network VSTEP driven The circuit in Figure 7 introduces a time delay between VSTEP and the switching activity that can be calculated as: Equation 11 V SS_FINAL T SS DELAY = C SS R SS_EQ ln ----------------------------------------------------------- V SS_FINAL - V SS START 20/67 DocID026211 Rev 6 A6986 Functional description Figure 9 shows how the device discharges the soft-start capacitor after an UVLO or thermal shutdown event in order to restart the switching activity ramping the error amplifier reference voltage. Figure 9. External soft-start after UVLO or thermal shutdown DocID026211 Rev 6 21/67 67 Functional description 5.3.1 A6986 Ratiometric startup The ratiometric startup is implemented sharing the same soft-start capacitor for a set of the A6986 device. Figure 10. Ratiometric startup 9 9287 9287 9287 W $0 As a consequence all the internal current generators charge in parallel the external capacitor. The capacitor value is dimensioned accordingly with Equation 12: Equation 12 I SSCH T SS 4A T SS C SS = n A6986 SS GAIN -------------------------------- = n A6986 3 --------------------------0.85V V FB where nA6986 represents the number of devices connected in parallel. For better tracking of the different output voltages the synchronization of the set of regulators is suggested. 22/67 DocID026211 Rev 6 A6986 Functional description Figure 11. Ratiometric startup operation 5.3.2 Output voltage sequencing The A6986 device implements sequencing connecting the RST pin of the master device to the SS/INH of the slave. The slave is inhibited as long as the master output voltage is outside regulation so implementing the sequencing (see Figure 12). DocID026211 Rev 6 23/67 67 Functional description A6986 Figure 12. Output voltage sequencing 9 9287 9287 9287 W W'(/$< W'(/$< W'(/$< $0 High flexibility is achieved thanks to the programmable RST thresholds (see Table 7: LNM / LCM selection on page 12) and programmable delay time. To minimize the component count the DELAY pin capacitor can be also omitted so the pin works as a normal power good. 5.4 Error amplifier The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (0.85 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. Table 8. Uncompensated error amplifier characteristics Description Values Transconductance 155 S Low frequency gain 100 dB The error amplifier output is compared with the inductor current sense information to perform PWM control. The error amplifier also determines the burst operation at light-load when the LCM is active. 5.5 Light-load operation The MLF pinstrapping during the power-up phase determines the light-load operation (refer to Table 7: LNM / LCM selection on page 12). 24/67 DocID026211 Rev 6 A6986 5.5.1 Functional description Low noise mode (LNM) The low noise mode implements a forced PWM operation over the different loading conditions. The LNM features a constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed VIN. The regulator in steady loading condition never skip pulses and it operates in continuous conduction mode (CCM) over the different loading conditions. Figure 13. Low noise mode operation Typical applications for the LNM operation are car audio, sensors. 5.5.2 Low consumption mode (LCM) The low consumption mode maximizes the efficiency at light-load. The regulator prevents the switching activity whenever the switch peak current request is lower than the ISKIP threshold (700 mA typical). As a consequence the A6986 device works in bursts and it minimizes the quiescent current request in the meantime between the switching operation. The LCM operation satisfies the requirements of the unswitched car body applications (KL30). These applications are directly connected to the battery and are operating when the engine is disabled. The typical load when the car is parked is represented by a CAN transceiver and a microcontroller in sleep mode (total load is around 20 - 30 A). As soon as the transceiver recognizes a valid word in the bus, it awakes the C and the rest of the application. The typical input current request of the module when the car is parked is 100 A typ. to prevent the battery discharge over the parking time. In order to minimize the regulator quiescent current request from the input voltage, the VBIAS pin can be connected to an DocID026211 Rev 6 25/67 67 Functional description A6986 external voltage source in the range 3 V < VBIAS < 5.5 V (see Chapter 5.1: Power supply and voltage reference on page 15). In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current drawn from the input voltage can be calculated as Equation 14. Figure 14. LCM operation at zero load Given the energy stored in the inductor during a burst, the voltage ripple depends on the capacitor value: Equation 13 T V OUT RIPPLE 26/67 BURST Q IL 0 iL t dt = -------------- = -------------------------------------------C OUT C OUT DocID026211 Rev 6 A6986 Functional description Figure 15. LCM operation over loading condition (part 1) Figure 16. LCM operation over loading condition (part 2) DocID026211 Rev 6 27/67 67 Functional description A6986 Figure 17. The regulator works in CCM 5.6 Switchover feature The switchover maximizes the efficiency at light-load that is crucial for LCM applications. 5.6.1 LCM The LCM operation satisfies the high efficiency requirements of the battery powered applications. In order to minimize the regulator quiescent current request from the input voltage, the VBIAS pin can be connected to an external voltage source in the range 3 V < VBIAS < 5.5 V (see Section 5.1: Power supply and voltage reference on page 15). In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current drawn from the input voltage can be calculated as: Equation 14 V BIAS 1 I QVIN = I QOPVIN + ----------------- --------------- I QOPVBIAS V IN A6986 where IQ OP VIN, IQ OP VBIAS are defined in Table 5: Electrical characteristics on page 8 and A6986 is the efficiency of the conversion in the working point. 5.6.2 LNM Equation 14 is also valid when the device works in LNM and it can increase the efficiency at medium load since the regulator always operates in continuous conduction mode. 28/67 DocID026211 Rev 6 A6986 5.7 Functional description Overcurrent protection The current protection circuitry features a constant current protection, so the device limits the maximum peak current (see Table 5: Electrical characteristics on page 8) in overcurrent condition. The A6986 device implements a pulse-by-pulse current sensing on both power elements (high-side and low-side switches) for effective current protection over the duty cycle range. The high-side current sensing is called "peak" the low-side sensing "valley". The internal noise generated during the switching activity makes the current sensing circuitry ineffective for a minimum conduction time of the power element. This time is called "masking time" because the information from the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. As a consequence, the peak current protection is disabled for a masking time after the high-side switch is turned on, the valley for a masking time after the low-side switch is turned on. In other words, the peak current protection can be ineffective at extremely low duty cycles, the valley current protection at extremely high duty cycles. The A6986 device assures an effective overcurrent protection sensing the current flowing in both power elements. In case one of the two current sensing circuitry is ineffective because of the masking time, the device is protected sensing the current on the opposite switch. Thus, the combination of the "peak" and "valley" current limits assure the effectiveness of the overcurrent protection even in extreme duty cycle conditions. The valley current threshold is designed higher than the peak to guarantee a proper operation. In case the current diverges because of the high-side masking time, the low-side power element is turned on until the switch current level drops below the valley current sense threshold. The low-side operation is able to prevent the high-side turn on, so the device can skip pulses decreasing the swathing frequency. DocID026211 Rev 6 29/67 67 Functional description A6986 Figure 18. Valley current sense operation in overcurrent condition Figure 18 shows the switching frequency reduction during the valley current sense operation in case of extremely low duty cycle (VIN 38 V, fSW = 500 kHz short-circuit condition). In worst case scenario (like Figure 18) of the overcurrent protection the switch current is limited to: Equation 15 V IN - V OUT I MAX = I VALLEYTH + ------------------------------ T MASKHS L where IVALLEY_TH is the current threshold of the valley sensing circuitry (see Table 5: Electrical characteristics on page 8) and TMASK_HS is the masking time of the high-side switch 100 nsec. typ.). In most of the overcurrent conditions the conduction time of the high-side switch is higher than the masking time and so the peak current protection limits the switch current. Equation 16 IMAX = IPEAK_TH 30/67 DocID026211 Rev 6 A6986 Functional description Figure 19. Peak current sense operation in overcurrent condition The DC current flowing in the load in overcurrent condition is: Equation 17 I RIPPLE V OUT V IN - V OUT I DCOC V OUT = I MAX - ---------------------------------------- = I MAX - ------------------------------ T ON 2 2L OCP and switchover feature Output capacitor discharging the current flowing to ground during heavy short-circuit events is only limited by parasitic elements like the output capacitor ESR and short-circuit impedance. Due to parasitic inductance of the short-circuit impedance, negative output voltage oscillations can be generated with huge discharging current levels (see Figure 20). DocID026211 Rev 6 31/67 67 Functional description A6986 Figure 20. Output voltage oscillations during heavy short-circuit inductor current short-circuit current switching node regulated output voltage Figure 21. Zoomed waveform inductor current short-circuit current switching node regulated output voltage The VBIAS pin absolute maximum ratings (see Table 2: Absolute maximum ratings on page 6) must be satisfied over the different dynamic conditions. If VBIAS is connected to GND there are no issues (see Figure 20 and Figure 21). 32/67 DocID026211 Rev 6 A6986 Functional description A small resistor value (few ohms) in series with VBIAS can help to limit the pin negative voltage (see Figure 22) during heavy short-circuit events if it is connected to the regulated output voltage. Figure 22. VBIAS in heavy short-circuit event inductor current switching node VBIAS pin voltage (cyan) regulated output voltage (purple) 5.8 Overvoltage protection The overvoltage protection monitors the FB pin and enables the low-side MOSFET to discharge the output capacitor if the output voltage is 20% over the nominal value. This is a second level protection and should never be triggered in normal operating conditions if the system is properly dimensioned. In other words, the selection of the external power components and the dynamic performance determined by the compensation network should guarantee an output voltage regulation within the overvoltage threshold even during the worst case scenario in term of load transitions. The protection is reliable and also able to operate even during normal load transitions for a system whose dynamic performance is not in line with the load dynamic request. As a consequence the output voltage regulation would be affected. Figure 23 shows the overvoltage operation during a negative steep load transient for a system designed with huge inductor value and small output capacitor. The inductor value limits the switch current slew rate and the extra charge flowing into the small capacitor value generates an overvoltage event. This can be considered as an example for a system with dynamic performance not in line with the load request. The A6986 device implements a 1 A typ. negative current limitation to limit the maximum reversed switch current during the overvoltage operation. DocID026211 Rev 6 33/67 67 Functional description A6986 Figure 23. Overvoltage operation 5.9 Thermal shutdown The shutdown block disables the switching activity if the junction temperature is higher than a fixed internal threshold (165 C typical). The thermal sensing element is close to the power elements, ensuring fast and accurate temperature detection. A hysteresis of approximately 30 C prevents the device from turning ON and OFF continuously. When the thermal protection runs away a new soft-start cycle will take place. 34/67 DocID026211 Rev 6 A6986 6 Closing the loop Closing the loop Figure 24. Block diagram of the loop 9,1 3:0FRQWURO &XUUHQWVHQVH +6 VZ LWFK /&ILOWHU 5HVLVWRUGLYLGHU / ,+6 J &6 /6 &287 VZ LWFK 5 &RPSHQVDWLRQ QHWZRUN 3:0FRPSDUDWRU &3 5& )% 5/2$' 95() 5 (UURUDPSOLILHU && $0 6.1 GCO(s) control to output transfer function The accurate control to output transfer function for a buck peak current mode converter can be written as: Equation 18 G CO s s 1 + ---- z 1 = R LOAD g cs -------------------------------------------------------------------------------------------------------- ---------------------- F H s R LOAD T SW s ------ 1 + ----------------------------------- m C 1 - D - 0.5 1 + L p where RLOAD represents the load resistance, Ri the equivalent sensing resistor of the current sense circuitry,p the single pole introduced by the the power stage and z the zero given by the ESR of the output capacitor. FH(s) accounts the sampling effect performed by the PWM comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. DocID026211 Rev 6 35/67 67 Closing the loop A6986 Equation 19 1 z = --------------------------------ESR C OUT Equation 20 m c 1 - D - 0.5 1 p = --------------------------------------- + ---------------------------------------------L C OUT f SW R LOAD C OUT where: Equation 21 Se m C = 1 + -----Sn S = V g f PP CS SW e V - V IN OUT S = --------------------------- n L Sn represents the on time slope of the sensed inductor current, Se the on time slope of the external ramp (VPP peak-to-peak amplitude) that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%. Se can be calculated from the parameter VPP gCS given in Table 5 on page 8. The sampling effect contribution FH(s) is: Equation 22 1 F H s = --------------------------------------------2 s s 1 + -------------------- + --------2n Qp n where: Equation 23 1 Q p = ----------------------------------------------------------- m c 1 - D - 0.5 36/67 DocID026211 Rev 6 A6986 6.2 Closing the loop Error amplifier compensation network The typical compensation network required to stabilize the system is shown in Figure 25. Figure 25. Transconductance embedded error amplifier 95() )% ($ &203 5& &3 && 9 5 G9 *P G9 & 5& &3 && 9 $0 RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability but it is useful to reduce the noise at the output of the error amplifier. The transfer function of the error amplifier and its compensation network is: Equation 24 A V0 1 + s R c C c A 0 s = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s R0 C0 + Cp Rc Cc + s R0 Cc + R0 C0 + Cp + Rc Cc + 1 Where Avo = Gm * Ro The poles of this transfer function are (if Cc >> C0 + CP): Equation 25 1 f PLF = ------------------------------------2 R0 Cc DocID026211 Rev 6 37/67 67 Closing the loop A6986 Equation 26 whereas the zero is defined as: 1 f PHF = -------------------------------------------------------2 R0 C0 + Cp Equation 27 1 f Z = ------------------------------------2 Rc Cc 6.3 Voltage divider The contribution of a simple voltage divider is: Equation 28 R2 G DIV s = -------------------R1 + R2 A small signal capacitor in parallel to the upper resistor (see Figure 26) of the voltage divider implements a leading network (fzero < fpole), sometimes necessary to improve the system phase margin: Figure 26. Leading network example 9,1 9,1 567 9%,$6 *1' 3:5JQG 3*1' /; 3*1' /; 0/) 9287 &U $ 5 9&& 66,1+ )% '(/$< &203 )6: 6*1' (3 6<1&+ 5F &S &F 5 3:5JQG *1' VLJQDO*1' $09 Laplace transformer of the leading network: Equation 29 1 + s + R 1 C R1 R2 G DIV s = -------------------- ------------------------------------------------------------R1 + R2 R1 R2 1 + s -------------------- C R1 R1 + R2 38/67 DocID026211 Rev 6 A6986 Closing the loop where: Equation 30 1 f Z = ----------------------------------------2 R 1 C R1 1 f p = ------------------------------------------------------R1 R2 2 -------------------- C R1 R1 + R2 fZ fp 6.4 Total loop gain In summary, the open loop gain can be expressed as: Equation 31 G s = G DIV s G CO s A 0 s Example 1 VIN = 12 V, VOUT = 3.3 V, ROUT = 2.2 Selecting L = 6.8 H, COUT = 15 F and ESR = 1 m, RC= 68 k, CC= 180 pF, CP = 6.8 pF (please refer to Example 2), the gain and phase bode diagrams are plotted respectively in Figure 27 and Figure 28. DocID026211 Rev 6 39/67 67 Closing the loop A6986 Figure 27. Module plot 0RGXOH>G%@ (;7(51$//22302'8/( [ [ [ [ [ )UHTXHQF\>+]@ $0 Equation 32 BW = 67kHz phase margin = 53 40/67 DocID026211 Rev 6 0 A6986 Closing the loop Figure 28. Phase plot (;7(51$//223*$,13+$6( [ [ [ [ [ $0 The blue solid trace represents the transfer function including the sampling effect term (see Equation 22 on page 36), the dotted blue trace neglects the contribution. 6.5 Compensation network design The maximum bandwidth of the system can be designed up to fSW/6 to guarantee a valid small signal model. Equation 33 f SW BW = --------6 Equation 34 2 BW C OUT V OUT R C = ---------------------------------------------------------------0.85V g CS g m TYP where: Equation 35 p f POLE = ----------2 DocID026211 Rev 6 41/67 67 Closing the loop A6986 p is defined by Equation 20 on page 36, gCS represents the current sense transconductance (see Table 5: Electrical characteristics on page 8) and gm TYP the error amplifier transconductance. Equation 36 5 C C = -------------------------------------2 R C BW Example 2 Considering VIN = 12 V, VOUT = 3.3 V, L = 6.8 H, COUT = 15 F, fSW = 500 kHz. The maximum system bandwidth is 80 kHz. Assuming to design the compensation network to achieve a system bandwidth of 70 kHz: Equation 37 f POLE = 6kHz Equation 38 V OUT R LOAD = -------------- = 2.2 I OUT so accordingly with Equation 34 and Equation 36: Equation 39 R C = 68k Equation 40 C C = 168pF 180pF 42/67 DocID026211 Rev 6 A6986 Application notes 7 Application notes 7.1 Output voltage adjustment The error amplifier reference voltage is 0.85 V typical. The output voltage is adjusted accordingly with Equation 41 (see Figure 29): Equation 41 R1 V OUT = 0.85 1 + ------- R2 Cr1 capacitor is sometimes useful to increase the small signal phase margin (please refer to Section 6.5: Compensation network design). Figure 29. A6986 application circuit 9,1 9,1 567 9%,$6 *1' 3:5JQG 3*1' /; 3*1' /; 0/) 9287 &U $ 5 9&& 66,1+ )% '(/$< &203 )6: 6*1' (3 6<1&+ 5F &S &F 5 *1' VLJQDO*1' 3:5JQG $09 7.2 Switching frequency A resistor connected to the FSW pin features the selection of the switching frequency. The pinstrapping is performed at power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven floating in order to minimize the quiescent current from VIN. Please refer toTable 6: fSW selection on page 11 to identify the pull-up / pull-down resistor value. fSW = 250 kHz / fSW = 500 kHz preferred codifications don't require any external resistor. 7.3 MLF pin A resistor connected to the MLF pin features the selection of the between low noise mode / low consumption mode and the different RST thresholds. The pinstrapping is performed at power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven floating in order to minimize the quiescent current from VIN. DocID026211 Rev 6 43/67 67 Application notes A6986 Please refer to Table 7: LNM / LCM selection on page 12 to identify the pull-up / pull-down resistor value. (LNM, RST threshold 93%) / (LCM, RST threshold 93%) preferred codifications don't require any external resistor. 7.4 Voltage supervisor The embedded voltage supervisor (composed of the RST and the DELAY pins) monitors the regulated output voltage and keeps the RST open collector output in low impedance as long as the VOUT is out of regulation. In order to ensure a proper reset of digital devices with a valid power supply, the device can delay the RST assertion with a programmable time. Figure 30. Voltage supervisor operation The comparator monitoring the FB voltage has four different programmable thresholds (80%, 87%, 93%, 96% nominal output voltage) for high flexibility (see Section 7.3: MLF pin and Table 7: LNM / LCM selection on page 12). When the RST comparator detects the output voltage is in regulation, a 2 A internal current source starts to charge an external capacitor to implement a voltage ramp on the DELAY pin. The RST open collector is then released as soon as VDELAY = 1.234 V (see Figure 30). The CDELAY is dimensioned accordingly with Equation 42: Equation 42 I SSCH T DELAY 2A T DELAY C DELAY = ------------------------------------------ = ------------------------------------V DELAY 1.234V The maximum suggested capacitor value is 270 nF. 44/67 DocID026211 Rev 6 A6986 Synchronization (LNM) Beating frequency noise is an issue when multiple switching regulators populate the same application board. The A6986 synchronization circuitry features the same switching frequency for a set of regulators simply connecting their SYNCH pin together, so preventing beating noise. The master device provides the synchronization signal to the others since the SYNCH pin is I/O able to deliver or recognize a frequency signal. For proper synchronization of multiple regulators, all of them have to be configured with the same switching frequency (see Table 6 on page 11), so the same resistor connected at the FSW pin. In order to minimize the RMS current flowing through the input filter, the A6986 device provides a phase shift of 180 between the master and the SLAVES. If more than two devices are synchronized, all slaves will have a common 180 phase shift with respect to the master. Considering two synchronized A6986 which regulates the same output voltage (i.e.: operating with the same duty cycle), the input filter RMS current is optimized and is calculated as: Equation 43 I RMS I OUT ----------- 2D 1 - 2D 2 = I OUT - 2D - 1 2 - 2D ---------- 2 if D < 0.5 if D > 0.5 The graphical representation of the input RMS current of the input filter in the case of two devices with 0 phase shift (synchronized to an external signal) or 180 phase shift (synchronized connecting their SYNCH pins) regulating the same output voltage is provided in Figure 31. To dimension the proper input capacitor please refer to Chapter 7.5.1: Input capacitor selection. Figure 31. Input RMS current 506FXUUHQWQRUPDOL]HG ,UPV,287 7.5 Application notes WZR UHJXODWRUV RSHUDWLQJ LQ SKDVH WZR UHJXODWRUV RSHUDWLQJ RXW RI SKDVH DocID026211 Rev 6 45/67 67 Application notes A6986 Figure 32 shows two regulators not synchronized. Figure 32. Two regulators not synchronized Figure 33 shows the same regulators working synchronized. The MASTER regulator (LX2 trace) delivers the synchronization signal (SYNCH1, SYNCH2 pins are connected together) to the SLAVE device (LX1). The SLAVE regulator works in phase with the synchronization signal which is out of phase with the MASTER switching operation. Figure 33. Two regulators synchronized 46/67 DocID026211 Rev 6 A6986 Application notes Multiple A6986 can be synchronized to an external frequency signal fed to the SYNCH pin. In this case the regulator set is phased to the reference and all the devices will work with 0 phase shift. The frequency range of the synchronization signal is 275 kHz - 1.4 MHz and the minimum pulse width is 100 nsec (see Figure 34). Figure 34. Synchronization pulse definition L)[ G4:/$)30 .)[ G4:/$)30 G4:/$)30 OTFD NJO OTFD NJO ". Since the slope compensation contribution that is required to prevent subharmonic oscillations in peak current mode architecture depends on the switching frequency, it is important to select the same oscillator frequency for all regulators (all of them operate as SLAVE) as close as possible to the frequency of the reference signal (please refer to Table 6: fSW selection on page 11). As a consequence all the regulators have the same resistor value connected to the FSW pin, so the slope compensation is optimized accordingly with the frequency of the synchronization signal. The slope compensation contribution is latched at power-up and so fixed during the device operation. The A6986 normally operates in MASTER mode, driving the SYNCH line at the selected oscillator frequency as shown in Figure 35 and Figure 32. In SLAVE mode the A6986 sets the internal oscillator at 250 kHz typ. (see Table 6 on page 11 - first row) and drives the line accordingly. Figure 35. A6986 synchronization driving capability VCC INT 5 mA fOSC 150nsec typ. HIGH LEVEL LOW LEVEL 0.7 mA In order to safely guarantee that each regulator recognizes itself in SLAVE mode during the normal operation, the external master must drive the SYNCH pin with a clock signal DocID026211 Rev 6 47/67 67 Application notes A6986 frequency higher than the maximum oscillator spread (refer to Table 6 on page 11) for at least 10 internal clock cycles. For example: selecting RFSW = 0 to GND Table 9. Example of oscillator frequency selection from Table 6 Symbol RVCC (E24 series) RGND (E24 series) fSW min. fSW typ. fSW max. fSW NC 0 450 500 550 the device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it is able to synchronize to a clock signal in the range 275 kHz - 1.4 MHz (see Figure 34). Anyway it is suggested to limit the frequency range within 20% FSW resistor nominal frequency (see details in text below). If not spread spectrum is required, all the regulators synchronize to a frequency higher to the maximum oscillator spread (550 kHz in the example). The device keeps operating in slave mode as far as the master is able to drive the SYNCH pin faster than 275 kHz (maximum oscillator spread for 250 kHz oscillator), otherwise it goes back into MASTER mode at the nominal oscillator frequency after successfully driving one pulse at 250 kHz (see Figure 36) in the SYNCH line. Figure 36. Slave to master mode transition switching node SLAVE mode 250kHz typ. stand alone operation at nominal fsw SYNCH signal The external master can force a latched SLAVE mode driving the SYNCH pin low at powerup, before the soft-start starts the switching activity. So the oscillator frequency is 250 kHz typ. fixed until a new UVLO event is triggered regardless FSW resistor value, that otherwise counts to design the slope compensation. The same considerations above are also valid. 48/67 DocID026211 Rev 6 A6986 Application notes The master driving capability must be able to provide the proper signal levels at the SYNCH pin (see Table 5 on page 8 - Synchronization section): Low level < VSYN THL= 0.7 V sinking 5 mA High level > VSYN THH = 1.2 V sourcing 0.7 mA Figure 37. Master driving capability to synchronize the A6986 VCCM 5 mA VSYN_TH_H 0.7 mA VSYN_TH_L RH RL As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the slope compensation is dimensioned accordingly with FSW resistors so, even if the A6986 supports synchronization over the 275 kHz - 1.4 MHz frequency range, it is important to limit the switching operation around a working point close to the selected frequency (FSW resistor). As a consequence, to guarantee the full output current capability and to prevent the subharmonic oscillations the master must limit the driving frequency range within 20% of the selected frequency. A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the peak current capability (see IPK parameter in Table 5) since the internal slope compensation signal may be saturated. In order to guarantee the synchronization as a slave over distribution, temperature and the output load, the external clock frequency must be lower than 1.4 MHz. 7.5.1 Input capacitor selection The input capacitor voltage rating must be higher than the maximum input operating voltage of the application. During the switching activity a pulsed current flows into the input capacitor and so its RMS current capability must be selected accordingly with the application conditions. Internal losses of the input filter depends on the ESR value so usually low ESR capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher conversion efficiency. DocID026211 Rev 6 49/67 67 Application notes A6986 The maximum RMS input current flowing through the capacitor can be calculated as: Equation 44 D D I RMS = I OUT 1 - ---- --- Where IOUT is the maximum DC output current, D is the duty cycles, is the efficiency. This function has a maximum at D = 0.5 and, considering = 1, it is equal to Io/2. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 45 V OUT + V LOWSIDE D MAX = -----------------------------------------------------------------------------------------------V INMIN + V LOWSIDE - V HIGHSIDE Equation 46 V OUT + V LOWSIDE D MIN = -------------------------------------------------------------------------------------------------V INMAX + V LOWSIDE - V HIGHSIDE Where VHIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches. The peak to peak voltage across the input filter can be calculated as: Equation 47 I OUT D D V PP = ------------------------- 1 - ---- ---- + ESR I OUT + I L C IN f SW In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target VPP can be written as follows: Equation 48 I OUT D D C IN = -------------------------- 1 - ---- ---V PP f SW Considering this function has its maximum in D = 0.5: Equation 49 I OUT C INMIN = ---------------------------------------------4 V PPMAX f SW Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 5% VIN_MAX. 50/67 DocID026211 Rev 6 A6986 Application notes Table 10. Input capacitors Manufacturer TDK Taiyo Yuden 7.5.2 Series Size Cap value (F) Rated voltage (V) C3225X7S1H106M 1210 10 50 C3216X5R1H106M 1206 UMK325BJ106MM-T 1210 Inductor selection The inductor current ripple flowing into the output capacitor determines the output voltage ripple (please refer to Section 7.5.3). Usually the inductor value is selected in order to keep the current ripple lower than 20% - 40% of the output current over the input voltage range. The inductance value can be calculated by Equation 50: Equation 50 V IN - V OUT V OUT I L = ------------------------------ T ON = -------------- T OFF L L Where TON and TOFF are the on and off time of the internal power switch. The maximum current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle (see Section 7.5.1: Input capacitor selection to calculate minimum duty). So fixing IL = 20% to 40% of the maximum output current, the minimum inductance value can be calculated: Equation 51 V OUT 1 - D MIN L MIN = ------------------- ----------------------F SW I LMAX where fSW is the switching frequency 1/(TON + TOFF). For example for VOUT = 3.3 V, VIN = 12 V, IO = 2 A and FSW = 500 kHz the minimum inductance value to have IL = 30% of IO is about 8.2 H. The peak current through the inductor is given by: Equation 52 I L I L PK = I OUT + -------2 So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. The higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit. In Table 11 some inductor part numbers are listed. Table 11. Inductors Manufacturer Series Inductor value (H) Saturation current (A) Coilcraft XAL50xx 2.2 to 22 6.5 to 2.7 XAL60xx 2.2 to 22 12.5 to 4 DocID026211 Rev 6 51/67 67 Application notes 7.5.3 A6986 Output capacitor selection The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output voltage ripple, that depends on the capacitor value and the equivalent resistive component (ESR). As a consequence the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. The voltage ripple equation can be calculated as: Equation 53 I LMAX V OUT = ESR I LMAX + --------------------------------------8 C OUT f SW Usually the resistive component of the ripple can be neglected if the selected output capacitor is a multi layer ceramic capacitor (MLCC). The output capacitor is important also for loop stability: it determines the main pole and the zero due to its ESR. (see Section 6: Closing the loop on page 35 to consider its effect in the system stability). For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.6 A, fSW = 500 kHz (resulting by the inductor value) and COUT = 10 F MLCC: Equation 54 V OUT I LMAX 1 1 0 6 15mV ------------------ -------------- ------------------------------ = ------ -------------------------------------------------- = ---------------- = 0.45% 33 8 10F 500kHz V OUT V OUT C OUT f SW 3.3 The output capacitor value has a key role to sustain the output voltage during a steep load transient. When the load transient slew rate exceeds the system bandwidth, the output capacitor provides the current to the load. In case the final application specifies high slew rate load transient, the system bandwidth must be maximized and the output capacitor has to sustain the output voltage for time response shorter than the loop response time. In Table 12 some capacitor series are listed. Table 12. Output capacitors Manufacturer Series Cap value (F) Rated voltage (V) ESR (m) GRM32 22 to 100 6.3 to 25 <5 GRM31 10 to 47 6.3 to 25 <5 ECJ 10 to 22 6.3 <5 EEFCD 10 to 68 6.3 15 to 55 SANYO TPA/B/C 100 to 470 4 to 16 40 to 80 TDK C3225 22 to 100 6.3 <5 MURATA PANASONIC 52/67 DocID026211 Rev 6 A6986 Application board 8 Application board The reference evaluation board schematic is shown in Figure 38. Figure 38. Evaluation board schematic 5 10 73 73 6<1&+ 9,1B)/7 9 9 5 10 5 X) 10 X) & & & & & 10 Q) 9 5 10 5 6<1&+ / /; /; )6: 66,1+ '(/$< Q) Q) 9287 X+ &203 6*1' & )% & 73 - 0/) & 0 - 9%,$6 9&& 5 567 9,1 (3 - 567 A6986 / 8 5 & 3*1' 3*1' N & S 5 N S VLJQDO*1' 10 5 N 10 & 5 X) 9 5 & 73 66,1+ 73 SRZHU*1' 3*1' *1' / 73 / 73 X+ 9,1B)/7 9,1 10 VL]H X) X) & 73 & 10 & 9,1B(0, 3*1' *1' $0 The additional input filter (C16, L3, C15, L2, C14) limits the conducted emission on the power supply. Table 13. Bill of material Reference Part number Description Manufacturer C1 CGA5L3X5R1H106K 10 F - 1206 - 50 V - X7R - 10% TDK C2 C2012X7S2A105K 1 F - 0805 - 50 V - X7S - 10% TDK C3 470 nF - 50 V - 0603 C4 2.2 pF - 50 V - 0603 C5 68 nF - 50 V - 0603 C6 10 nF - 50 V - 0603 C8 120 pF - 50 V - 0603 C1 CGA5L3X5R1H106K 10 F - 1206 - 50 V - X7R - 10% TDK C9 C3216X5R1C476M 47 F - 1206 - 16 V - X5R - 20% TDK C14, C15, C16 C3216X7R1H475K160AC 4.7 F - 1206 - 50 V - X7R - 10% TDK C7, C10, C11, C13 Not mounted R1, R4 0 R - 0603 DocID026211 Rev 6 53/67 67 Application board A6986 Table 13. Bill of material (continued) Reference Part number Description R6 1 M - 1%- 0603 R7 180 k - 1% - 0603 R8 130 k - 1% - 0603 R9 62 k - 1% - 0603 R11 10 - 1% - 0603 R2, R3, R5, R10 Not mounted Manufacturer L1 XAL5050-103MEC 10 H Coilcraft L2 XAL5030-472MEC 4.7 H Coilcraft L3 MPZ2012S221A EMC bead TDK J1 Open J2 Open J3 Closed J4 Open U1 A6986 Switchover STM Figure 39 and Figure 40 show the magnitude and phase margin Bode's plots related to the evaluation board presented in Figure 38. The small signal dynamic performance of the demonstration board is: Equation 55 BW = 67kHz phase margin = 53 54/67 DocID026211 Rev 6 0 A6986 Application board Figure 39. Magnitude Bode's plot 0RGXOH>G%@ (;7(51$//22302'8/( [ [ [ [ [ )UHTXHQF\>+]@ $0 Figure 40. Phase margin Bode's plot (;7(51$//223*$,13+$6( 3KDVH X [ [ [ [ )UHTXHQF\>+]@ $0 DocID026211 Rev 6 55/67 67 Application board A6986 Figure 41. Top layer Figure 42. Bottom layer 56/67 DocID026211 Rev 6 A6986 9 Efficiency curves Efficiency curves Figure 43. Efficiency curves over fsw: VIN = 13.5 V - VOUT = 3.3 V 90 85 80 75 70 65 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VIN=13.5V VOUT=3.3V A6986 500kHz VBIAS PSKIP VIN=13.5V VOUT=3.3VA6986 500kHz NOVBIAS PSKIP VIN=13.5V VOUT=3.3V A6986 500kHz NOVBIAS NOPSKIP VIN=13.5V VOUT=3.3V A6986 500kHz VBIAS NOPSKIP VIN=13.5V VOUT=3.3V 1MHz VBIAS PSKIP VIN=13.5V VOUT=3.3V 1MHz NOVBIAS PSKIP VIN=13.5V VOUT=3.3V 1MHz NOVBIAS NOPSKIP VIN=13.5V VOUT=3.3V 1MHz VBIAS NOPSKIP VIN=13.5V VOUT=3.3V 2MHz VBIAS NOSPKIP VIN=13.5V VOUT=3.3V 2MHz NOVBIAS NOSPKIP VIN=13.5V VOUT=3.3V 2MHz NOVBIAS SPKIP VIN=13.5V VOUT=3.3V 2MHz VBIAS SPKIP 2 Figure 44. Efficiency curves over fsw: VIN = 13.5 V - VOUT = 3.3 V (log scale) 90 85 80 75 70 65 60 0.0015 0.015 0.15 VIN=13.5V VOUT=3.3V A6986 500kHz VBIAS PSKIP VIN=13.5V VOUT=3.3VA6986 500kHz NOVBIAS PSKIP VIN=13.5V VOUT=3.3V A6986 500kHz NOVBIAS NOPSKIP VIN=13.5V VOUT=3.3V A6986 500kHz VBIAS NOPSKIP VIN=13.5V VOUT=3.3V 1MHz VBIAS PSKIP VIN=13.5V VOUT=3.3V 1MHz NOVBIAS PSKIP VIN=13.5V VOUT=3.3V 1MHz NOVBIAS NOPSKIP VIN=13.5V VOUT=3.3V 1MHz VBIAS NOPSKIP VIN=13.5V VOUT=3.3V 2MHz VBIAS NOSPKIP VIN=13.5V VOUT=3.3V 2MHz NOVBIAS NOSPKIP VIN=13.5V VOUT=3.3V 2MHz NOVBIAS SPKIP VIN=13.5V VOUT=3.3V 2MHz VBIAS SPKIP DocID026211 Rev 6 57/67 67 Efficiency curves A6986 Figure 45. Efficiency curves over fsw: VIN = 13.5 V - VOUT = 5 V 95 90 85 80 75 70 65 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VIN=13.5V VOUT=5V A6986 500kHz VBIAS NOPSKIP VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS NOPSKIP VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS PSKIP VIN=13.5V VOUT=5V A6986 500kHz VBIAS PSKIP VIN=13.5V VOUT=5V 1MHz VBIAS NOSPKIP VIN=13.5V VOUT=5V 1MHz NOVBIAS NOSPKIP VIN=13.5V VOUT=5V 1MHz NOVBIAS SPKIP VIN=13.5V VOUT=5V 1MHz VBIAS SPKIP VIN=13.5V VOUT=5V 2MHz VBIAS SPKIP VIN=13.5V VOUT=5V 2MHz NOVBIAS SPKIP VIN=13.5V VOUT=5V 2MHz NOVBIAS NOSPKIP VIN=13.5V VOUT=5V 2MHz VBIAS NOSPKIP Figure 46. Efficiency curves over fsw: VIN = 13.5 V - VOUT = 5 V (log scale) 95 90 85 80 75 70 65 60 0.0015 58/67 0.015 0.15 VIN=13.5V VOUT=5V A6986 500kHz VBIAS NOPSKIP VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS NOPSKIP VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS PSKIP VIN=13.5V VOUT=5V A6986 500kHz VBIAS PSKIP VIN=13.5V VOUT=5V 1MHz VBIAS NOSPKIP VIN=13.5V VOUT=5V 1MHz NOVBIAS NOSPKIP VIN=13.5V VOUT=5V 1MHz NOVBIAS SPKIP VIN=13.5V VOUT=5V 1MHz VBIAS SPKIP VIN=13.5V VOUT=5V 2MHz VBIAS SPKIP VIN=13.5V VOUT=5V 2MHz NOVBIAS SPKIP VIN=13.5V VOUT=5V 2MHz NOVBIAS NOSPKIP VIN=13.5V VOUT=5V 2MHz VBIAS NOSPKIP DocID026211 Rev 6 2 A6986 Efficiency curves Figure 47. Efficiency curves over fsw: VIN = 24 V - VOUT = 3.3 V 85 80 75 70 65 60 55 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VIN=24V VOUT=3.3V A6986 500kHz VBIAS PSKIP VIN=24V VOUT=3.3V A6986 500kHz NOVBIAS PSKIP VIN=24V VOUT=3.3V A6986 500kHz NOVBIAS NOPSKIP VIN=24V VOUT=3.3V A6986 500kHz VBIAS NOPSKIP VIN=24V VOUT=3.3V 1MHz VBIAS PSKIP VIN=24V VOUT=3.3V 1MHz NOVBIAS PSKIP VIN=24V VOUT=3.3V 1MHz NOVBIAS NOPSKIP VIN=24V VOUT=3.3V 1MHz VBIAS NOPSKIP VIN=24V VOUT=3.3V 2MHz VBIAS NOSPKIP VIN=24V VOUT=3.3V 2MHz NOVBIAS NOSPKIP VIN=24V VOUT=3.3V 2MHz NOVBIAS SPKIP VIN=24V VOUT=3.3V 2MHz VBIAS SPKIP 2 Figure 48. Efficiency curves over fsw: VIN = 24 V - VOUT = 3.3 V (log scale) 85 80 75 70 65 60 55 50 0.0025 0.025 0.25 VIN=24V VOUT=3.3V A6986 500kHz VBIAS PSKIP VIN=24V VOUT=3.3V A6986 500kHz NOVBIAS PSKIP VIN=24V VOUT=3.3V A6986 500kHz NOVBIAS NOPSKIP VIN=24V VOUT=3.3V A6986 500kHz VBIAS NOPSKIP VIN=24V VOUT=3.3V 1MHz VBIAS PSKIP VIN=24V VOUT=3.3V 1MHz NOVBIAS PSKIP VIN=24V VOUT=3.3V 1MHz NOVBIAS NOPSKIP VIN=24V VOUT=3.3V 1MHz VBIAS NOPSKIP VIN=24V VOUT=3.3V 2MHz VBIAS NOSPKIP VIN=24V VOUT=3.3V 2MHz NOVBIAS NOSPKIP VIN=24V VOUT=3.3V 2MHz NOVBIAS SPKIP VIN=24V VOUT=3.3V 2MHz VBIAS SPKIP DocID026211 Rev 6 59/67 67 Efficiency curves A6986 Figure 49. Efficiency curves over fsw: VIN = 24 V - VOUT = 5 V 90 85 80 75 70 65 60 55 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VIN=24V VOUT=5V A6986 500kHz VBIAS NOPSKIP VIN=24V VOUT=5V A6986 500kHz NOVBIAS NOPSKIP VIN=24V VOUT=5V A6986 500kHz NOVBIAS PSKIP VIN=24V VOUT=5V A6986 500kHz VBIAS PSKIP VIN=24V VOUT=5V 1MHz VBIAS NOSPKIP VIN=24V VOUT=5V 1MHz NOVBIAS NOSPKIP VIN=24V VOUT=5V 1MHz NOVBIAS SPKIP VIN=24V VOUT=5V 1MHz VBIAS SPKIP VIN=24V VOUT=5V 2MHz VBIAS SPKIP VIN=24V VOUT=5V 2MHz NOVBIAS SPKIP VIN=24V VOUT=5V 2MHz NOVBIAS NOSPKIP VIN=24V VOUT=5V 2MHz VBIAS NOSPKIP Figure 50. Efficiency curves over fsw: VIN = 24 V - VOUT = 5 V (log scale) 90 85 80 75 70 65 60 55 50 0.0025 60/67 0.025 0.25 VIN=24V VOUT=5V A6986 500kHz VBIAS NOPSKIP VIN=24V VOUT=5V A6986 500kHz NOVBIAS NOPSKIP VIN=24V VOUT=5V A6986 500kHz NOVBIAS PSKIP VIN=24V VOUT=5V A6986 500kHz VBIAS PSKIP VIN=24V VOUT=5V 1MHz VBIAS NOSPKIP VIN=24V VOUT=5V 1MHz NOVBIAS NOSPKIP VIN=24V VOUT=5V 1MHz NOVBIAS SPKIP VIN=24V VOUT=5V 1MHz VBIAS SPKIP VIN=24V VOUT=5V 2MHz VBIAS SPKIP VIN=24V VOUT=5V 2MHz NOVBIAS SPKIP VIN=24V VOUT=5V 2MHz NOVBIAS NOSPKIP VIN=24V VOUT=5V 2MHz VBIAS NOSPKIP DocID026211 Rev 6 2 A6986 Efficiency curves Figure 51. Efficiency curves: fsw = 500kHz - VIN = 24 V - VOUT = 3.3 V 95 90 85 80 75 VIN=13.5V VOUT=3.3V A6986 500kHz VBIAS PSKIP VIN=13.5V VOUT=3.3V A6986 500kHz NOVBIAS PSKIP 70 VIN=13.5V VOUT=3.3V A6986 500kHz NOVBIAS NOPSKIP 65 VIN=13.5V VOUT=3.3V A6986 500kHz VBIAS NOPSKIP 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Figure 52. Efficiency curves: fsw = 500 kHz - VIN = 13.5 V - VOUT = 3.3 V (log scale) 90 80 70 60 VIN=13.5V VOUT=3.3V A6986 500kHz VBIAS PSKIP VIN=13.5V VOUT=3.3V A6986 500kHz NOVBIAS PSKIP 50 VIN=13.5V VOUT=3.3V A6986 500kHz NOVBIAS NOPSKIP VIN=13.5V VOUT=3.3V A6986 500kHz VBIAS NOPSKIP 40 30 0.001 0.01 0.1 Figure 53. Efficiency curves: fsw = 500 kHz - VIN = 13.5 V - VOUT = 5 V 95 90 85 80 75 70 VIN=13.5V VOUT=5V A6986 500kHz VBIAS NOPSKIP 65 VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS NOPSKIP VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS PSKIP 60 VIN=13.5V VOUT=5V A6986 500kHz VBIAS PSKIP 55 0 0.2 0.4 0.6 0.8 DocID026211 Rev 6 1 1.2 1.4 1.6 61/67 67 Efficiency curves A6986 Figure 54. Efficiency curves: fsw = 500 kHz - VIN = 13.5 V - VOUT = 5 V (log scale) 90 80 70 60 VIN=13.5V VOUT=5V A6986 500kHz VBIAS NOPSKIP 50 VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS NOPSKIP VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS PSKIP 40 VIN=13.5V VOUT=5V A6986 500kHz VBIAS PSKIP 30 20 0.001 0.01 0.1 Figure 55. Efficiency curves: fsw = 500 kHz - VIN = 24 V - VOUT = 3.3 V 90 85 80 75 70 VIN=24V VOUT=3.3V A6986 500kHz VBIAS PSKIP 65 VIN=24V VOUT=3.3V A6986 500kHz NOVBIAS PSKIP 60 VIN=24V VOUT=3.3V A6986 500kHz NOVBIAS NOPSKIP 55 VIN=24V VOUT=3.3V A6986 500kHz VBIAS NOPSKIP 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Figure 56. Efficiency curves: fsw = 500 kHz - VIN = 24 V - VOUT = 3.3 V (log scale) 80 70 60 50 VIN=24V VOUT=3.3V A6986 500kHz VBIAS PSKIP 40 30 20 0.001 62/67 VIN=24V VOUT=3.3V A6986 500kHz NOVBIAS PSKIP VIN=24V VOUT=3.3V A6986 500kHz NOVBIAS NOPSKIP VIN=24V VOUT=3.3V A6986 500kHz VBIAS NOPSKIP 0.01 DocID026211 Rev 6 0.1 2 A6986 Efficiency curves Figure 57. Efficiency curves: fsw = 500 kHz - VIN = 24 V - VOUT = 5 V (log scale) 90 85 80 75 70 65 60 VIN=24V VOUT=5V A6986 500kHz VBIAS NOPSKIP 55 VIN=24V VOUT=5V A6986 500kHz NOVBIAS NOPSKIP VIN=24V VOUT=5V A6986 500kHz NOVBIAS PSKIP 50 VIN=24V VOUT=5V A6986 500kHz VBIAS PSKIP 45 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Figure 58. Efficiency curves: fsw = 500 kHz - VIN = 24 V - VOUT = 5 V (log scale) 90 80 70 60 50 40 VIN=13.5V VOUT=5V A6986 500kHz VBIAS NOPSKIP VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS NOPSKIP VIN=13.5V VOUT=5V A6986 500kHz NOVBIAS PSKIP VIN=13.5V VOUT=5V A6986 500kHz VBIAS PSKIP 30 20 0.001 0.01 0.1 DocID026211 Rev 6 63/67 67 Package information 10 A6986 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10.1 HTSSOP16 package information Figure 59. HTSSOP16 package outline 64/67 DocID026211 Rev 6 A6986 Package information . Table 14. HTSSOP16 package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A 1.20 A1 0.15 A2 0.80 b 0.19 0.30 c 0.09 0.20 D 4.90 5.00 5.10 D1 2.8 3 3.2 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 E2 2.8 3 3.2 e L 1.05 0.65 0.45 L1 k 1.00 0.60 0.75 1.00 0.00 aaa 8.00 0.10 DocID026211 Rev 6 65/67 67 Order codes 11 A6986 Order codes Table 15. Order codes Part numbers Package A6986 Tube HTSSOP16 A6986TR 12 Packaging Tape and reel Revision history Table 16. Document revision history Date Revision Changes 14-May-2015 5 Updated Section 5.5.2: Low consumption mode (LCM) on page 25 (added cross-reference to Equation 14). Minor modifications throughout document. 6 Updated Section : Description on page 1. Updated Table 3: Thermal data on page 7 (added Rth JC row). Updated Table 6: fSW selection on page 11 (added note 3. below table). Updated Figure 6 on page 18, Figure 8 on page 20, Figure 9 on page 21, Figure 11 on page 23, Figure 13 on page 25 to Figure 23 on page 34, Figure 30 on page 44, Figure 32 on page 46 and Figure 33 on page 46 (replaced by new figures). Updated Equation 18 on page 35 (replaced RLOAD / Ri by RLOAD * gcs). Updated Section 7.5: Synchronization (LNM) on page 45 (replaced value of "range" "2 MHz" by "1.4 MHz", added text). 30-Nov-2015 66/67 DocID026211 Rev 6 A6986 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2015 STMicroelectronics - All rights reserved DocID026211 Rev 6 67/67 67 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: STMicroelectronics: A6986TR A6986