TPS43336QDAPQ1 - Texas Instruments High-Performance Analog

TPS43335-Q1/

TPS43336-Q1

VBuckA

VBuckB

VBAT

2 V

VBAT

VBUCKA

VBUCKB

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

LOW IQ, SINGLE BOOST, DUAL SYNCHRONOUS BUCK

CONTROLLER

Check for Samples: TPS43335-Q1,TPS43336-Q1

1FEATURES

•Two Synchronous Buck Controllers •Sense Resistor or Inductor DCR Sensing

•One Pre-Boost Controller •Out of Phase Switching between Buck

Channels

•Input Range up to 40V, (transients up to 60V),

Operation Down to 2V when Boost is enabled •Peak Gate Drive Current 0.7 A

•Low Power Mode IQ: 30µA (one Buck on), 35µA•Thermally Enhanced Package –38-Pin

(two Bucks on) HTSSOP (DAP) with PowerPadTM

•Low Shutdown Current Ish <4µA•Qualified for Automotive

•Buck Output Range 0.9V to 11V APPLICATIONS

•Boost Output Selectable: 7V/10V/11V •Automotive Start-Stop, Infotainment,

•Programmable frequency and External Navigation Instrument Cluster Systems

Synchronization Range 150kHz to 600kHz •Industrial/Automotive Multi-Rail DC Power

•Separate Enable Inputs (ENA, ENB) Distribution Systems and Electronic Control

•Frequency Spread Spectrum (TPS43336) Units

•Selectable Forced Continuous Mode or

Automatic Low Power Mode at Light Loads

DESCRIPTION

The TPS43335-Q1/TPS43336-Q1 includes two current mode synchronous buck controllers and a voltage mode

boost controller. The part is ideally suited as pre-regulator stage with low Iq requirements and systems that need

to survive supply drops due to cranking events. The integrated boost controller allows the device to operate down

to 2V at the input without seeing a drop on the Buck regulator output stages. At light loads, the buck controllers

can be enabled to operate automatically in Low Power Mode consuming just 30µA of quiescent current.

The buck controllers have independent soft start capability and power good indicators. External MOSFET

protection is provided by current fold back in the buck controllers and cycle-by-cycle current limitation in the

boost controller. The switching frequency can be programmed over 150 kHz to 600 kHz or synchronized to an

external clock in the same range. Additionally, the TPS43336-Q1 offers frequency-hopping spread spectrum

operation.

spacer

Figure 1. Typical Application Diagram

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION(1)

TJOPTION PACKAGE(2) ORDERABLE PART NUMBER

Frequency Hopping Spread Spectrum OFF TPS43335QDAPQ1

-40ºC to 150ºC DAP(3)

Frequency Hopping Spread Spectrum ON TPS43336QDAPQ1

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) The DAP package is available in tape and reel. Add the R suffix (TPS43335QDAPR, TPS43336QDAPR) to order.

space

ABSOLUTE MAXIMUM RATINGS(1)

MIN MAX UNIT

Voltage Input Voltage: VIN, VBAT –0.3 60 V

Enable Inputs: ENA, ENB –0.3 60 V

Bootstrap Inputs: CBA, CBB –0.3 68 V

Phase Inputs: PHA, PHB –0.7 60 V

Phase Inputs: PHA, PHB (for 150ns) –1.0 V

Feedback Inputs: FBA, FBB –0.3 13 V

Error amplifier outputs: COMPA, COMPB –0.3 13 V

Voltage High-Side MOSFET Driver: GA1-PHA, GB1-PHB –0.3 8.8 V

(Buck Function: Low-Side MOSFET Drivers: GA2, GB2 –0.3 8.8 V

Buck A and Buck B) Current Sense Voltage: SA1, SA2, SB1, SB2 –0.3 13 V

Soft Start: SSA, SSB –0.3 13 V

Power Good Output: PGA, PGB –0.3 13 V

Power Good Delay: DLYAB –0.3 13 V

Switching Frequency Timing Resistor: RT –0.3 13 V

SYNC, EXTSUP –0.3 13 V

Low-Side MOSFET Driver: GC1 –0.3 8.8 V

Error amplifier output: COMPC –0.3 13 V

Voltage Enable Input: ENC –0.3 13 V

(Boost Function) Current Limit Sense: DS –0.3 60 V

Output Voltage Select: DIV –0.3 8.8 V

P-Channel MOSFET Driver: GC2 –0.3 60 V

Voltage

(PMOS Driver) P-Channel MOSFET Driver: VIN-GC2 –0.3 8.8 V

Gate Driver Supply: VREG –0.3 8.8 V

Junction Temperature: TJ–40 150 °C

Temperature Operating Temperature: TA–40 125 °C

Storage Temperature: TS–55 165 °C

Human Body Model (HBM) ±2 kV

Charged Device Model (CDM)

- FBA, FBB, RT, DLYAB ±400 V

- VBAT, ENC, SYNC, VIN ±750

Electrostatic Discharge

Ratings - all other pins ±500

Machine Model (MM)

- PGA, PGB ±150 V

- all others ±200

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to GND.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT

Input Voltage: VIN, VBAT 4 40 V

Enable Inputs: ENA, ENB 4 40 V

Boot Inputs: CBA, CBB 4 44 V

Buck Function: Phase Inputs: PHA, PHB –0.6 40 V

Buck A and Buck B Current Sense Voltage: SA1, SA2, SB1, SB2 0 11 V

Voltage Power Good Output: PGA, PGB 0 11 V

Power Good Delay: DLYAB 0 6 V

SYNC, EXTSUP 0 9 V

Error amplifier output: COMPC 0 6 V

Enable Input: ENC 0 9 V

Boost Function Voltage Sense: DS 40 V

DIV 0 6 V

Thermal Resistance Junction to Ambient, θJA(1) 28 °C/W

Temperature Ratings Thermal Resistance Junction to pad, θJC(2) 10 °C/W

Operating Temperature: TA–40 125 °C

(1) This assumes a JEDEC JESD 51-5 standard board with thermal vias –See Power Pad section and application note from Texas

Instruments SLMA002 for more information.

(2) This assumes junction to exposed pad.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

DC ELECTRICAL CHARACTERISTICS

VIN = 8 V to 18 V, TJ= -40°C to 150°C (unless otherwise noted)

NO. TEST(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

1.0 Input Supply

Boost Controller enabled, after initial start up

1.1 PT VBat Supply Voltage 2 40 V

condition is satisfied

Input voltage required for device on initial start

Device Operating Range 6.5 40 V

1.2 PT VIN Buck regulator operating range after initial start 4 40 V

VIN Falling 3.5 3.6 3.8 V

1.3 PT VIN UV Buck Undervoltage Lockout VIN Rising 3.8 4 V

1.4 PT VBAT-Off Boost unlock threshold VBAT Rising 8.2 8.5 8.8 V

VIN = 13V, BuckA: LPM, BuckB: off 30 40 µA

LPM Quiescent Current:

1.5 PT Iq_LPM_ VIN = 13V, BuckB: LPM, BuckA: off

TA= 25°C(2)

VIN = 13V, BuckA, B: LPM 35 45 µA

VIN = 13V, BuckA: LPM, BuckB: off 40 50 µA

LPM Quiescent Current:

1.6 PT Iq_LPM VIN = 13V, BuckB: LPM, BuckA: off

TA= 125°C(2)

VIN = 13V, BuckA, B: LPM 45 55 µA

Normal operation, SYNC = 5V

VIN = 13V, BuckA: CCM, BuckB: off

Quiescent Current:

1.7 PT Iq_NRM 4.85 5.3 mA

TA= 25°C(2) VIN = 13V, BuckB: CCM, BuckA: off

VIN = 13V, BuckA, B: CCM 7 7.6 mA

Normal operation, SYNC = 5V

VIN = 13V, BuckA: CCM, BuckB: off

Quiescent Current:

1.8 PT Iq_NRM 5 5.5 mA

TA= 125°C(2) VIN = 13V, BuckB: CCM, BuckA: off

VIN = 13V, BuckA, B: CCM 7.5 8 mA

1.9 PT Ibat_sh Shutdown current ,TA= 25°C BuckA, B: off, VBat = 13V 2.5 4 µA

1.10 PT Ibat_sh Shutdown current ,TA= 125°C BuckA, B: off, VBat = 13V 3 5 µA

2.0 Input voltage VBAT - Undervoltage lock out

VBAT falling 1.8 1.9 2 V

2.1 PT VBATUV Boost Input Undervoltage VBAT rising 2.4 2.5 2.6 V

2.2 PT UVLOHys Hysteresis 500 600 700 mV

2.3 PT UVLOfilter Filter time 5 µs

3.0 Input voltage VIN - Over voltage lock out

(based on VIN sense) Rising 45 46 47 V

3.1 PT VOVLO Overvoltage shutdown Falling 43 44 45 V

3.2 PT OVLOHys Hysteresis 1 2 3 V

3.3 PT OVLOfilter Filter time 5 µs

4.0 Boost Controller

4.1 PT Vboost7-VIN Boost VOUT = 7V DIV = low, VBAT = 2 V to 7 V 7 V

VBAT falling –Boost enable threshold 7.5 8 8.5 V

Boost mode threshold

4.2 PT Vboost7-th VBAT rising –Boost disable threshold 8 8.5 9 V

Boost VOUT = 7V Hysteresis 0.4 0.5 0.6 V

4.3 PT Vboost10-VIN Boost VOUT = 10V DIV = open, VBAT = 2 V to 10 V 10 V

VBAT falling –Boost enable threshold 10.5 11 11.5 V

Boost mode threshold

4.4 PT Vboost10-th VBAT rising –Boost disable threshold 11 11.5 12 V

Boost VOUT = 10V Hysteresis 0.4 0.5 0.6 V

4.5 Info Vboost11-VIN Boost VOUT = 11V DIV = VREG, VBAT = 2 V to 11 V 11 V

(1) PT = Production tested; CT = Characterization only, not production tested; Info = Information based on simulations and lab evaluation,

not production tested

(2) Quiescent current specification is non-switching current consumption without including the current in the external feedback resistor

divider.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 V to 18 V, TJ= -40°C to 150°C (unless otherwise noted)

NO. TEST(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VBAT falling –Boost enable threshold 11.5 12 12.5 V

Boost mode threshold

4.6 Info Vboost11-th VBAT rising –Boost disable threshold 12 12.5 13 V

Boost VOUT = 11V Hysteresis 0.4 0.5 0.6 V

Boost Switch current limit

4.7 PT VDS Current limit sensing DS input with respect to PGNDA 0.175 0.2 0.225 V

4.8 Info tDS leading edge blanking 200 ns

Gate Driver for Boost Controller

4.9 Info IGC1 Peak Gate driver peak current 1.5 A

4.10 PT RDS(ON) Source and Sink driver VREG = 5.8V, IGC1 current = 200mA 2 Ω

Gate Driver for PMOS

4.11 PT RDS ON PMOS OFF 10 20 Ω

4.12 PT IPMOS_ON Gate current VIN = 13.5V, Vgs = -5V 10 mA

4.13 PT tdelay_ON Turn ON delay C = 10nF 5 10 µs

Boost Controller Switching frequency

4.14 PT fsw-Boost Boost Switching Frequency fSW_Buck/2 kHz

4.15 PT DBoost Boost duty cycle 90%

Error Amplifier (OTA) for Boost Converters

VBAT = 12V 0.8 1.35

4.16 PT GmBOOST Forward Transconductance mmho

VBAT = 5V 0.35 0.65

5.0 Buck Controllers

5.1 PT VBuckA/B Adjustable. output voltage range 0.9 11 V

PT Measure FBX pin 0.792 0.800 0.808 V

internal reference voltage in

5.2 Vref, NRM normal mode

Info Internal tolerance on reference -1% +1%

PT Measure FBX pin 0.784 0.800 0.816 V

internal reference voltage in low

5.3 Vref, LPM power mode

Info Internal tolerance on reference -2% +2%

V sense for forward current limit in Maximum sense voltage FBx = 0.75V

5.4 PT 60 75 90 mV

CCM (low duty cycles)

Vsense V sense for reverse current limit in

5.5 PT Minimum sense voltage FBx = 1V -65 -37.5 -23 mV

CCM

5.6 CT VI-Foldback V sense for output short Sense voltage in foldback FBx = 0V 17 32.5 48 mV

shoot through delay, blanking

5.7 Info tdead 20 ns

time

CT High side minimum on time 100 ns

5.8 DCNRM Duty cycle

Info Maximum duty cycle (digitally controlled) 98.75%

5.9 CT DCLPM Duty Cycle LPM 80%

LPM entry threshold load current

ILPM_Entry as fraction of maximum set load 1%

current The exit threshold is specified to be always

5.10 Info higher than entry threshold

LPM exit threshold load current as

ILPM_Exit fraction of maximum set load 10%

current

High Side external NMOS Gate Drivers for Buck Controller

5.11 Info IGX1_peak Gate driver peak current 0.7 A

5.12 PT RDS ON Source and Sink driver VVREG = 5.8V, IGX1 current = 200mA 4 Ω

Low Side NMOS Gate Drivers for Buck Controller

5.13 Info IGX2_peak Gate driver peak current 0.7 A

5.14 PT RDS ON Source and sink driver VREG = 5.8V, IGX2 current = 200mA 4 Ω

Error Amplifier (OTA) for Buck Converters

COMPA, COMPB = 0.8V,

5.15 PT GmBUCK Transconductance 0.72 1 1.35 mmho

source/sink = 5µA, Test in feedback loop

5.16 PT IPULLUP_FBx Pull-Up Current at FBx pins FBx = 0V 50 100 200 nA

6.0 Digital Inputs: ENA, ENB, ENC, SYNC

6.1 PT Vih Higher threshold VIN = 13V 1.7 V

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 V to 18 V, TJ= -40°C to 150°C (unless otherwise noted)

NO. TEST(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

6.2 PT Vil Lower threshold VIN = 13V 0.7 V

6.3 PT Rih_SYNC Resistance VSYNC = 5V, SYNC: pull down resistance 500 kΩ

6.4 PT Ril_ENC Resistance VENC = 5V, ENC: pull down resistance 500 kΩ

VENx = 0V,

6.5 PT Iil_ENx pull-up current 0.5 2 µA

ENA, ENB: pull up current source

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 V to 18 V, TJ= -40°C to 150°C (unless otherwise noted)

NO. TEST(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

7.0 Boost Output Voltage: DIV

Vreg-

7.1 PT Vih_DIV Higher threshold VREG = 5.8V V

0.2

7.2 PT Vil_DIV Lower threshold 0.2 V

7.3 PT Voz_DIV open floating Vreg/2 V

8.0 Switching Parameter –Buck DC-DC Controllers

8.1 PT fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz

8.2 PT fSW_Buck Buck switching frequency RT pin: 60kΩexternal resistor 360 400 440 kHz

8.3 PT fSW_adj Buck adjustable range RT pin: using external resistor 150 600 kHz

8.4 PT fSYNC Buck synch. range External clock input 150 600 kHz

8.5 PT fSS Spread Spectrum spreading TPS43336-Q1 only 5%

9.0 Internal Gate Driver Supply

Internal regulated supply VIN = 8V to 18V, EXTSUP = 0V, SYNC = high 5.5 5.8V 6.1 V

9.1 PT VREG IVREG = 0mA to 100mA, EXTSUP = 0V,

Load Regulation 0.2% 1%

SYNC = high

Internal Regulated supply EXTSUP = 8.5V 7.2 7.5 7.8 V

9.2 PT VREG-EXTSUP IEXTSUP = 0mA to 125mA, SYNC = High

Load Regulation 0.2 1 %

EXTSUP = 8.5V to 13V

VEXTSUP- IVREG = 0mA to 100mA ,

9.3 PT Switch over voltage 4.4 4.6 4.8 V

VREG EXTSUP ramping positive

9.4 PT VEXTSUP-Hys Switch over hysteresis 150 250 mV

9.5 PT IREG-Limit Current Limit on VREG EXTSUP = 0V, normal mode as well as LPM 100 400 mA

IREG_EXTSUP- Current Limit on VREG when IVREG = 0mA to 100mA,

9.6 PT 125 400 mA

Limit using EXTSUP EXTSUP = 8.5V, SYNC = High

10.0 Soft Start

10.1 PT ISSx Soft Start source current SSA and SSB = 0V 0.75 1 1.25 µA

11.0 Oscillator (RT)

11.1 PT VRT Oscillator reference voltage 1.2 V

12.0 Power Good / Delay

12.1 PT PGpullup Pullup for A and B internal pullup to Sx2 50 kΩ

12.2 PT PGth1 Power Good Threshold FBx falling -5 -7 -9 %

12.3 PT PGhys Hysteresis 2%

12.4 PT PGdrop Voltage drop IPGA = 5mA 450 mV

12.5 PT IPGA = 1mA 100 mV

12.6 PT PGleak Leakage VSx2 = VPGx = 13V 1 µA

12.7 PT tdeglitch Deglitch Time Power Good deglitch 2 16 µs

External capacitor = 1nF

12.8 PT tdelay Reset Delay 1 ms

VBUCKX <PGth1

12.9 PT tdelay_fix Fixed Reset Delay No external capacitor, pin open 20 50 µs

12.10 PT Ioh Activate current source Current to charge external capacitor 30 40 50 µA

12.11 PT Iil Activate current sink Current to discharge external capacitor 30 40 50 µA

13.0 Over Temperature Protection

13.1 CT Tshutdown shutdown threshold Junction temperature 150 165 °C

13.2 CT Thys Hysteresis 15 °C

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

19 20

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC SYNC

DLYAB

AGND

PGB

SSB

COMPB

FBB

SB2

SB1

PGNDB

GB2

PHB

GB1

CBB

VREG

DIV

EXTSUP

VIN

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

DEVICE INFORMATION

DAP PACKAGE

(TOP VIEW)

PIN FUNCTIONS

NO. NAME I/O DESCRIPTION

Battery input sense for the boost controller. If the boost controller is enabled and the voltage at VBAT falls below

1 VBAT I the boost threshold, the device will activate the boost controller and regulate the voltage at VIN to the

programmed boost output voltage.

This input monitors the voltage on the external Boost converter low-side MOSFET for over current protection.

2 DS I Alternatively, it can be connected to a sense resistor between the source of the low-side MOSFET and ground via

a filter network for better noise immunity.

An external low-side N-channel MOSFET for the boost regulator can be driven from this output. This output

3 GC1 O provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.

A floating output drive to control the external P-channel MOSFET is available at this pin. This MOSFET can be

4 GC2 O used to bypass the boost rectifier diode or a reverse protection diode when the boost is not switching or disabled,

and thus reduce power losses.

A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate drive circuitry in the

5 CBA I buck controller BUCK A. When the buck is in a dropout condition, the device automatically reduces the duty cycle

of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to re-charge.

External high-side N-channel MOSFET for the buck regulator BUCK A can be driven from these output. The

6 GA1 O output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground

reference provided by the PHA and has a voltage swing provided by CBA.

Switching terminal of the buck regulator BUCK A, providing a floating ground reference for the high-side MOSFET

7 PHA O gate driver circuitry and is used to sense current reversal in the inductor when discontinuous mode operation is

desired.

External low-side N-channel MOSFET for the buck regulator BUCK A can be driven from this output. The output

8 GA2 O provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.

9 PGNDA O Power ground connection to the source of the low-side N-channel MOSFETs of BUCK A.

10 SA1 I High Impedance differential voltage inputs from the current sense element (sense resistor or inductor DCR) for

each buck controller. The current sense element should be chosen to set the maximum current through the

inductor based on the current limit threshold (subject to tolerances) and considering the typical characteristics

11 SA2 I across duty cycle and VIN. (SA1 positive node, SA2 negative node).

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

PIN FUNCTIONS (continued)

NO. NAME I/O DESCRIPTION

Feedback voltage pin for BUCK A. The buck controller regulates the feedback voltage to the internal reference of

12 FBA I 0.8V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output

voltage.

Error amplifier output of BUCK A and compensation node for voltage loop stability. The voltage at this node sets

13 COMPA O the target for the peak current through the respective inductor. This voltage is clamped on the upper and lower

ends to provide current limit protection for the external MOSFETs.

Soft-start or tracking input for the buck controller BUCK A. The buck controller regulate the FBA voltage to the

lower of 0.8V or the SSA pin voltage. An internal pull-up current source of 1µA is present at the pin and an

14 SSA O appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected

to another supply can also be used to provide a tracking input to this pin.

Open drain power good indicator pin for BUCK A. An internal power good comparator monitors the voltage at the

15 PGA O feedback pin and pull this output low when the output voltage falls below 93% of the set value, or if either Vin or

Vbat drops below their respective undervoltage threshold.

Enable inputs for BUCK A (active high with an internal pull up current source). An input voltage higher than 1.5V

16 ENA I enables the controller while an input voltage lower than 0.7V disables the controller. When both ENA and ENB are

low, the device is shut down and consumes less than 4µA of current.

Enable inputs for BUCK B (active high with an internal pull up current source). An input voltage higher than 1.5V

17 ENB I enables the controller while an input voltage lower than 0.7V disables the controller. When both ENA and ENB are

low, the device is shut down and consumes less than 4µA of current.

18 COMPC O Error amplifier output and loop compensation node of the boost regulator.

This input enables and disables the boost regulator. An input voltage higher than 1.5V enables the controller.

19 ENC I Voltages lower than 0.7V disable the controller. When enabled, the controller will start switching as soon as VBAT

falls below the boost threshold depending upon the programmed output voltage.

If an external clock is present on this pin the device detects it and the internal PLL locks on to the external clock.

This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600

kHz. A high logic level on this pin ensures forced continuous mode operation of the buck controllers and inhibits

20 SYNC I transition to low power mode. An open or low allows discontinuous mode operation and entry into low power

mode at light loads. On the TPS43336-Q1, a high level enables frequency-hopping spread spectrum while an

open or a low level disables it.

The capacitor at the DLYAB pin sets the power good delay interval used to de-glitch the outputs of the power

21 DLYAB O good comparators. When this pin is left open, the power good delay is set to an internal default value of 20µsec

typical.

The operating switching frequency of the buck and boost controllers is set by connecting a resistor to ground on

22 RT O this pin. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for

the boost controller.

23 AGND O Analog Ground Reference

Open drain power good indicator pin for BUCK B. An internal power good comparator monitors the voltage at the

24 PGB O feedback pin and pull this output low when the output voltage falls below 93% of the set value, or if either Vin or

Vbat drops below their respective undervoltage threshold.

Soft-start or tracking input for the buck controller BUCK B. The buck controller regulate the FBB voltage to the

lower of 0.8V or the SSB pin voltage. An internal pull-up current source of 1µA is present at the pin and an

25 SSB O appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected

to another supply can also be used to provide a tracking input to this pin.

Error amplifier output of BUCK B and compensation node for voltage loop stability. The voltage at this node sets

26 COMPB O the target for the peak current through the respective inductor. This voltage is clamped on the upper and lower

ends to provide current limit protection for the external MOSFETs.

Feedback voltage pin for BUCK B. The buck controller regulates the feedback voltage to the internal reference of

27 FBB I 0.8V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output

voltage.

28 SB2 I High Impedance differential voltage inputs from the current sense element (sense resistor or inductor DCR) for

each buck controller. The current sense element should be chosen to set the maximum current through the

inductor based on the current limit threshold (subject to tolerances) and considering the typical characteristics

29 SB1 I across duty cycle and VIN. (SB1 positive node, SB2 negative node).

30 PGNDB O Power ground connection to the source of the low-side N-channel MOSFETs of BUCK B.

External low-side N-channel MOSFETs for the buck regulator BUCK B can be driven from this output. The output

31 GB2 O provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG.

Switching terminal of the buck regulator BUCK B, providing a floating ground reference for the high-side MOSFET

32 PHB O gate driver circuitry and is used to sense current reversal in the inductor when discontinuous mode operation is

desired.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

PIN FUNCTIONS (continued)

NO. NAME I/O DESCRIPTION

External high-side N-channel MOSFET for the buck regulator BUCK B can be driven from these output. The

33 GB1 O output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground

reference provided by the PHB and has a voltage swing provided by CBB.

A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate drive circuitry in the

34 CBB I buck controller BUCK B. When the buck is in a dropout condition, the device automatically reduces the duty cycle

of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to re-charge.

An external capacitor on this pin is required to provide a regulated supply for the gate drivers of the buck and

boost controllers. A capacitance in the order of 4.7uF is recommended. The regulator can be used such that it is

35 VREG O either powered from VIN or EXTSUP. This pin has a current limit protection and should not be used to drive any

other loads.

The status of this pin defines the output voltage of the boost regulator. A high input regulates the Boost converter

36 DIV I at 11V, a low input sets the value at 7V and a floating pin sets 10V.

EXTSUP can be used to supply the VREG regulator from one of the TPS43335-Q1/TPS43336-Q1 buck regulator

37 EXTSUP I rails to reduce power dissipation in cases where VIN is expected to be high. When EXTSUP is open or lower than

4.6V, the regulator is powered from VIN.

Main Input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally it

38 VIN I powers the internal control circuits of the device.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

VIN

SYNC

GA1

FBA

GA2

CBA

SA1

SA2

PGNDA

COMPA

ENA

PGA

GC2

VREG

DLYAB

PHA

SSA

EXTSUP

Filter timer

–

0.8V

PWM

comp +

Slope Comp

OTA

Current sense

Amp

PWM logic

40 Am

Internal ref

(Band gap)

VREF

SA2

VREF

Gate Driver

Supply

Internal

Oscillator

SYNC &

LPM

180 deg

ENA

1 Am

Source/

Sink

Logic

ENB

VIN

500 nA

1 Am

SSB

ENB

Duplicate for second

Buck controller channel

GB1

FBB

GB2

CBB

SB1

SB2

PGNDB

COMPB

PGB

PHB

VREG

SSA

PWM

Logic

Vref

VBAT

VIN

0.2V

OTA

OCP

DIV

COMPC

GC1

ENC

PWM

comp

AGND

Second Buck Controller

Channel

VREG

PGNDA

FBA

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

Figure 2. Functional Block Diagram

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

OUTPUT CURRENT (A)

EFFICIENCY (%)

EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS)

POWER LOSS (mW)

EFFICIENCY,

SYNC = LOW

POWER LOSS,

SYNC = HIGH

POWER LOSS,

SYNC = LOW

EFFICIENCY,

SYNC = HIGH

VIN = 12V, VOUT = 5V, SWITCHING FREQUENCY = 400kHz

INDUCTOR = 4.7µH, RSENSE = 10mW

0.0001 0.001 0.01 0.1 110

100

0.1

100

1000

10000

SOFT-START OUTPUTS (BUCK)

2ms/DIV

VOUTA

VOUTB

1V/DIV

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

TYPICAL CHARACTERISTICS

Figure 3. Figure 4.

Figure 5. Figure 6.

Figure 7. Figure 8.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

LOAD STEP RESPONSE (BOOST)

(0 TO 5A AT 2.5A/µs)

2ms/DIV

VIN (BOOST OUTPUT) AC-COUPLED

IIND

5A/DIV

500mV/DIV

VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V,

SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,

RSENSE = 7.5m , CIN = 440µF, COUT = 660µFW

OUTPUT CURRENT (A)

EFFICIENCY (%)

EFFICIENCY ACROSS OUTPUT CURRENTS (BOOST)

VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz,

INDUCTOR = 1.0µH, RSENSE = 7.5mW

0.01 110

100

VBAT = 8V

VBAT = 5V

VBAT = 3V

CRANKING PULSE BOOST RESPONSE

(12V to 3V IN 1ms AT BUCK OUTPUTS 7.5W/11.5W)

20ms/DIV

VBAT (BOOST INPUT)

5V/DIV

VOUT BUCKA AC-COUPLED

200mV/DIV

VOUT BUCKB AC-COUPLED

200mV/DIV

IIND

10A/DIV

VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A,

SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,

RSENSE = 7.5mOHM, CIN = 440µF, COUT = 660µF

CRANKING PULSE BOOST RESPONSE

(12V to 4V IN 1ms AT BOOST DIRECT OUTPUT 25W)

20ms/DIV

VBAT (BOOST INPUT)

5V/DIV

VIN (BOOST OUTPUT)

5V/DIV

IIND

10A/DIV

VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A,

SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,

RSENSE = 7.5mOHM, CIN = 440µF, COUT = 660µF

INDUCTOR CURRENTS (BOOST)

VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V,

SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0µH,

RSENSE = 7.5m , CIN = 440µF, COUT = 660µFW

2µs/DIV

3A LOAD

5A/DIV

100mA LOAD

5A/DIV

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

TYPICAL CHARACTERISTICS (continued)

Figure 9. Figure 10.

Figure 11. Figure 12.

Figure 13.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

BUCKx PEAK CURRENT LIMIT vs. COMPx VOLTAGE

COMPx VOLTAGE (V)

PEAK CURRENT SENSE VOLTAGE (mV)

SYNC = LOW

SYNC = HIGH

0.65 0.8 0.95 1.1 1.25 1.4 1.55

-37.5

-25

-12.5

12.5

37.5

62.5

BOTH BUCKS ON

ONE BUCK ON

NEITHER BUCK ON

Quiescent Current (µA)

Temperature (°C)

-40 -15 10 35 60 85 110 135 160

NO-LOAD QUIESCENT CURRENT

ACROSS TEMPERATURE

CURRENT SENSE PINS INPUT CURRENT (BUCK)

OUTPUT VOLTAGE (V)

SENSE CURRENT (µA)

01 2 345678 9 10 11 12

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

150°C

25°C

FOLDBACK CURRENT LIMIT (BUCK)

FBx VOLTAGE (V)

PEAK CURRENT SENSE VOLTAGE (mV)

0 0.2 0.4 0.6 0.8

REGULATED FBx VOLTAGE vs TEMPERATURE (BUCK)

TEMPERATURE (°C)

REGULATED FBx VOLTAGE (mV)

-40 -15 10 35 60 85 110 135 160

795

796

797

798

799

800

801

802

803

804

805

CURRENT LIMIT VS DUTY CYCLE (BUCK)

DUTY CYCLE (%)

PEAK CURRENT SENSE VOLTAGE (mV)

0 10 20 30 40 50 60 70 80 90 100

VIN = 8V

VIN = 12V

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

Figure 14. Figure 15.

Figure 16. Figure 17.

Figure 18. Figure 19.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

f = (X=24kΩ×MHz)

f =24× RT

I ×Δt

C = (Farads)

ΔV

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

DETAILED DESCRIPTION

Feedback Inputs

BUCK CONTROLLERS: NORMAL MODE

PWM OPERATION The output voltage is set by choosing the right

resistor feedback divider network connected to the

Frequency Selection and External FBx (feedback) pins. This is to be chosen such that

Synchronization the regulated voltage at the FBx pin equals 0.8V. The

FBx pins have a 100nA pull up current source as a

The buck controllers operate using constant protection feature in case the pins open up as a

frequency peak current mode control for optimal result of physical damage.

transient behavior and ease of component choices.

The switching frequency is programmable between Soft-Start Inputs

150 kHz and 600 kHz depending upon the resistor

value at the RT pin. A short circuit to ground at this In order to avoid large inrush currents, both buck

pin sets the default switching frequency to 400 kHz. controllers have independent programmable soft-start

The frequency can also be set by a resistor at RT timer. The voltage at the SSx pins acts as the

according to the formula: soft-start reference voltage. A 1µA pull-up current is

available at the SSx pins and by choosing a suitable

capacitor a ramp of the desired soft-start speed can

be generated. After start-up, the pull-up current

ensures that this node is higher than the internal

reference of 0.8V which then becomes the reference

for the buck controllers. The soft-start ramp time is

Equation 1 Switching Frequency defined by:

For example,

600kHz requires 40kΩ

Equation 2 SoftStart Ramp Time

150kHz requires 160kΩWhere,

It is also possible to synchronize to an external clock

at the SYNC pin in the same frequency range of 150 ISS = 1µA (typical)

kHz to 600 kHz. The device detects clock pulses at ∆V = 0.8V

this pin and an internal PLL locks on to the external

clock within the specified range. The device can also CSS is the required capacitor for ∆t, the desired

detect a loss of clock at this pin and when this is soft-start time.

detected it sets the switching frequency to the internal Alternatively the soft-start pins can be used as

oscillator. The two buck controllers operate at tracking inputs. In this case, they should be

identical switching frequencies 180 degrees out of connected to the supply to be tracked via a suitable

phase. resistor divider network.

Enable Inputs Current Mode Operation

The buck controllers are enabled using independent Peak current-mode control regulates the peak current

enable inputs from the ENA and ENB pins. These are through the inductor such that the output voltage is

high voltage pins with a threshold of 1.5V for high maintained to its set value. The error between the

level and can be connected directly to the battery for feedback voltage at FBx and the internal reference

self-bias. The low threshold is 0.7V. Both these pins produces a signal at the output of the error amplifier

have internal pull-up currents of 0.5µA (typical). As a (COMPx) which serves as target for the peak inductor

result, an open circuit on these pins enables the current. The current through the inductor is sensed as

respective buck controllers. When both buck a differential voltage at Sx1-Sx2 and compared with

controllers are disabled, the device is shut down and this target during each cycle. A fall or rise in load

consumes a current less than 4µA. current produces a rise or fall in voltage at FBx

causing COMPx to fall or rise respectively, thus

increasing/decreasing the current through the

inductor until the average current matches the load.

In this way the output voltage is maintained in

regulation.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

DCR

Inductor L

VBUCK X

Sx2

Sx1

TPS43335-Q1/

TPS43336-Q1

L×f =200

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

The top N-channel MOSFET is turned on at the

beginning of each clock cycle and kept on until the

inductor current reaches its peak value. Once this

MOSFET is turned off, and after a small delay

(shoot-through delay) the lower N-channel MOSFET

is turned on until the start of the next clock cycle. In

dropout operation the high-side MOSFET stays on

100%. In every fourth clock cycle the duty cycle is

limited to 95% in order to charge the bootstrap

capacitor at CBx. This allows a maximum duty cycle

of 98.75% for the buck regulators. During dropout the

buck regulator switches at one-fourth of its normal

frequency. Figure 20. DCR Sensing Configuration

Current Sensing and Current Limit with Foldback Slope Compensation

The maximum value of COMPx is clamped such that

the maximum current through the inductor is limited Optimal slope compensation which is adaptive to

to a specified value. When the output of the buck changes in input voltage and duty cycle allows stable

regulator (and hence the feedback value at FBx) falls operation at all conditions. For optimal performance

to a low value due to a short circuit/over-current of this circuit, the following condition must be satisfied

condition, the clamped voltage at the COMPx in the choice of inductor and sense resistor:

successively decreases, thus providing current fold

back protection. This protects the high-side external

MOSFET from excess current (forward direction

current limit). Equation 3 Inductor and Sense Resistor Choice

Similarly, if due to a fault condition the output is Where

shorted to a high voltage and the low-side MOSFET L is the buck regulator inductor in Henry

turns fully on, the COMPx node will drop low. It is

clamped on the lower end as well in order to limit the RSis the sense resistor in Ohm

maximum current in the low-side MOSFET (reverse fsw is the buck regulator switching frequency in Hertz

direction current limit).

The current through the inductor is sensed by an Power Good Outputs and Filter Delays

external resistor. The sense resistor should be Each buck controller has an independent power good

chosen such that the maximum forward peak current comparator monitoring the feedback voltage at the

in the inductor generates a voltage of 75mV across FBx pins and indicating whether the output voltage

the sense pins. This value is specified at low duty has fallen below a specified power good threshold.

cycles only. At typical duty cycle conditions around this threshold has a typical value of 93% of the

40% (assuming 5V output and 12V input), 50mV is a regulated output voltage. the power good indicator is

more reasonable value, considering tolerances and available as an open drain output at the PGx pins. An

mismatches. the typical characteristics provide a internal 50kΩpull-up resistor to Sx2 is available or an

guide for using the correct current limit sense voltage. external resistor can be used. When a buck controller

The current sense pins Sx1 and Sx2 are high is shut down, the power good indicator is pulled down

impedance pins with low leakage across the entire internally. Connecting the pull/up resistor to a rail

output range. This allows DCR current sensing using other than the output of that particular buck channel

the DC resistance of the inductor for higher efficiency. will cause a constant current flow through the resistor

DCR sensing is shown in the below figure. Here the when the buck controller is powered down.

series resistance (DCR) of the inductor is used as the In order to avoid triggering the power good indicators

sense element. The filter components should be due to noise or fast transients on the output voltage,

placed close to the device for noise immunity. It an internal delay circuit for de-glitching is used.

should be remembered that while the DCR sensing Similarly, when the output voltage returns to its set

gives high efficiency, it is inaccurate due to the value after a long negative transient, the power good

temperature sensitivity and a wide variation of the indicator will be asserted high (the open-drain pin

parasitic inductor series resistance. Hence it may released) after the same delay. This can be used to

often be advantageous to use the more accurate delay the reset to the circuits being powered from the

sense resistor for current sensing. buck regulator rail. The delay of this circuit can be

programmed by using a suitable capacitor at the

DLYAB pin according to the equation:

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

DELAY

DLYAB

t 1 msec

C 1 nF

TPS43335-Q1

TPS43336-Q1

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SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

The TPS43335-Q1/TPS43336-Q1 can support the full

current load during low power mode until the

transition to normal mode takes place. The design

ensures the low power mode exit occurs at 10%

Equation 4 Power Good Indicator Delay (typical) of full load current if the inductor and sense

When the DLYAB pin is open the delay is set to a resistor have been chosen as recommended.

default value of 20µsec typical. The power good Moreover, there is always a hysteresis between the

delay timing is common to both the buck rails but the entry and exit thresholds to avoid oscillating between

power good comparators and indicators function the two modes.

independently. In the event that both buck controllers are active, low

power mode is only possible when both buck

Light Load PFM Mode controllers have light loads that are low enough for

An external clock or a high level on the SYNC pin low power mode entry. When the boost controller is

results in forced continuous mode operation of the enabled, low power mode is possible only if VBAT is

bucks. When the SYNC pin is low or open, the buck high enough to prevent the boost from switching and

controllers will be allowed to operate in discontinuous if DIV is open or set to GND. If DIV is high (VREG),

mode at light loads by turning off the low-side low power mode is inhibited. .

MOSFET whenever a zero-crossing in the inductor

current is detected. Boost Controller

In discontinuous mode, as the load decreases, the The boost controller has a fixed frequency voltage

duration of the clock period when both the high-side mode architecture and includes a cycle-by-cycle

as well the low-side MOSFET is turned off increases current limit protection for the external N-channel

(deep discontinuous mode). In case the duration MOSFET. The switching frequency is derived from

exceeds 60% of the clock period and VBAT >8V, the and set to one half of the buck controller switching

buck controller switches to a low power operation frequency. The output voltage of the boost controller

mode. The design ensures that this typically occurs at at the VIN pin is set by an internal resistor divider

1% of the set full load current if the inductor and the network and is programmable to 7V, 10V and 11V

sense resistor have been chosen appropriately as based on the low, open and high status respectively

recommended in the slope compensation section. of the DIV pin. A change of the DIV-setting is not

recognized, while the device is in low power mode.

In Low Power PFM Mode the buck monitors the FBx

voltage and compares it with the 0.8V internal The boost controller is enabled by the active-high

reference. Whenever the FBx value falls below the ENC pin and is active when the input voltage at the

reference, the high-side MOSFET is turned on for a VBAT pin has crossed the unlock threshold of 8.5V at

pulse-duration inversely proportional to the difference least once. After that, the boost controller is armed

VIN-Sx2. At the end of this on-time, the high-side and starts switching as soon as VIN falls below the

MOSFET is turned off and the current in the inductor value set by the DIV pin and regulates the VIN

decays until it becomes zero. The low-side MOSFET voltage. Thus, the boost regulator maintains a stable

is not turned on. The next pulse occurs the next time input voltage for the buck regulators during transient

FBx falls below the reference value. This results in a events such as cranking pulse at VBAT.

constant volt-second Ton hysteretic operation with a

total device quiescent current consumption of 30µA Whenever the voltage at the DS pin exceeds 200mV,

when a single buck channel is active and 35µA when the boost external MOSFET is turned off by pulling

both channels are active. the GC1 pin low. By connecting the DS pin to the

drain of the MOSFET or to a sense resistor between

As the load increases, the pulse become more and the MOSFET source and ground, cycle-by-cycle

more frequent and move closer to each other until the over-current protection for the MOSFET can be

current in the inductor becomes continuous. At this achieved. The on-resistance of the MOSFET or the

point, the buck controller returns to normal fixed value of the sense resistor has to be chosen in such

frequency current mode control. Another criteria to a way that the on-state voltage at the DS does not

exit the low power mode is when VIN falls low exceed 200mV at the maximum load and minimum

enough to require higher than 80% duty cycle of the input voltage conditions. When sense resistor is

high-side MOSFET. used , a filter network is recommended to be

connected between the DS pin and the sense resistor

for better noise immunity.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

GC1

TPS43335-Q1/

TPS43336-Q1

VIN

Vbat

RISEN

RIFLT

CIFLT

GC1

TPS43335-Q1/

TPS43336-Q1

VIN

Vbat

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

The boost output (VIN) can also be used to supply

other circuits in the system. However they should be

high-voltage tolerant. The boost output is regulated to

the programmed value only when VIN is low and so

VIN can reach battery levels.

Figure 22. External Current Shunt Resistor

Figure 21. External Drain-Source Voltage Sensing

Frequency-Hopping Spread Spectrum (TPS43336-Q1 only)

The TPS43336-Q1 features a frequency-hopping pseudo-random spectrum spreading architecture. On this

device, whenever the SYNC pin is high, the internal oscillator frequency is varied from one cycle to the next

within a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a

linear feedback shift register that changes the frequency of the internal oscillator based on a digital code. The

shift register is long enough to make the hops pseudo-random in nature and is designed in such a way that the

frequency shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies.

Table 1. Frequency Hopping Control

Sync Frequency Spread Spectrum (FSS) Comments

Terminal

Device in forced continuous mode, internal PLL locks into external clock

External clock Not active between 150kHz and 600kHz.

Device can enter discontinuous mode. Automatic LPM entry and Exit

Low or open Not active depending on load conditions

TPS43335-Q1: FSS not active

High Device in forced continuous mode

TPS43336-Q1: FSS active

Table 2. Mode of Operation

ENABLE AND INHIBIT PINS DRIVER STATUS DEVICE STATUS QUIESCENT CURRENT

ENA ENB ENC SYNC BUCK CONTROLLERS BOOST CONTROLLER

Low Low Low X Shutdown disabled Shutdown ~4 µA

Low Buck B: LPM enabled ~30µA (light loads)

Low High Low Buck B running disabled

High Buck B: LPM inhibited mA range

Low Buck A: LPM enabled ~30µA (light loads)

High Low Low Buck A running disabled

High Buck A: LPM inhibited mA range

Low Buck A/B: LPM enabled ~35µA (light loads)

High High Low Buck A&B running disabled

High Buck A/B: LPM inhibited mA range

Low Low Low X Shutdown disabled Shutdown ~4 µA

Low Buck B: LPM enabled ~50µA (no boost, light loads)

Boost running for VIN <set

Low High High Buck B running Boost Output

High Buck B: LPM inhibited mA range

Low Buck A: LPM enabled ~50µA (no boost, light loads)

Boost running for VIN <set

High Low High Buck A running Boost Output

High Buck A: LPM inhibited mA range

Low Buck A/B: LPM enabled ~60µA (no boost, light loads)

Boost running for VIN <set

High High High Buck A and B running Boost Output

High Buck A/B: LPM inhibited mA range

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

C14

Fuse (S1)

C13

C15C17

C16

R10

GC2

VIN

GC1

COMPC

VBAT

Vbat

TPS43335-Q1/

TPS43336-Q1

TPS43335-Q1/

TPS43336-Q1

GC2

VBAT

Fuse

VIN

GC1

COMPC

VBAT

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

Gate Driver Supply (VREG, EXTSUP) scheme of reverse battery protection which may

require only a smaller sized diode to protect the

The gate drivers of the buck and boost controllers are N-channel MOSFET as it conducts only for a part of

supplied from an internal linear regulator whose the switching cycle. Since it is not always in series

output (5.8V typical) is available at the VREG pin and path, the system efficiency can be improved.

should be decoupled using at least a 1µF ceramic

capacitor. This pin has an internal current limit

protection and should not be used to power any other

circuits.

The VREG linear regulator is powered from VIN by

default when the EXTSUP voltage is lower than 4.6V

(typ.). In case VIN expected to go to high levels,

there can be excessive power dissipation in this

regulator, especially at high switching frequencies

and when using large external MOSFET's. In this

case, it is advantageous to power this regulator from

the EXTSUP pin which can be connected to a supply

lower than VIN but high enough to provide the gate Figure 23. Reverse Battery Protection Option for

drive. When EXTSUP is connected to a voltage Buck Boost Configuration

greater than 4.6V, the linear regulator automatically

switches to EXTSUP as its input to provide this

advantage. Efficiency improvements are possible

when one of the switching regulator rails from the

TPS43335-Q1/TPS43336-Q1 or any other voltage

available in the system is used to power the

EXTSUP. The maximum voltage that should be

applied to EXTSUP is 13V.

Using a large value for EXTSUP is advantageous as

it provides a large gate drive and hence better

on-resistance of the external MOSFET's. A 0.1µF

ceramic capacitor is recommended for decoupling the Figure 24. Reverse Battery Protection Option for

EXTSUP pin when not being used. Buck Boost Configuration

During low power mode, the EXTSUP functionality is

not available. The internal regulator operates as a Undervoltage Lockout and Overvoltage

shunt regulator powered from VIN and has a typical Protection

value of 7.5V. Current limit protection for VREG is

available in low power mode as well. The TPS43335-Q1/TPS43336-Q1 starts up at a VIN

voltage of 6.5V (min). Once it has started up, the

External P-Channel Drive (GC2) and Reverse device operates down to a VIN voltage of 3.6V, below

Battery Protection this voltage level the undervoltage lockout will disable

the device. A voltage of 46V at VIN triggers the

The TPS43335-Q1/TPS43336-Q1 includes a gate overvoltage comparator which shuts down the device.

driver for an external P-channel MOSFET which can In order to prevent that transient spikes shutting down

be connected across the rectifier diode of the boost the device, the under and overvoltage protection

regulator. This is useful to reduce power losses when have filter times of 5µs (typical).

the boost controller is not switching. The gate driver

provides a swing of 6V typical below the VIN voltage When the voltages return to the normal operating

in order to drive a P-channel MOSFET. When VBAT region, the enabled switching regulators start

falls below the boost enable threshold, the gate driver including a new soft-start ramp for the buck

turns off the P-channel MOSFET and the diode is no regulators.

longer bypassed. When the boost controller is enabled, a voltage less

The gate driver can also be used to bypass any than 1.9V (typical) on VBAT triggers an undervoltage

additional protection diodes connected in series as lockout and pulls the boost gate driver (GC1) low. As

shown in Figure 23.Figure 24 also shows a different a result VIN will fall at a rate dependent on its

capacitor and load, eventually triggering VIN

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

undervoltage. A short falling transient at VBAT even Thermal Protection

lower than 2V can thus be survived, if VBAT returns The TPS43335-Q1/TPS43336-Q1 protects itself from

to higher than 2.5V before VIN is discharged to the overheating using an internal thermal shutdown

undervoltage threshold. This detection has a filter circuit. If the die temperature exceeds the thermal

delay of 5µsec typical. shutdown threshold of 165 degrees Celsius due to

excessive power dissipation (e.g.: Due to fault

conditions such as a short circuit at the gate drivers

or VREG), the controllers are turned off and restarted

when the temperature has fallen by 15 degrees.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

COMPx

VIN

VREF

10 V

12 V

C 1

C 2

RESR

OTA-gmEA

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

APPLICATION INFORMATION

The following example illustrates the design process and component selection for the TPS43335-Q1. The design

goal parameters are given in Table 3.

Table 3.

PARAMETER VBUCK A VBUCK B BOOST

VIN 6 V to 30 V VIN 6 V to 30 V VBAT - 5 V (cranking

Input voltage 12 V - typ 12 V - typ pulse input) to 30V

Output voltage, VO5 V 3.3 V 10 V

Max - output current, IO3 A 2 A 2.5 A

Load step output tolerance, ∆VO±0.2 V ±0.12 V ±0.5 V

Current output load step, ∆IO0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A

Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

This is a starting point and theoretical representation of the values to be used for the application, further

optimization of the components derived may be required to improve the performance of the device.

Boost Component Selection

A Boost converter operating in continuous conduction

mode (CCM) has a right-half-plane (RHP) zero in its

transfer function. The RHP zero is inversely related to

the load current and inductor value and directly

related to the input voltage. The RHP zero limits the

maximum bandwidth achievable for the boost

regulator. If the bandwidth is too close to the RHP

zero frequency, the regulator may become unstable.

Thus, for high power systems with low input voltages,

a low inductor value is chosen. This increases the

amplitude of the ripple currents in the N-channel

MOSFET, the inductor and the capacitors for the

boost regulator. They must be designed with the

ripple/RHP zero trade-off in mind and considering the Figure 25. Boost Compensation Components

power dissipation effects in the components due to

parasitic series resistance. This design is done assuming continuous conduction

mode. During light load conditions, the boost

A boost converter that operates in the discontinuous converter will operate in discontinuous mode without

mode does not contain the RHP-zero in its transfer affecting stability. Hence the assumptions here cover

function. However, this needs an even lower inductor the worst case for stability.

value and has high ripple currents. Also, it must be

ensured that the regulator never enters the

continuous conduction mode otherwise it may Boost Maximum Input Current IIN_MAX

become unstable. The maximum input current is drawn at the minimum

input voltage and maximum load. the efficiency for

VBAT = 5V at 2.5A is 80% based on the typical

characteristics plot

Hence,

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

max max

54.9 H

2 2.52 2 200

BAT ON BAT

IN IN SW

V T V V

I I f A kHz m

= = =

* * * *

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

Boost Inductor Selection, L

Allow input ripple current of 40% of IIN max at

VBAT =5V

Choose a lower value of 4 µH in order to ensure a

high RHP-zero frequency while making a compromise

that expects a high current ripple. Also, this can make

the boost converter operate in discontinuous

conduction mode where it is easier to compensate.

The inductor saturation current needs to be higher

than the peak inductor current and some percentage

higher than the maximum current limit value set by

the external sensing resistive element. Select CO= 660 µF.

This rating should be determined at the minimum This capacitor is usually aluminum electrolytic with

input voltage, maximum output current and maximum ESR in the 10s of mΩ. This is good for loop stability

core temperature for the application since it provides a phase boost due to the ESR. The

output filter components LC create a double pole

Inductor Ripple Current, IRIPPLE (180 degree phase shift) at a frequency fLC and the

ESR of the output capacitor RESR creates a “zero“for

Based on an Inductor value of 4 µH, the ripple current the modulator at frequency fESR. These frequencies

is approximately 3.1 A. can be determined by the following;

Peak Current in Low Side FET, IPEAK

Based on this peak current value the external current

sense resistor RSENSE is calculated.

Select 20 mΩallowing for tolerance

The filter component values RIFLT and CIFLT for

current sense are 1.5 kΩand 1 nF respectively. This This satisfies fLC ≤0.1 fRHP .

allows for good noise immunity.

Bandwidth of Boost Converter, fC

Right Half Plane Zero RHP Frequency, fRHP Use the following guidelines to set the frequency

poles, zeroes and crossover values for trade off

between stability and transient response:

fLC <fESR<fC<fRHP Zero

spacer fC<fRHP Zero / 3

spacer fC<fSW / 6

Output Capacitor, COfLC <fC/ 3

To ensure stability, the output capacitor COis chosen

such that

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

10 20

3 5.9

85 10

10 10

1 33

2 3 2 8 5.9

1 33

2 265

200

2 3 1 ( ) 1 2 5.9 33 ( ) 1

2 2

R k

C nF

f R kHz k

C nF

C pF

f kHz

R C k nF

p p

= = W

* *

= = =

* * * * W

= = =

* * * - * W * * -

416

ESR

RIPPLE

ESR RIPPLE

f C

V mV

V I R mV

= =

* *

D * =

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

Output Ripple Voltage Due to Load Output Schottky Diode D1 Selection

Transients, ∆VOA schottky diode with low forward conducting voltage

VFover temperature and fast switching

characteristics is required to maximize efficiency. The

reverse breakdown voltage should be higher than the

maximum input voltage and the component should

have low reverse leakage current. Additionally the

peak forward current should be higher than the peak

inductor current The power dissipation in the Schottky

Since the boost converter is active only during brief diode is given by :

events such as a cranking pulse and the buck

converters are high-voltage tolerant, a higher

excursion on the boost output may be tolerable in

some cases. In such cases, smaller component

choices for the boost output may be used. Since this is activated for low input voltage profile

related to crank pulse the duration is less than 25ms

Selection of Components for Type II

Compensation Low-Side MOSFET (BOT_SW3)

The required loop gain for unity gain bandwidth

(UGB) is

The times trand tfdenote the rising and falling times

of the switching node and are related to the gate

driver strength of the TPS43335-Q1/TPS43336-Q1

and gate Miller capacitance of the MOSFET. The first

term denotes the conduction losses which are

minimized when the on-resistance of the MOSFET is

The boost converter error amplifier (OTA) has a Gm low. The second term denotes the transition losses

that is proportional to the VBAT voltage. This allows a which arise due to the full application of the input

constant loop response across the input voltage voltage across the drain-source of the MOSFET as it

range and makes it easier to compensate by turns on or off. They are higher at high output

removing the dependency on VBAT.currents and low input voltages (due to the large input

peak current) and when the switching time is low.

Note: The on resistance RDS(ON) has a positive

temperature coefficient which produces the

(TC=d*DeltaT) term that signifies the temperature

dependence.( Temperature coefficient d is available

as a normalized value from MOSFET data sheets

and can be assumed to be 0.005/degrees Celsius as

a starting value)

BUCKA Component Selection

Input Capacitor, CIMinimum ON Time, tON min

The input ripple required is lower than 50 mV.

This is higher than the min duty cycle specified (100

ns typ). Hence the minimum duty cycle is achievable

Therefore our recommendation is 330µF with at this frequency.

10mOhm ESR.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

Vref

RLCOMP

VSENSE

Type2A

gmea

RESR

2 * * * 2 * 50 * 5 * 100

3 23.57

* * * *

C O O

REF REF

CFB CFB

f V C kHz F

R k

gm K V gm K V

p p m

= = = W

10 10

1 1.35

2 * 3 * 2 * 24 * 50

C nF

R f k kHz

p p

= = =

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

Current Sense Resistor RSENSE Selection of Components for Type II

Compensation

Based on the typical characteristics for VSENSE limit

with VIN versus duty cycle, the sense limit is

approximately 65 mV (at VIN = 12V and duty cycle of

5V/12V = 0.416). Allowing for tolerances and ripple

currents choose VSENSE max of 50mV.

Select 15 mΩ

Inductor Selection L Figure 26. Buck Compensation Components

As explained in the description of the buck

controllers, for optimal slope compensation and loop

response, the inductor should be chosen such that:

Use standard value of R3 = 24 kΩ

Where; VO= 5V, CO= 100uF, gm = 1ms, VREF = 0.8V

KFLR = Coil selection constant = 200 KCFB = 0.125 / RSENSE = 8.33 (0.125 is an internal

Choose a standard value of 8.2µH. For the buck constant)

converter, the inductor saturation currents and core

should be chosen to sustain the maximum currents.

Inductor Ripple Current IRIPPLE Use standard value of 1.5 nF

At nominal input voltage of 12V, this gives a ripple

current of 30% of IO max ≈1A.

Output Capacitor CO The resulting bandwidth of Buck Converter fC

Select an output capacitance COof 100µF with low

ESR in the range of 10mΩ. This give ∆VO(Ripple) ≈

15mV and ∆V drop of ≈180 mV during a load step,

which will not trigger the power good comparator and

is within the required limits.

Bandwidth of Buck Converter fCThis is close to the target bandwidth of 50 kHz

Use the following guidelines to set frequency poles, The resulting zero frequency fZ1

zeroes and cross over values for trade off between

stability and transient response

•Crossover frequency fCbetween fSW/6 and fSW/10

Assume fC= 50kHz This is close to the fC/10 guideline of 5 kHz

•Select the zero fz≈fC/10 The second pole frequency fP2

•Make the second pole fP2 ≈fSW/2

spacer

spacer This is close to the fSW/2 guideline of 200 kHz. Hence

all requirements for a good loop response are

spacer satisfied.

spacer

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

10 10

1 1.2

2 * 3 * 2 * 30 * 50C

C nF

R f k kHzp p

= = =

2 * 3 * 1* ( 2

1.2 33

400

2 * 30 *1.2 * ( 2

) 1

R C

nF pF

kHz

k nF

= =

* 3* *

2 *

1 * 20 * 4.16 * 0.8 48

2 *100 * 3.3

CFB REF

O O

gm R K V

fC V

ms k

f kHz

p m

= =

416

1 1 4.4

2 * 3 * 1 2 * 30 *1.2

Zf kHz

R C k nFp p

= = =

1 1

2 * 3 * 2 2 * 30 * 33

160

p p

= =PfR C k pF kHz

2 * * *

* *

2 * 50 * 3.3*100

1 * 4.16 * 0.8

C O O

CFB REF

f V C

Rgm K V

kHz F

ms k

p m

= = W

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

Resistor Divider Selection for setting VO

Voltage

Choose divider current through R1 and R2 to be 50

µA. Then

And

Therefore, R2 = 16 kΩand R1 = 84 kΩ

BUCKB Component Selection

Using the same method as VBUCKA, the following This close to the target bandwidth of 50 kHz

parameters and components are realized The resulting zero frequency fZ1

This is higher than the min duty cycle specified (100 This close to the fCguideline of 5kHz

ns typ) The second pole frequency fP2

This close to the fSW/2 guideline of 200 kHz

Hence all requirements for a good loop response are

∆Iripple current ≈0.4 A (approx.20% of IO max)satisfied

Select an output capacitance COof 100µF with low

ESR in the range of 10mΩ. This give ∆VO(Ripple) ≈Resistor Divider Selection for Setting VO

7.5mV and ∆V drop of ≈120 mV during a load step Voltage

Assume fC= 50kHz

Choose divider current through R1 and R2 to be 50

µA. Then

Use standard value of R3 = 30kΩAnd

Therefore, R2 = 16 kΩand R1 = 50 kΩ

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

2( )

( ) * (1 ) * ( ) * ( ) *

BuckTOPFET

I O

O DS ON r f SW

V I

I R TC D t t f

+ + +

2( )( ) (1 ) (1 ) (2 )

buckLOWERFET

O DS ON F O d SW

I R TC D V I t f

* + * - + * * * *

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

BUCKX High-Side and Low-Side N-Channel low. The second term denotes the transition losses

MOSFETs which arise due to the full application of the input

voltage across the drain-source of the MOSFET as it

The gate drive supply for these MOSFET is supplied turns on or off. They are lower at low currents and

by an internal supply which is 5.8V typical under when the switching time is low.

normal operating conditions. The output is a totem

pole allowing full voltage drive of VREG to the gate

with peak output current of 1.2 A. The High-Side

MOSFET is referenced to a floating node at the

phase terminal (PHx) and the Low-Side MOSFET is

referenced to power ground (PGx) terminal. For a

particular applications these MOSFET‘s should be

selected with consideration for the following

parameters Rds ON, gate charge Qg, drain to source In addition, during the dead time tdwhen both the

breakdown voltage BVDSS, Maximum DC current MOSFETs are off, the body diode of the low-side

IDC(max) and thermal resistance for the package. MOSFET conducts, increasing the losses. This is

The times trand tfdenote the rising and falling times denoted by the second term in the above equation.

of the switching node and are related to the gate Using external Schottky diodes in parallel to the

driver strength of the TPS43335-Q1/TPS43336-Q1 low-side MOSFETs of the buck converters helps to

and gate Miller capacitance of the MOSFET. The first reduce this loss.

term denotes the conduction losses which are Note: The RDS(ON) has a positive temperature

minimized when the on-resistance of the MOSFET is coefficient which is accounted for in the TC term for

RDS(ON). TC = d * delta T[°C]. The temperature

coefficient d is available as a normalized value from

MOSFET data sheets and can be assumed to be

0.005/degrees Celsius as a starting value

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

VBAT

TPS43335-Q1

TPS43336-Q1

2.5V to 40V

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC SYNC

DLYAB

AGND

PGB

SSB

COMPB

FBB

SB2

SB1

PGNDB

GB2

PHB

GB1

CBB

VREG

DIV

EXTSUP

VIN

3.9µH

0.1µF

1µF

10nF

1nF

5k5k

100µF

15µH

0.03Ω VBUCKB –3.3V, 6.6W

8.2µH

10µF 680µF

100µF

VBUCKA - 5V, 15W 0.015Ω

5.6k

33nF

270pF

24k

1.5nF33pF 20k 1.8nF 47pF

16k

50k

16k

84k

TOP-SW1

BOT-SW1 BOT-SW2

TOP-SW2

TOP-SW3

BOT-SW3

330µF

L2 L3

COUT2 COUT3

COUT1

0.02Ω

BOOST 10V, 25W

1.5k

1nF

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

Schematic

The following section summarize the previously calculated example and gives schematic + component proposals.

Table 3.

Table 4. Application Example 1

PARAMETER VBUCK A VBUCK B BOOST

VIN 6 V to 30 V VIN 6 V to 30 V VBAT - 5 V (cranking

Input voltage 12 V - typ 12 V - typ pulse input) to 30V

Output voltage, VO5 V 3.3 V 10 V

Max - output current, IO3 A 2 A 2.5 A

Load step output tolerance, ∆VO±0.2 V ±0.12 V ±0.5 V

Current output load step, ∆IO0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A

Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

Table 5. Application Example 1 - Component Proposals

Name Component Proposal Value

L1 MSS1278T-392NL (Coilcraft) 4µH

L2 MSS1278T-822ML (Coilcraft) 8.2µH

L3 MSS1278T-153ML (Coilcraft) 15µH

D1 SK103 (Micro Commercial Components)

TOP_SW3 IRF7416 (International Rectifier)

TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW3 IRFR3504ZTRPBF (International Rectifier)

COUT1 EEVFK1J681M (Panasonic) 680µF

COUT2,3 ECASD91A107M010K00 (Murata) 100µF

CIN EEEFK1V331P (Panasonic) 330µF

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

VBAT

TPS43335-Q1

TPS43336-Q1

5V to 30V

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC SYNC

DLYAB

AGND

PGB

SSB

COMPB

FBB

SB2

SB1

PGNDB

GB2

PHB

GB1

CBB

VREG

DIV

EXTSUP

VIN

3.9µH

0.1µF

1µF

10nf

10nF

1nF

5k5k

100uF

22uH

0.045Ω VBUCKB –2.5V, 2.5W

10uH

10µF 470µF

150µF

VBUCKA - 5V, 15W 0.015Ω

6.8k

24nF

220pF

39k

1nF20pF 36k 1nF 22pF

16k

34k

16k

84k

TOP-SW1

BOT-SW1 BOT-SW2

TOP-SW2

TOP-SW3

BOT-SW3

L2 L3

COUT2 COUT3

COUT1

0.03Ω

BOOST 10V, 20W

1.5k

470pF

330µF

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

Table 6. Application Example 2

PARAMETER VBUCK A VBUCK B BOOST

VIN 5 V to 30 V VIN 6 V to 30 V VBAT - 5 V (cranking

Input voltage 12 V - typ 12 V - typ pulse input) to 30V

Output voltage, VO5 V 2.5 V 10 V

Max - output current, IO3 A 1 A 2 A

Load step output tolerance, ∆VO±0.2 V ±0.12 V ±0.5 V

Current output load step, ∆IO0.1 A to 3 A 0.1 A to 1 A 0.1 A to 2 A

Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

Table 7. Application Example 2 - Component Proposals

Name Component Proposal Value

L1 MSS1278T-392NL (Coilcraft) 3.9µH

L2 MSS1278T-822ML (Coilcraft) 8.2µH

L3 MSS1278T-223ML (Coilcraft) 22µH

D1 SK103 (Micro Commercial Components)

TOP_SW3 IRF7416 (International Rectifier)

TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW3 IRFR3504ZTRPBF (International Rectifier)

COUT1 EEVFK1V471Q (Panasonic) 470µF

COUT2 ECASD91A157M010K00 (Murata) 150µF

COUT3 ECASD40J107M015K00 (Murata) 100µF

CIN EEEFK1V331P (Panasonic) 330µF

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

TPS43335-Q1

TPS43336-Q1

www.ti.com

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

Power Dissipation De-Rate Profile 32 pin HTTSOP package with power PAD

Figure 27. Power dissipation de rating profile based on high K Jedec PCB

PCB Layout Guidelines

Grounding and PCB Circuit Layout Considerations

Boost converter

1. The path formed from the input capacitor to the inductor and BOT_SW3 with low side current sense resistor

should have short leads and PC trace lengths. The same applies for the trace from the inductor to the

Schottky Diode D1 to the COUT1 capacitors. The negative terminal of the input capacitor and the negative

terminal of the sense resistor be connected together with short trace lengths.

2. The over current sensing shunt resistor may require noise filtering and this capacitor should be close to the

IC pin.

Buck Converter

1. Connect the drain of TOP_SW1 and TOP_SW2 together with positive terminal of the input capacitor COUT1.

The trace length between these terminals should be short.

2. Connect a local decoupling capacitor between Drain of TOP_SWx and Source of BOT_SWx.

3. The Kelvin current sensing for the shunt resistor should have minimum trace spacing and routed together.

Any filtering capacitors for noise should be placed near the IC pins.

4. The resistor divider for sensing output voltage is connected between the positive terminal of the respective

output capacitor and COUT2 or COUT3 and the IC signal ground. These components and the traces should

not be routed near any switching nodes or high current traces.

Other Considerations

1. PGNDx and AGND should be shorted to thermal pad. Use a star ground configuration if connecting to non

ground plane system. Use tie-ins for EXTSUP capacitor, compensation network ground and voltage sense

feedback ground networks to this start ground.

2. Connect compensation network between compensation pins and IC signal ground. Connect the oscillator

resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits should NOT be

located near the dv/dt nodes; these include the gate drive outputs, phase pins and boost circuits (bootstrap).

3. Reduce the surface area of the high current carrying loops to a minimum, by ensuring optimal component

placement. Ensure the bypass capacitors are located as close as possible to their respective power and

ground pins.

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

VBAT

GC1

GC2

CBA

GA1

PHA

GA2

PGNDA

SA1

SA2

FBA

COMPA

SSA

PGA

ENA

ENB

COMPC

ENC

V IN

EXTSUP

D IV

VREG

CBB

GB1

PHB

GB2

PGNDB

SB1

SB2

FBB

COMPB

SSB

PGB

AGND

DLYAB

SYNC

VBUCKA

VBUCKB

POW ER

INPUT

VBOOST

Exposed Pad

connec ted to GND

P lane

M ic rocon tro lle r

Powe r L ines

Connec tion to GND P lane o fPCB th rough v ias

Connec tion to top /bo ttom o f PCB th rough v ias

Vo ltage R a ilO u tpu ts

TPS43335-Q1

TPS43336-Q1

SLVSAV6A –JUNE 2011–REVISED NOVEMBER 2011

www.ti.com

PCB Layout

Product Folder Link(s): TPS43335-Q1 TPS43336-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 7-Dec-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TPS43335QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TPS43336QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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