74HC2G02DP,125 - NEXPERIA - Datasheet.Directory

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1. General description

The 74HC2G02; 74HCT2G02 is a dual 2-input NOR gate. Inputs include clamp diodes.

This enables the use of current limiting resistors to interface inputs to voltages in excess

of VCC.

2. Features and benefits

Wide supply voltage range from 2.0 V to 6.0 V

Input levels:

For 74HC2G02: CMOS level

For 74HCT2G02: TTL level

Symmetrical output impedance

High noise immunity

Low power dissipation

Balanced propagation delays

Multiple package options

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Specified from 40 C to +85 C and 40 C to +125 C

3. Ordering information

74HC2G02; 74HCT2G02

Dual 2-input NOR gate

Rev. 5 — 27 September 2013 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC2G02DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm SOT505-2

74HCT2G02DP

74HC2G02DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline p ackage; 8 leads;

body width 2.3 mm SOT765-1

74HCT2G02DC

74HC2G02GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;

8 terminals; body 3  2  0.5 mm SOT996-2

74HCT2G02GD

Product data sheet Rev. 5 — 27 September 2013 2 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

4. Marking

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

6. Pinning information

6.1 Pinning

Table 2. Marking code

Type number Marking code[1]

74HC2G02DP H02

74HCT2G02DP T02

74HC2G02DC H02

74HCT2G02DC T02

74HC2G02GD H02

74HCT2G02GD T02

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)

001aah780

1B 1Y

2B 2Y

001aah781

mna105

Fig 4. Pin configuration SOT505-2 (TSSOP8) and

SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8)

74HC2G02

74HCT2G02

1A VCC

1B 1Y

2Y 2B

GND 2A

001aak016

001aak017

74HC2G02

74HCT2G02

Transparent top view

GND

VCC

Product data sheet Rev. 5 — 27 September 2013 3 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

6.2 Pin description

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level.

8. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.

For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.

For XSON8 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.

Table 3. Pin description

Symbol Pin Description

1A, 2A 1, 5 data input

1B, 2B 2, 6 data input

GND 4 ground (0 V)

1Y, 2Y 7, 3 data output

VCC 8 supply voltage

Table 4. Function table[1]

Input Output

nA nB nY

LLH

LHL

HLL

HHL

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7.0 V

IIK input clamping current VI<0.5 V or VI>V

CC + 0.5 V [1] -20 mA

IOK output clamping current VO<0.5 V or VO>V

CC + 0.5 V [1] -20 mA

IOoutput current VO= 0.5 V to (VCC +0.5V) [1] -25mA

ICC supply current [1] -50mA

IGND ground current [1] 50 - mA

Tstg storage temperature 65 +150 C

PDdynamic power dissipation Tamb = 40 C to +125 C[2] - 300 mW

Product data sheet Rev. 5 — 27 September 2013 4 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

9. Recommended operating conditions

10. Static characteristics

Table 6. Recommended operating con ditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 74HC2G02 74HCT2G02 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 - VCC 0-V

CC V

VOoutput voltage 0 - VCC 0-V

CC V

Tamb ambient temperature 40 +25 +125 40 +25 +125 C

t/V input transition rise

and fall rate VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V - - 83 - - - ns/V

Table 7. Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

74HC2G02

VIH HIGH-level input

voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - V

VIL LOW-level input

voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 V

VOH HIGH-level output

voltage VI= VIH or VIL

IO= 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - V

IO= 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V

IO= 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - V

IO= 4.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V

IO= 5.2 mA; VCC = 6.0 V 5.63 5.81 - 5.2 - V

VOL LOW-level output

voltage VI= VIH or VIL

IO= 20 A; VCC = 2.0 V - 0 0.1 - 0.1 V

IO= 20 A; VCC = 4.5 V - 0 0.1 - 0.1 V

IO= 20 A; VCC = 6.0 V - 0 0.1 - 0.1 V

IO= 4.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V

IO= 5.2 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V

IIinput leakage current VI=V

CC or GND; VCC =6.0V - - 1.0 - 1.0 A

ICC supply current per input pin; VI=V

CC or GND;

IO=0A; V

CC =6.0V --10 - 20A

CIinput capacitance - 1.5 - - - pF

Product data sheet Rev. 5 — 27 September 2013 5 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

[1] All typical values are measured at Tamb = 25 C.

11. Dynamic characteristics

74HCT2G02

VIH HIGH-level input

voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V

VIL LOW-level input

voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V

VOH HIGH-level outp ut

voltage VI= VIH or VIL

IO= 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V

IO= 4.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V

VOL LOW-level output

voltage VI= VIH or VIL

IO= 20 A; VCC = 4.5 V - 0 0.1 - 0.1 V

IO= 4.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V

IIinput leakage current VI=V

CC or GND; VCC =5.5V - - 1.0 - 1.0 A

ICC supply current VI=V

CC or GND; IO=0A;

VCC =5.5V --10 - 20A

ICC additional supply

current per input; VCC = 4.5 V to 5.5 V;

VI=V

CC 2.1 V; IO=0A - - 375 - 410 A

CIinput capacitance - 1.5 - - - pF

Table 7. Static characteristics …continued

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); fo r test circuit see Figure 7.

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

74HC2G02

tpd propagation delay nA and nB to nY; see Figure 6 [2]

VCC = 2.0 V - 26 95 - 110 ns

VCC = 4.5 V - 9 19 - 22 ns

VCC = 5.0 V; CL = 15 pF - 9 - - - ns

VCC = 6.0 V - 8 16 - 20 ns

tttransition time see Figure 6 [3]

VCC = 2.0 V - 19 95 - 125 ns

VCC = 4.5 V - 7 19 - 25 ns

VCC = 6.0 V - 5 16 - 20 ns

CPD power dissipation

capacitance VI=GNDtoV

CC [4] -10- - -pF

Product data sheet Rev. 5 — 27 September 2013 6 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

[1] All typical values are measured at Tamb = 25 C.

[2] tpd is the same as tPLH and tPHL.

[3] tt is the same as tTLH and tTHL.

[4] CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CL  VCC2  fo) = sum of outputs.

12. Waveforms

74HCT2G02

tpd propagation delay nA and nB to nY; see Figure 6 [2]

VCC = 4.5 V - 12 24 - 29 ns

VCC = 5.0 V; CL = 15 pF - 12 - - - ns

tttransition time VCC = 4.5 V; see Figure 6 [3] -619-22ns

CPD power dissipation

capacitance VI=GNDtoV

CC 1.5 V [4] -10- - -pF

Table 8. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); fo r test circuit see Figure 7.

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 6. Propa gat io n de la y data input (nA, nB) to data output (nY) an d tran s itio n time outp ut (nY)

001aae759

PLH

PHL

90%

10%

nY output

nA, nB input

GND

TLH

THL

Table 9. Measurement points

Type Input Output

VMVM

74HC2G02 0.5  VCC 0.5  VCC

74HCT2G02 1.3 V 1.3 V

Product data sheet Rev. 5 — 27 September 2013 7 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

Test data is given in Table 10.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Fig 7. Load circuit for measuring switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aad983

DUT

VIVO

RLS1

open

Table 10. Test data

Type Input Load S1 position

VItr, tfCLRLtPHL, tPLH

74HC2G02 GND to VCC  6 ns 15 pF, 50 pF 1 kopen

74HCT2G02 GND to 3 V  6 ns 15 pF, 50 pF 1 kopen

Product data sheet Rev. 5 — 27 September 2013 8 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

13. Package outline

Fig 8. Package outline SOT505-2 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(1) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00 0.95

0.75 0.38

0.22 0.18

0.08 3.1

2.9 3.1

2.9 0.65 4.1

3.9 0.70

0.35 8°

0°

0.13 0.10.20.5

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

0.47

0.33

SOT505-2 - - - 02-01-16

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2

1.1

pin 1 index

Product data sheet Rev. 5 — 27 September 2013 9 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

Fig 9. Package outline SOT765-1 (VSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00 0.85

0.60 0.27

0.17 0.23

0.08 2.1

1.9 2.4

2.2 0.5 3.2

3.0 0.4

0.1 8°

0°

0.13 0.10.20.4

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.40

0.15

0.21

0.19

SOT765-1 MO-187 02-06-07

0.12

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1

pin 1 index

Product data sheet Rev. 5 — 27 September 2013 10 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

Fig 10. Package outline SOT996-2 (XSON8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT996-2

sot996-2_po

07-12-21

12-11-20

Unit(1)

mm max

nom

min 0.5 0.05

0.00

2.1

1.9

3.1

2.9

0.5

0.3

0.15

0.05

0.6

0.4

0.5 1.5 0.05

Dimensions (mm are the original dimensions)

XSON8: plastic extremely thin small outline package; no leads;

8 terminals; body 3 x 2 x 0.5 mm SOT996-2

A1b

0.35

0.15

DEee

1LL

1L2v

0.1

0.05

0.1

0 1 2 mm

scale

terminal 1

index area

B A

detail X

AA1

eAC B

vCw

Product data sheet Rev. 5 — 27 September 2013 11 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

14. Abbreviations

15. Revision history

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT2G02 v.5 20130927 Product data sheet - 74HC_HCT2G02 v.4

Modifications: •For type numbers 74HC2G02GD and 74HCT2G02GD XSON8U has changed to XSON8.

74HC_HCT2G02 v.4 20090511 Product data sheet - 74HC_HCT2G02 v.3

74HC_HCT2G02 v.3 20030514 Product data sheet - 74HC_HCT2G02 v.2

74HC_HCT2G02 v.2 20030203 Product specification - 74HC_HCT2G02 v.1

74HC_HCT2G02 v.1 20020710 Product specification - -

Product data sheet Rev. 5 — 27 September 2013 12 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

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Product data sheet Rev. 5 — 27 September 2013 13 of 14

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

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For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74HC2G02; 74HCT2G02

Dual 2-input NOR gate

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 September 2013

Document identifier: 74HC_HCT2G02

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

17 Contact information. . . . . . . . . . . . . . . . . . . . . 13

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14