LT8711
1
Rev A
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Micropower Synchronous
Multitopology Controller
with 42V Input Capability
The LT
®
8711 is a multitopology current mode PWM control-
ler that can easily be configured as a synchronous buck,
boost, SEPIC, ZETA or as a nonsynchronous buck-boost
converter. Its dual gate drive voltage inputs optimize gate
driver efficiency.
The 15µA no-load quiescent current with the output voltage
in regulation extends operating run time in battery powered
systems. Low ripple Burst Mode operation enables high
efficiency at very light loads while maintaining low output
voltage ripple. The LT8711's fixed switching frequency can
be set from 100kHz to 750kHz or can be synchronized to
an external clock.
The additional features include 100% duty cycle capability
when in buck mode, a topology selection pin and adjustable
soft-start. LT8711 is available in the 20-lead TSSOP and
20-lead 3mm×4mm QFN packages.
All registered trademarks and trademarks are the property of their respective owners.
400kHz 5V to 40V Input/12V Output Nonsynchronous Buck Boost
Efficiency vs Load Current
n Easily Configurable as a Synchronous Buck, Boost,
SEPIC, ZETA or Nonsynchronous Buck-Boost Converter
n Wide Input Range: 4.5V to 42V (VIN Can Operate
to 0V, when EXTVCC > 4.5V)
n Automatic Low Noise Burst Mode
®
Operation
n Low IQ in Burst Mode Operation (15μA Operating)
n Input Voltage Regulation for High Impedance Source
n 100% Duty Cycle in Dropout (Buck Mode)
n 2A Gate Drivers (BG and TG)
n Adjustable Soft-Start with One Capacitor
n Frequency Programmable from 100kHz to 750kHz
n Can Be Synchronized to External Clock
n Available in 20-Lead TSSOP and 20-Lead 3mm×4mm
QFN Packages
APPLICATIONS
n General Purpose DC/DC Conversion
n Automotive Systems
n Industrial Supplies
n Solar Panel Power Converter
BIAS
INTVEE
TG
BG
CSP
CSN
2.2µF
2.2µF
100pF
60.4k
110k
330nF
100pF
2.2nF
ISN
ISP
GND
EN/FBIN
EXTVCC
OPMODE
INTVCC
RT
SYNC
SS
VC
1M
4mΩ
69.8k
100µF ×2
16V, X7R
VOUT
12V,
3.5A (VIN >16V)
2.5A (9V < VIN < 16V)
1.5A (VIN < 9V)
10µF ×6
50V, X7R
VIN
5V TO
40V
LT8711
FB
VIN
VOUT
M1
D1 L1
4.7µH D2
M2
4mΩ
8711 TA01a
LOAD CURRENT (A)
0.001
0.01
0.1
1
4
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
LT8711
2
Rev A
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PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN Voltage ................................................ –0.3V to 42V
BIAS Voltage .............................................. –0.3V to 42V
EXTVCC Voltage ......................................... –0.3V to 42V
BG, TG Voltage ..................................................... Note 2
FB Voltage ................................................. –0.3V to 5.5V
VC Voltage ................................................ –0.3V to 2.5V
EN/FBIN Voltage ................. –0.3V to MAX(VIN, EXTVCC)
SYNC Voltage ........................................... –0.3V to 5.5V
OPMODE Voltage ...................................... –0.3V to 5.5V
INTVEE Voltage..................................................... Note 2
CSP Voltage ............................................... –0.3V to 42V
(Note 1)
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
EN/FBIN
FB
VC
SS
OPMODE
ISP
ISN
INTVEE
BIAS
TG
RT
SYNC
NC
CSP
CSN
EXTVCC
VIN
INTVCC
NC
BG
21
GND
20 19 18 17
7 8
TOP VIEW
21
GND
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 52°C/W, θJC = 6.8°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
9 10
6
5
4
3
2
1
11
12
13
14
15
16
VC
SS
OPMODE
ISP
ISN
INTVEE
CSP
CSN
EXTVCC
VIN
INTVCC
NC
FB
EN/FBIN
RT
SYNC
BIAS
TG
NC
BG
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8711EFE#PBF LT8711EFE#TRPBF LT8711 FE 20-Lead TSSOP –40°C to 125°C
LT8711IFE#PBF LT8711IFE#TRPBF LT8711 FE 20-Lead TSSOP –40°C to 125°C
LT8711EUDC#PBF LT8711EUDC#TRPBF LGQJ 20-Lead 3mm × 4mm QFN –40°C to 125°C
LT8711IUDC#PBF LT8711IUDC#TRPBF LGQJ 20-Lead 3mm × 4mm QFN –40°C to 125°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LT8711#orderinfo
CSN Voltage ........................... CSP – 0.3V to CSP+0.3V
ISP Voltage ..............................ISN – 0.3V to ISN + 0.3V
ISN Voltage ...............................................–0.3V to BIAS
INTVCC Voltage ......................................... –0.3V to 5.5V
RT Voltage ................................................ –0.3V to 5.5V
SS Voltage ............................................... –0.3V to 5.5V
Operating Junction Temperature Range
LT8711E ............................................. –40°C to 125°C
LT8711I .............................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
LT8711
3
Rev A
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ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage Range VEXTVCC = 0V
VEXTVCC = 4.5V
l
l
4.5
042
42 V
V
Quiescent Current in Normal Operation
(IVIN+IEXTVCC+IBIAS)VEN/FBIN = 2.5V, Not Switching 2.0 2.5 mA
Quiescent Current in Burst Mode Operation
(IVIN+IEXTVCC+IBIAS)VFB = VFB_REG + 3mV 15 25 µA
Quiescent Current in Shutdown
(IVIN+IEXTVCC+IBIAS)VEN/FBIN = 0V 1 2 µA
FB Output Regulation Voltage, VFB_REG l784
795 800
800 816
805 mV
mV
FB Line Regulation 4.5V ≤ VIN ≤ 42V 0.01 0.05 %/V
FB Pin Input Bias Current VFB = 0.8V l–50 0 50 nA
Error Amp Transconductance ∆I = ±5µA 250 µmhos
Error Amp Voltage Gain 90 dB
Maximum Current Sense Voltage,
VCSP – VCSN Minimum Duty Cycle
Maximum Duty Cycle
l
l
46
26 50
33 54
40 mV
mV
Switching Frequency, fOSC RT = 30.3k
RT = 247k
l
l
675
85 750
100 825
115 kHz
kHz
Switching Frequency Range Free-Running
Synchronizing
l
l
85
140 825
750 kHz
kHz
SYNC Input Voltage High l1.3 V
SYNC Input Voltage Low l0.4 V
SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V, fSYNC = 500kHz 20 80 %
Recommended SYNC Ratio fSYNC/fOSC 0.8 1.2
INTVCC Voltage IINTVCC = 10mA l4.75 5 5.25 V
INTVCC Line Regulation 6V ≤ VIN ≤ 42V, VEXTVCC = 0, IINTVCC=10mA
6V ≤ VEXTVCC ≤ 42V, VVIN = 0, IINTVCC=10mA –0.003
–0.003 –0.03
–0.03 %/V
%/V
INTVCC Load Regulation IINTVCC = 0mA to 40mA –1 –2 %
INTVCC Maximum External Load Current Internal Load Current = 40mA 10 mA
INTVCC Undervoltage Lockout INTVCC Rising
INTVCC Falling
l
l
3.9
3.45 4.1
3.6 4.3
3.75 V
V
INTVCC Undervoltage Lockout Hysteresis 500 mV
INTVEE Voltage, VBIAS – VINTVEE IINTVEE = 10mA l4.85 5.15 5.4 V
INTVEE Undervoltage Lockout, VBIAS – VINTVEE VBIAS – VINTVEE Rising
VBIAS – VINTVEE Falling
l
l
3.6
3.4 3.85
3.6 4.1
3.8 V
V
INTVEE Undervoltage Lockout Hysteresis,
VBIAS–VINTVEE
250 mV
BG Rise Time CBG = 3.3nF (Note 4) 14 ns
BG Fall Time CBG = 3.3nF (Note 4) 12 ns
TG Rise Time CTG = 3.3nF (Note 4) 11 ns
TG Fall Time CTG = 3.3nF (Note 4) 14 ns
BG and TG Non-Overlap Time TG Rising to BG Rising, CBG = CTG = 3.3nF (Note 4) 70 ns
BG and TG Non-Overlap Time BG Falling to TG Falling, CBG = CTG = 3.3nF (Note 4) 70 ns
Minimum On-Time CBG = CTG = 3.3nF 100 ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VBIAS = 12V, unless otherwise noted (Note 3).
LT8711
4
Rev A
For more information www.analog.com
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not apply a positive or negative voltage or current source to
BG, TG and INTVEE pins, otherwise permanent damage may occur.
Note 3: The LT8711E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the
–40°C to 125°C operating temperature range are assured by design,
PARAMETER CONDITIONS MIN TYP MAX UNITS
SS Charge Current VSS = 0V, Current Flows Out of SS pin l6 10 15 µA
SS Low Detection Voltage Part Exiting Undervoltage Lockout l65 85 105 mV
EN/FBIN Active Mode EN/FBIN Rising l1.28 1.35 1.42 V
EN/FBIN Chip Enable EN/FBIN Rising
EN/FBIN Falling
l
l
0.97
0.94 1.03
11.11
1.08 V
V
EN/FBIN Chip Enable Hysteresis 30 mV
EN/FBIN Input Voltage Low Shutdown Mode l0.2 V
EN/FBIN Current Limit Adjustment Voltage Full Current Limit
Near Zero Current Limit
l
l
1.12 1.27 V
V
EN/FBIN Pin Input Bias Current VEN/FBIN = 12V l–50 0 50 nA
EN/FBIN Amp Transconductance VFB = 0.6V 40 µmhos
EN/FBIN Amp Voltage Gain VFB = 0.6V 100 V/V
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VBIAS = 12V, unless otherwise noted (Note 3).
characterization and correlation with statistical process controls. The
LT8711I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation over the specified maximum operating junction
temperature may impair device reliability.
LT8711
5
Rev A
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TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Maximum Current Limit vs
Duty Cycle (CSP–CSN)
Maximum Current Limit vs SS
(CSP–CSN)
Output Voltage Regulation
(VFB_REG)
Input Voltage Regulation
(EN/FBIN) EN/FBIN Chip Enable Threshold EN/FBIN Active Mode Threshold
Input Voltage Regulation vs FB
(EN/FBIN) CSN Bias Current ISN Bias Current
DUTY CYCLE (%)
0
10
20
30
40
50
60
70
80
90
100
20
27
34
41
48
55
MAX CSP - CSN (mV)
8711 G01
SS (V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
0
10
20
30
40
50
60
MAX CSP – CSN (mV)
8711 G02
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
795
796
797
798
799
800
801
802
803
804
805
V
FB_REG
(mV)
8711 G03
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
EN/FBIN VOLTAGE (V)
8711 G04
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
EN/FBIN CHIP ENABLE (V)
8711 G05
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
1.330
1.335
1.340
1.345
1.350
1.355
1.360
1.365
1.370
EN/FBIN ACTIVE MODE (V)
8711 G06
FB (V)
0.60
0.65
0.70
0.75
0.80
0.85
0.90
1.0
1.1
1.2
1.3
1.4
1.5
1.6
EN/FBIN (V)
8711 G07
V
CSP
= V
CSN
= 12V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
60
80
100
120
140
160
180
CSN BIAS CURRENT (µA)
8711 G08
V
ISP
= V
ISN
=12V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
100
150
200
250
300
350
ISN BIAS CURRENT (µA)
8711 G09
LT8711
6
Rev A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
DCM Thresholds (ISP–ISN)
Oscillator Frequency vs
Temperature BG Transition Time vs Cap Load
TG Transition Time vs Cap Load Minimum Operating Input Voltage INTVCC vs Temperature
INTVCC UVLO vs Temperature
INTVCC Current Limit vs
VIN or EXTVCC
INTVCC Dropout from
VIN or EXTVCC
V
ISN
= 0V
V
ISN
= 12V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
ISP -ISN (mV)
8711 G10
R
T
= 30.3kΩ
R
T
= 247kΩ
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0
100
200
300
400
500
600
700
800
F
OSC
(kHz)
8711 G11
RISING
FALLING
CAP LOAD (nF)
0
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
60
BG TRANSITION TIME (ns)
8711 G12
RISING
FALLING
CAP LOAD (nF)
0
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
60
TG TRANSITION TIME (ns)
8711 G13
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
V
IN
OR V
EXTVCC
(V)
8711 G14
I
INTVCC
= 10mA
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
INTVCC (V)
8711 G15
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
INTVCC (V)
8711 G16
INPUT VOLTAGE (V)
5
10
15
20
25
30
35
40
0
10
20
30
40
50
60
70
INTVCC CURRENT LIMIT (mA)
8711 G17
INTVCC LOAD CURRENT (mA)
0
10
20
30
40
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
POWER INPUT - INTVCC (V)
8711 G18
LT8711
7
Rev A
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TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
INTVEE vs Temperature INTVEE UVLO vs Temperature INTVEE Current Limit vs BIAS
INTVEE Dropout (BIAS = 6V) IQ_BURST vs VIN or EXTVCC IQ_BURST vs Temperature
I
INTVEE
= 10mA
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
BIAS - INTVEE (V)
8711 G19
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
3.5
3.6
3.7
3.8
3.9
BIAS – INTVEE (V)
8711 G20
BIAS (V)
5
10
15
20
25
30
35
40
0
10
20
30
40
50
60
70
80
INTVEE CURRENT LIMIT (mA)
8711 G21
BIAS = 6V
INTVEE LOAD CURRENT (mA)
0
10
20
30
40
50
60
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
INTVEE (V)
8711 G22
INPUT VOLTAGE (V)
5
10
15
20
25
30
35
40
10
12
14
16
18
20
IQ_BURST (µA)
8711 G23
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
10.00
12.00
14.00
16.00
18.00
20.00
IQ_BURST (µA)
8711 G24
LT8711
8
Rev A
For more information www.analog.com
PIN FUNCTIONS
EN/FBIN (Pin 1/Pin 19): Enable and Input Voltage Regu-
lation Pin. In conjunction with the UVLO (undervoltage
lockout) circuit, this pin is used to enable/disable the chip
and restart the soft-start sequence. The EN/FBIN pin is
also used to limit the switching regulator current to avoid
collapsing the input supply. Drive below 0.2V to disable the
chip with very low quiescent current. Drive above 1.03V
(typical) to activate the chip. The commanded input cur-
rent will adjust when the EN/FBIN pin voltage is between
1.12V and 1.27V. Drive above 1.35V (typical) to activate
switching with no reduction in input current and restart the
soft-start sequence. See the Block Diagram and Applica-
tions section for more information. Do not float this pin.
FB (Pin 2/Pin 20): Feedback Input Pin. The LT8711 regu-
lates the FB pin to 0.8V. Connect the feedback resistor
divider tap to this pin.
VC (Pin 3/Pin 1): Error Amplifier Output Pin. Tie external
compensation network to this pin.
SS (Pin 4/Pin 2): Soft Start Pin. Place a soft-start capaci-
tor here. Upon start-up, the SS pin will be charged by a
410k resistor to about 4.3V. During an overtemperature
or UVLO condition, the SS pin will be quickly discharged
to reset the part. Once those conditions are clear, the part
will attempt to restart.
OPMODE (Pin 5/Pin 3): Topology Selection Pin. Tie this
pin to ground to select buck/ZETA mode. Tie to INTVCC
to select SEPIC/boost mode. Tie to a 100pF capacitor to
GND to select nonsynchronous buck-boost mode.
ISP & ISN (Pins 6 & 7/ Pins 4 & 5): Current Sense Posi-
tive and Negative Input Pins respectively. Kelvin connect
ISP and ISN pins to a sense resistor.
INTVEE (Pin 8/Pin 6): 5V Below BIAS LDO Regulator Pin.
Must be locally bypassed with a minimum capacitance
of 2.2µF to BIAS. This pin sets the bottom rail for the TG
gate driver. The TG gate driver can begin switching when
BIAS – INTVEE exceeds 3.6V (typical).
BIAS (Pin 9/Pin 7): Power Supply for the TG PFET Driver.
Must be locally bypassed with a minimum capacitance of
2.2µF to INTVEE. The BIAS pin sets the top rail for the TG
gate driver.
TG (Pin 10/Pin 8): PFET Gate Drive Pin. Low and high
levels are INTVEE and BIAS respectively with a 2A drive
capability.
BG (Pin 11/Pin 10): NFET Gate Drive Pin. Low and high
levels are GND and INTVCC respectively with a 2A drive
capability.
NC (Pin 12/Pin 9): No Connection. Do not connect. Must
be floated.
INTVCC (Pin 13/Pin 12): 5V Dual Input LDO Regulator Pin.
Must be locally bypassed with a minimum capacitance of
2.2µF to GND. Logic will choose to run INTVCC from the
VIN or EXTVCC pins. A maximum 10mA external load can
connect to the INTVCC pin. The undervoltage lockout on
INTVCC is 3.6V (typical). The BG gate driver can begin
switching when INTVCC exceeds 4.1V (typical).
VIN (Pin 14/Pin 13): Input Supply Pin. Must be locally
bypassed. Can run down to 0V as long as EXTVCC > 4.5V.
EXTVCC (Pin 15/Pin 14): Alternate Input Supply Pin.
Must be locally bypassed. Can run down to 0V as long
as VIN>4.5V.
CSN & CSP (Pins 16 & 17/ Pins 15 & 16): Current Sense
Negative and Positive Input Pins Respectively. Kelvin
connect CSN and CSP pins to a sense resistor to limit
the input current. The maximum sense voltage at low
duty cycle is 50mV.
NC (Pin 18/Pin 11): No Connection. Do not connect. Must
be floated.
SYNC (Pin 19/Pin 17): To synchronize the switching
frequency to an outside clock, simply drive this pin with
a clock. The high voltage level of the clock must exceed
1.3V, and the low level must be less than 0.4V. Drive this
pin to less than 0.4V to revert to the internal free running
clock. See the Applications Information section for more
information.
RT (Pin 20/Pin 18): Timing Resistor Pin. Adjusts the
LT8711’s switching frequency. Place a resistor from this
pin to ground to set the frequency to a fixed free running
level. Do not float this pin.
GND (Pin 21/Pin 21): Ground. Must be soldered directly
to the local ground plane.
(TSSOP/QFN)
LT8711
9
Rev A
For more information www.analog.com
BLOCK DIAGRAM
+
–
BUCK/ZETA
BOOST/SEPIC
BUCK-BOOST
IREC ×
RSENSE
REV
COMP
EXTVCC
INTVCC
EN/FBIN
OPMODE
SYNC
RT
410k R CHARGEQUICK DISCHARGE
SS_L
SS_L
CSIS
IS
CLK
W3 W4
Q1
PNP
+
–
+
–
8711 BD
BIAS
BIAS
VC
SS
INTVCC
CSP
CSN
ISP
ISN
+
–
FB
TG
BG
VIN
VIN
VOUT
INTVEE
DRIVER
DRIVER
M2
PFET
M1
NFET
UVLO LDO
UVLO
LDO
LDO LOGIC
LEVEL
SHIFT
1.215V
REF
QR
S
RAMP
GENERATOR
SYNC
BLOCK
LOGIC
START-UP
AND
FAULT
LOGIC
CURRENT
SENSE
PROCESSOR
MODE
DETECTION
ADJUSTABLE
OSCILLATOR
L1 RSENSE
RFB1
RFB2 COUT
CIN
CINTVEE
VOUT
0.88V
+
–
0.88V
+
–
85mV
+
–
+
–
+
–
0.8V1.2V
EN/FBIN
+
–
1.35V
D2
D1
D6 D4
+
–
DIE
TEMP
165°C
PWM
COMP
DISABLE
DRIVER
RIN1
RIN2
CSS CCCF
RC
RT
A1
A2
EA2 EA1
CINTVCC
ISW × RSENSE
LT8711
10
Rev A
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START-UP AND FAULT SEQUENCE
8711 F01
BEGIN SWITCHING
• NFET BEGINS SWITCHING
• PFET BEGINS SWITCHING
WHEN INTVEE REGULATOR
IS OUT OF UVLO
• NO RESET CONDITIONS
DETECTED
INITIALIZE
• SS PULLED LOW
• INTVCC CHARGES UP
RESET OVER
• SS DISCHARGES QUICKLY
• SWITCHER DISABLED
RESET DETECTED
ACTIVE MODE
RESET
RESET
RESET
• SS CHARGES UP
CHIP OFF
EN/FBIN < 1.0V (TYP) OR
VIN AND EXTVCC < 4.5V OR
TJUNCTION > 165°C
• ALL SWITCHES OFF
EN/FBIN > 1.35V(TYP) AND
INTVCC > 4.1V (TYP) AND
BIAS–INTVEE > 3.85V (TYP)
(BUCK/BUCK-BOOST/ZETA)
SS < 50mV
RESET = UVLO ON VIN OR EXTVCC (<4.5V MAX)
UVLO ON INTVCC (<3.6V TYP)
UVLO ON INTVEE (BUCK/BUCK-BOOST/ZETA) (<3.6V TYP)
EN/FBIN < 1.35V (TYP) AT 1ST POWER-UP
EN/FBIN < 1.00V (TYP) AFTER ACTIVE MODE SET
STATUS CHANGE ON OPMODE PIN
OVERTEMPERATURE (TJ > 165°C)
EN/FBIN > 1.0V (TYP) AND
VIN OR EXTVCC > 4.5V AND
TJUNCTION < 160°C
Figure1. State Diagram
LT8711
11
Rev A
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OPERATION
OPERATION—OVERVIEW
The LT8711 uses a constant frequency, current mode con-
trol scheme to provide excellent line and load regulation.
The part’s undervoltage lockout (UVLO) function, together
with soft-start, offers a controlled means of starting up.
Output voltage and input voltage have control over the
commanded peak current which allows a wide range of
applications to be built using the LT8711. Synchronous
switching makes high efficiency and high output cur-
rent applications possible. When operating at light load
condition, the LT8711 will enter burst mode to minimize
switching loss. Refer to the Block Diagram and the State
Diagram (Figure1) for the following description of the
part’s operation.
OPERATION—TOPOLOGY SELECTING
The 8711 can be configured as a synchronous buck, boost,
SEPIC, ZETA or nonsynchronous buck-boost converter by
configuration of the OPMODE pin.
When the OPMODE pin is connected to GND, the controller
operates in buck/ZETA mode.
When the OPMODE pin is connected to the INTVCC pin,
the controller operates in SEPIC/boost mode.
When the OPMODE pin is tied to a 100pF capacitor to
GND, the controller operates in nonsynchronous buck-
boost mode.
OPERATION—START-UP
Several functions are provided to enable a very clean
start-up of the LT8711.
Precise Turn-On Voltages
The EN/FBIN pin has two voltage levels for activating the
part: one that enables the part and allows internal rails
to operate and a 2nd voltage threshold which activates
a soft-start cycle and switching can begin. To enable the
part, take the EN/FBIN pin above 1.03V (typical). This
comparator has 50mV of hysteresis to protect against
glitches and slow ramping. To activate a soft-start cycle
and allow switching, take EN/FBIN above 1.35V (typical).
When EN/FBIN exceeds 1.35V (typical), the logic state is
latched so that if EN/FBIN drops between 1.03V to 1.35V
(typical), the SS pin is not pulled low by the EN/FBIN pin.
The EN/FBIN pin is also used for input voltage regulation
which is at 1.200V (typical). Input voltage regulation is
explained in more detail in the Operation—Regulation
section. Taking the EN/FBIN pin below 0.2V shuts down
the chip, resulting in extremely low quiescent current.
See Figure2 that illustrates the different EN/FBIN voltage
thresholds.
8711 F03
ACTIVE MODE THRESHOLD
(TOLERANCE)
NORMAL OPERATION IF ACTIVE MODE SET
INPUT VOLTAGE REGULATION
(ONLY IF ACTIVE MODE SET)
EN/FBIN (V)
CHIP ENABLE THRESHOLD
(HYSTERSIS AND TOLERANCE)
LOCKOUT
(SWITCH OFF, SS CAP DISCHARGED, INTVCC AND
INTVEE DISABLED)
SHUTDOWN
(LOW QUIESCENT CURRENT)
SWITCH OFF, INTVCC AND INTVEE ENABLED, SS CAP
DISCHARGED IF ACTIVE MODE NOT SET
ACTIVE MODE
(NORMAL OPERATION)
(MODE LATCHED UNTIL EN/FBIN DROPS BELOW
CHIP ENABLE TRESHOLD)
1.42V
1.28V
1.27V
1.12V
1.11V
0.94V
0.2V
0V
Figure2. EN/FBIN Modes of Operation
Undervoltage Lockout (UVLO)
The LT8711 has internal UVLO circuitry that disables the chip
when the greater of VIN or EXTVCC < 3.6V (typical). The EN/
FBIN pin can also be used to create a configurable UVLO.
Soft-Start of Switch Current
The soft-start circuitry provides for a gradual ramp-up of
the switch current (refer to Max Current Limit vs SS in
Typical Performance Characteristics). When the part is
brought out of shutdown, the external SS capacitor is first
discharged which resets the states of the logic circuits in
the chip. Once the chip is in active mode, an integrated
410k resistor pulls the SS pin to ~4.3V at a ramp rate set
by the external capacitor connected to the pin. Typical
values for the soft-start capacitor range from 100nF to 1μF.
LT8711
12
Rev A
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OPERATION—REGULATION
Use the Block Diagram when stepping through the follow-
ing description of the LT8711 operating in regulation. The
LT8711 has two modes of regulation:
1. Output Voltage (via FB pin)
2. Input Voltage (via EN/FBIN pin)
Both of these regulation loops control the peak com-
manded current. At the start of each oscillator cycle, the
SR latch is set, which first turns off the external rectifier
switch (NFET in Block Diagram), and then turns on the
external main switch (PFET in Block Diagram). The PFET’s
current flows through an external current sense resistor
(RSENSE) generating a voltage proportional to the PFET
switch current. This voltage is then amplified by A1 and
added to a stabilizing ramp. The resulting sum is fed into
the positive terminal of the PWM comparator. When the
voltage on the positive input of the PWM comparator ex-
ceeds the voltage on the negative input (VC pin), the SR
latch is reset, turning off the PFET and then turning on the
NFET. The voltage on the VC pin is controlled by one of the
regulation loops, or a combination of regulation loops.
Slope compensation provides stability in constant fre-
quency current mode control architectures by preventing
subharmonic oscillations at high duty cycles. This is ac-
complished internally by adding a compensating ramp to
the positive terminal of the PWM comparator.
Output Voltage Regulation
The error amplifier servos the VC node by comparing the
voltage on the FB pin with an internal 0.800V reference.
When the load current increases it causes a reduction in
the feedback voltage relative to the reference causing the
error amplifier to raise the VC voltage. In this manner, the
FB error amplifier sets the correct peak current level to
maintain output voltage regulation.
Input Voltage Regulation
A resistor divider from the converter’s input voltage to
the EN/FBIN pin sets the input voltage regulation point.
The EN/FBIN pin voltage connects to the positive input of
amplifier EA2. The VC pin voltage is set by EA2, which is
the amplified difference between the EN/FBIN pin voltage
and an internal 1.200V reference voltage. In this manner,
the EN/FBIN error amplifier sets the correct peak current
level to maintain input voltage regulation.
OPERATION—RESET CONDITIONS
The LT8711 has three reset cases. When the part is in reset,
the SS pin is pulled low and both power switches, NFET
and PFET, are forced off. Once all of the reset conditions
are gone, the part is allowed to begin a soft-start sequence
and switching can commence. Each of the following events
can cause the LT8711 to be in reset:
1. UVLO
a. The greater of VIN and EXTVCC is<4.5V (maximum)
b. UVLO on INTVCC. INTVCC < 3.6V (typical)
c. UVLO on INTVEE. VBIAS – VINTVEE < 3.6V (typical)
unless BOOST/SEPIC topology is selected
d. EN/FBIN < 1.35V (typical) at first power-up
e. EN/FBIN < 1.00V (typical) after active mode set
2. OPMODE pin status changes
3. Die Temperature > 165°C
OPERATION—POWER SWITCH CONTROL
The external PFET and NFET switches are never on at the
same time (except buck-boost mode), and there is a non-
overlap time of about 100ns to prevent cross conduction.
OPERATION
LT8711
13
Rev A
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Light Load Operation Modes
The SYNC pin can be used to tell the LT8711 to operate
in FCM regardless of load current, or operate in DCM and
Burst Mode at light loads.
SYNC = logic high: FCM
SYNC = logic low: DCM or Burst Mode operation
If a clock is applied to the SYNC pin the part will synchronize
to an external clock frequency and operate in FCM mode.
OPERATION—AUTOMATIC LOW NOISE Burst Mode
OPERATION
At no load or very light load condition, high FB voltage
causes VC to decrease. When VC voltage is lower than a
threshold voltage, the controller operates in Burst Mode
to minimize switching loss. Between bursts, all circuitry
associated with controlling the output switch is shut
down, reducing the average input supply current to 15μA
in a typical application. Low standby power and higher
conversion efficiency is thus achieved. To optimize the
quiescent current performance at light loads, the current
in the feedback resistor divider must be minimized as it
appears to the output as load current.
OPERATION—LDO REGULATORS (INTVCC AND INTVEE)
The INTVCC LDO regulates at 5.0V (typical) and is used
as the top rail for the BG gate driver. The INTVCC LDO can
run from VIN or EXTVCC and will intelligently select to run
from the best rail to minimize power loss in the chip, but
at the same time, select the proper input for maintaining
INTVCC as close to 5.0V as possible. The INTVCC regulator
also has safety features to limit the power dissipation in
the internal pass device and also to prevent it from damage
if the pin is shorted to ground. The UVLO threshold on
INTVCC is 3.6V (typical), and the LT8711 will be in reset
until the LDO comes out of UVLO.
The INTVEE regulator regulates to 5.15V (typical) below
the BIAS pin voltage. The BIAS and INTVEE voltages are
used for the top and bottom rails of the TG gate driver
respectively. Just like the INTVCC regulator, the INTVEE
regulator has a safety feature to limit the power dissipation
in the internal pass device. The TG pin can begin switching
only after the INTVEE regulator comes out of UVLO (3.85V
typical across the BIAS and INTVEE pins). When the INTVEE
regulator is in UVLO, for the boost and SEPIC topologies,
the bottom switch is allowed to switch. The output current
would flow through the body diode of the PFET. To protect
the PFET from thermal damage under this condition, the
maximum commanded current is folded back to 27mV
(typical) across the CSP-CSN pins.
OPERATION
LT8711
14
Rev A
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BUCK CONVERTER COMPONENT SELECTION
The LT8711 can be configured as a buck converter as in
Figure3.
For a desired output current and output voltage over a
given input voltage range, Table 1 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a buck converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 1.
Variable Definitions:
VIN(MIN) = Minimum Input Voltage
VIN(MAX) = Maximum Input Voltage
VOUT = Output Voltage
IOUT = Output Current of Converter
f = Switching Frequency
DCMAX = Power Switch Duty Cycle at VIN(MIN)
VCSPN = Current Limit Voltage at DCMAX
APPLICATIONS INFORMATION
Table1. Buck Design Equations
Parameters/Equations
Step 1: Inputs Pick VIN, VOUT, IOUT, and f to calculate equations
below.
Step 2: DCMAX
DCMAX ≅
V
OUT
V
IN MIN
( )
Step 3: VCSPN See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find VCSPN at DCMAX.
Step 4: RSENSE
RSENSE ≤0.75 •
V
CSPN
IOUT
Step 5: L
LTYP =
RSENSE • VIN MIN
( )
– VOUT
( )
12.5m • f •VOUT
VIN MIN
( )
LMIN =
RSENSE • VIN MIN
()
40m • f •2VOUT – VIN MIN
()
V
OUT
LMAX =
RSENSE • VIN MIN
()
– VOUT
( )
2.5m • f •VOUT
VIN MIN
()
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
LTYP and LMIN.
Step 6: COUT
COUT ≥1– DCMIN
8 •L • f2• 0.005
Step 7: CIN
CIN ≥
I
OUT
•DC
MAX
f • ∆V
IN
∆VIN is acceptable maximum input ripple voltage.
Step 8: RFB1/RFB2
RFB1 =VOUT
0.8V – 1
⎛
⎝
⎜⎞
⎠
⎟•RFB2
Step 9: RT
RT=25000
f
– 2: f is in kHz and RT is in kΩ
NOTE: The final values for COUT and CIN may deviate from the above
equations in order to obtain desired load transient performance for a
particular application. The COUT and CIN equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
Figure3. Buck Converter—The Component Values Given Are
Typical Values for a 400kHz, 5V–40V to 3.3V/6.5A Buck
8711 F03
BIAS
INTVEE
TG
CSP
CSN
ISP
ISN
2.2µF
2.2µF
RT 60.4k
51k
47nF
68pF
1.5nF
BG
GND
EN/FBIN
EXTVCC
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
1M
RFB2
316k
COUT
100µF
×2
VOUT
3.3V,
6.5A
CIN
10µF
×5
VIN
5V TO
40V VIN
LT8711
FB
VOUT
M1
M2
L1
4.7µH RSENSE
4.5mΩ
ADDITIONAL 470µF, 6.3V ELECTROLYTIC CAP ON VOUT
47µF, 50V ELECTROLYTIC CAP ON VIN
LT8711
15
Rev A
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BOOST CONVERTER COMPONENT SELECTION
The LT8711 can be configured as a boost converter as
in Figure4.
For a desired output current and output voltage over a
given input voltage range, Table 2 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a boost converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 2.
Variable Definitions:
VIN(MIN) = Minimum Input Voltage
VIN(MAX) = Maximum Input Voltage
VOUT = Output Voltage
IOUT = Output Current of Converter
f = Switching Frequency
DCMAX = Power Switch Duty Cycle at VIN(MIN)
VCSPN = Current Limit Voltage at DCMAX
Table2. Boost Design Equations
Parameters/Equations
Step 1: Inputs Pick VIN, VOUT, IOUT, and f to calculate equations
below.
Step 2: DCMAX
DCMAX ≅1– V
IN MIN
( )
VOUT
Step 3: VCSPN See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find VCSPN at DCMAX.
Step 4: RSENSE
RSENSE ≤0.63 •
V
CSPN
IOUT
1– DCMAX
( )
Step 5: L
LTYP =
RSENSE • VIN MIN
( )
12.5m • f • 1– VIN MIN
( )
VOUT
⎛
⎝
⎜⎞
⎠
⎟
LMIN =RSENSE • VOUT
40m • f • 1– V
IN MIN
( )
VOUT – V
IN MIN
( )
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
LMAX1 =
RSENSE • VIN MIN
( )
5m • f • 1– VIN MIN
( )
VOUT
⎛
⎝
⎜⎞
⎠
⎟
LMAX2 =
R
SENSE
• V
IN MAX
( )
5m • f • 1–
V
IN MAX
( )
VOUT
⎛
⎝
⎜⎞
⎠
⎟
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
LTYP and LMIN. The maximum of the L value range
is the lower of LMAX.
Step 6: COUT
COUT ≥
I
OUT
•DC
MAX
f • 0.005 • VOUT
Step 7: CIN
CIN ≥
DC
MAX
8 •L • f2• 0.005
Step 8: RFB1/RFB2
RFB1 =VOUT
0.8V – 1
⎛
⎝
⎜⎞
⎠
⎟•RFB2
Step 9: RT
RT=25000
f
– 2: f is in kHz and RT is in kΩ
NOTE: The final values for COUT and CIN may deviate from the above
equations in order to obtain desired load transient performance for a
particular application. The COUT and CIN equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
APPLICATIONS INFORMATION
Figure4. Boost Converter—The Component Values Given are
Typical Values for a 400kHz, 12V to 24V/3A Boost
VOUT
BIAS
INTVEE
BG
GND
CSP
ISP
ISN
CSN
2.2µF
2.2µF
RT
60.4k
187k
330nF
42pF
1nF
TG
EN/FBIN
EXTVCC
VIN
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
1M
RFB2
34k
COUT
6.8µF
×4
VOUT
24V,
3A
CIN
10µF
×6
VIN
10.8V TO
13.2V
LT8711
FB
VOUT
M1
M2
L1
8.2µH
RSENSE
4mΩ
8711 F04
ADDITIONAL 270µF, 50V ELECTROLYTIC CAP ON VOUT
47µF, 50V ELECTROLYTIC CAP ON VIN
LT8711
16
Rev A
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APPLICATIONS INFORMATION
SEPIC CONVERTER COMPONENT SELECTION
The LT8711 can be configured as a SEPIC converter as
in Figure5.
For a desired output current and output voltage over a
given input voltage range, Table 3 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a SEPIC converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 3.
Variable Definitions:
VIN(MIN) = Minimum Input Voltage
VIN(MAX) = Maximum Input Voltage
VOUT = Output Voltage
IOUT = Output Current of Converter
f = Switching Frequency
DCMAX = Power Switch Duty Cycle at VIN(MIN)
VCSPN = Current Limit Voltage at DCMAX
Table3. SEPIC Design Equations
Parameters/Equations
Step 1: Inputs Pick VIN, VOUT, IOUT, and f to calculate equations
below.
Step 2: DCMAX
DCMAX ≅
V
OUT
V
IN MIN
( )
+VOUT
Step 3: VCSPN See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find VCSPN at DCMAX.
Step 4: RSENSE
RSENSE ≤0.63 •
V
CSPN
IOUT
1– DCMAX
( )
RSENSE1 = RSENSE2 = RSENSE
Step 5: L
LTYP =RSENSE • VOUT
12.5m • f •VIN MIN
( )
VIN MIN
( )
+VOUT
LMIN =RSENSE • VOUT
40m • f • 1– V
IN MIN
( )
VOUT
⎛
⎝
⎜⎞
⎠
⎟
2
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
LMAX =RSENSE • VOUT
5m • f •VIN MIN
()
VIN MIN
()
+VOUT
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
LTYP and LMIN. The maximum of the L value range
is the lower of LMAX.
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors.
Step 6: C1 C1 ≥ 10µF (Typical); VRATING > VIN
Step 7: COUT
COUT ≥
I
OUT
•DC
MAX
f • 0.005 • VOUT
Step 8: CIN
CIN ≥
DC
MAX
8 •L • f2• 0.005
Step 9: RFB1/RFB2
RFB1 =VOUT
0.8V – 1
⎛
⎝
⎜⎞
⎠
⎟•RFB2
Step 10: RT
RT=25000
f
– 2: f is in kHz and RT is in kΩ
NOTE: The final values for COUT and CIN may deviate from the above
equations in order to obtain desired load transient performance for a
particular application. The COUT and CIN equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
Figure5. SEPIC Converter —The Component Values Given Are
Typical Values for a 200kHz, 4.5V–40V to 12V/4A SEPIC
VOUT
BIAS
INTVEE
BG
CSP
CSN
GND
2.2µF
2.2µF
C1
10µF
×3
RT 118k
49.9k
470nF
100pF
4.7nF TG
EN/FBIN
EXTVCC
VIN
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
1M
RFB2
71.5k
COUT
22µF
×3
VOUT
12V,
4A
CIN
10µF
×2
VIN
4.5V TO
40V
LT8711
FB
VOUT
M1
M2
RSENSE
2mΩ
L1
8.2µH
L2
15µH
RSENSE1
2mΩ
8711 F05
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON VOUT
56µF, 50V ELECTROLYTIC CAP ON VIN
ISP
ISN
LT8711
17
Rev A
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APPLICATIONS INFORMATION
ZETA CONVERTER COMPONENT SELECTION
The LT8711 can be configured as a ZETA converter as in
Figure6.
For a desired output current and output voltage over a
given input voltage range, Table 4 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a ZETA converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 4.
Variable Definitions:
VIN(MIN) = Minimum Input Voltage
VIN(MAX) = Maximum Input Voltage
VOUT = Output Voltage
IOUT = Output Current of Converter
f = Switching Frequency
DCMAX = Power Switch Duty Cycle at VIN(MIN)
VCSPN = Current Limit Voltage at DCMAX
Table4. ZETA Design Equations
Parameters/Equations
Step 1: Inputs Pick VIN, VOUT, IOUT, and f to calculate equations
below.
Step 2: DCMAX
DCMAX ≅
V
OUT
V
IN MIN
( )
+VOUT
Step 3: VCSPN See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find VCSPN at DCMAX.
Step 4: RSENSE
RSENSE ≤0.63 •
V
CSPN
IOUT
1– DCMAX
( )
RSENSE1 = RSENSE2 = RSENSE
Step 5: L
LTYP =RSENSE • VOUT
12.5m • f •VIN MIN
( )
VIN MIN
( )
+VOUT
LMIN =RSENSE • VOUT
40m • f • 1– V
IN MIN
( )
VOUT
⎛
⎝
⎜⎞
⎠
⎟
2
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
LMAX =RSENSE • VOUT
5m • f •VIN MIN
()
VIN MIN
()
+VOUT
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
LTYP and LMIN. The maximum of the L value range
is the lower of LMAX.
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors.
Step 6: C1 C1 ≥ 10µF (Typical); VRATING > VIN
Step 7: COUT
COUT ≥
I
OUT
•DC
MAX
f • 0.005 • VOUT
Step 8: CIN
CIN ≥
DC
MAX
8 •L • f2• 0.005
Step 9: RFB1/RFB2
RFB1 =VOUT
0.8V – 1
⎛
⎝
⎜⎞
⎠
⎟•RFB2
Step 10: RT
RT=25000
f
– 2: f is in kHz and RT is in kΩ
NOTE: The final values for COUT and CIN may deviate from the above
equations in order to obtain desired load transient performance for a
particular application. The COUT and CIN equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
BIAS
INTVEE
TG
ISN
ISP
CSP
CSN
2.2µF
2.2µF
C1
10µF ×3
RT
118k
20k
470nF
100pF
2.2nF
BG
EN/FBIN
EXTVCC
VIN
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
1M
RFB2
69.8k
COUT
22µF
×4
VOUT
12V,
3.5A (VIN > 16V)
2.5A (9V < VIN < 16V)
1.5A (VIN < 9V)
CIN
10µF
×6
VIN
5V TO
40V
LT8711
FB
VOUT
RSENSE2
3.5mΩ
L1B 2.2µH
L1A 2.2µH
RSENSE1
3.5mΩ
8711 F06
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON VOUT
56µF, 50V ELECTROLYTIC CAP ON VIN
GND
CSP
CSN
CSP
CSN
Figure6. ZETA Converter—The Component Values Given Are
Typical Values for a 200kHz, 5V–40V to 12V/3.5A ZETA
LT8711
18
Rev A
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APPLICATIONS INFORMATION
BUCK-BOOST CONVERTER COMPONENT SELECTION
The LT8711 can be configured as a buck-boost converter
as in Figure7.
For a desired output current and output voltage over a
given input voltage range, Table 5 is a step-by-step set of
equations to calculate component values for the LT8711
when operating as a buck-boost converter. Refer to more
detail in this section and the Appendix for further informa-
tion on the design equations presented in Table 5.
Variable Definitions:
VIN(MIN) = Minimum Input Voltage
VIN(MAX) = Maximum Input Voltage
VOUT = Output Voltage
IOUT = Output Current of Converter
f = Switching Frequency
DCMAX = Power Switch Duty Cycle at VIN(MIN)
VCSPN = Current Limit Voltage at DCMAX
Table5. Buck-Boost Design Equations
Parameters/Equations
Step 1: Inputs Pick VIN, VOUT, IOUT, and f to calculate equations
below.
Step 2: DCMAX
DCMAX ≅
V
OUT
V
IN MIN
( )
+VOUT
Step 3: VCSPN See Max Current Limit vs Duty Cycle plot in Typical
Performance Characteristics to find VCSPN at DCMAX.
Step 4: RSENSE
RSENSE ≤0.63 •
V
CSPN
IOUT
1– DCMAX
( )
RSENSE1 = RSENSE2 = RSENSE
Step 5: L
LTYP =RSENSE • VOUT
12.5m • f •VIN MIN
( )
VIN MIN
( )
+VOUT
LMIN =RSENSE • VOUT
40m • f • 1– V
IN MIN
( )
VOUT
⎛
⎝
⎜⎞
⎠
⎟
2
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
LMAX =RSENSE • VOUT
5m • f •VIN MIN
()
VIN MIN
()
+VOUT
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
LTYP and LMIN. The maximum of the L value range
is the lower of LMAX.
Step 6: COUT
COUT ≥
I
OUT
•DC
MAX
f • 0.005 • VOUT
Step 7: CIN
CIN ≥
DC
MAX
8 •L • f2• 0.005
Step 8: RFB1/RFB2
RFB1 =VOUT
0.8V – 1
⎛
⎝
⎜⎞
⎠
⎟•RFB2
Step 9: RT
RT=25000
f
– 2: f is in kHz and RT is in kΩ
NOTE: The final values for COUT and CIN may deviate from the above
equations in order to obtain desired load transient performance for a
particular application. The COUT and CIN equations assume zero ESR, so
increase the capacitance accordingly based on the combined ESR.
Figure7. Buck-Boost Converter—The Component Values
Given Are Typical Values for a 400kHz, 5V–40V to 12V/2.5A
Buck-Boost
10nF
10Ω
10Ω
10nF
BIAS
INTVEE
TG
BG
CSP
CSN
2.2µF
ISN
ISP
GND
EN/FBIN
EXTVCC
OPMODE
INTVCC
RT
SYNC
SS
VC
RSENSE2
4mΩ
VOUT
12V,
3.5A (VIN >16V)
2.5A (9V < VIN < 16V)
1.5A (VIN < 9V)
LT8711
FB
VIN
VOUT
M1
D1
L1 4.7µH D2
M2
RSENSE1
4mΩ
RFB1
1M
RFB2
69.8k
COUT
100µF
×2
8711 F07
2.2µF
100pF
RT
60.4k
110k
330nF
100pF
2.2nF
CIN
10µF
×6
VIN
5V TO
40V
LT8711
19
Rev A
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APPLICATIONS INFORMATION
SETTING THE OUTPUT VOLTAGE REGULATION
The LT8711 output voltage is set by a resistor divider
between VOUT, FB, and GND.
VOUT =0.8V • 1+RFB1
R
FB2
⎛
⎝
⎜⎞
⎠
⎟
where RFB1 and RFB2 are shown in the Block Diagram.
See the Electrical Characteristics for tolerances on the FB
regulation voltage.
SETTING THE INPUT VOLTAGE REGULATION OR
UNDERVOLTAGE LOCKOUT
By connecting a resistor divider between VIN, EN/FBIN,
and GND, the EN/FBIN pin provides a means to regulate
the input voltage or to create an undervoltage lockout
function. Referring to error amplifier EA2 in the block
diagram, when EN/FBIN is lower than the 1.2V reference,
VC is pulled low. For example, if VIN is provided by a
relatively high impedance source (e.g. a solar panel) and
the current draw pulls VIN below a preset limit, VC will be
reduced, thus reducing current draw from the input supply
and limiting the input voltage drop.
To set the minimum or regulated input voltage use:
V
IN MIN–REG
( )
=1.2V • 1+RIN1
RIN2
⎛
⎝
⎜⎞
⎠
⎟
where RIN1 and RIN2 are shown in the Block Diagram.
Temperature Dependent Output Voltage Using NTC
Resistor
It may be desirable to regulate the converter’s output based
on the ambient temperature. The INTVCC LDO regulated
voltage is 5.0V ± 4% (see Electrical Characteristics), and
a negative temperature coefficient (NTC) resistor can be
used to sum into the FB pin to create an output voltage
that decreases with temperature. See Figure 8 for the
necessary connections.
+
–
8711 F08
RNTC
R2RFB2
RFB1
R1
INTVCC
FB
VC
0.8V
VOUT
FROM SYSTEM
5V
EA1
LT8711
Figure8. Temperature Dependent Output Using an
NTC Resistor Divider
The FB voltages regulates to 0.8V (typical). For an accurate
room temperature output voltage, size the resistor divider
off the INTVCC pin to give 0.8V such that the current through
R2 is ~0 at room temperature. Choose RNTC(25) ≤ 10kΩ
and use the equations below to calculate R1, RFB1, and
VOUT at room temperature and RFB2 for a desired VOUT
change over temperature.
R1=RNTC(25)
0.8V
5.0V – 0.8V
VOUT ≅0.8V +
R
FB1
R2
• 0.8V – 5.0V • R1
R1+RNTC(25)
⎛
⎝
⎜⎞
⎠
⎟+0.8V • RFB1
RFB2
RNTC =RNTC 25
( )
• e
β•1
T–1
T25
⎛
⎝
⎜⎞
⎠
⎟
∆VOUT =–5.0V •
R
FB1
R2 •R1
•1
R1+RNTC(T(MAX))
–1
R1+RNTC(T(MIN))
⎛
⎝
⎜⎞
⎠
⎟
R2 =
–5.0V
∆VOUT
•RFB1 •R1
•1
R1+RNTC(T(MAX))
–1
R1+RNTC(T(MIN))
⎛
⎝
⎜⎞
⎠
⎟
LT8711
20
Rev A
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APPLICATIONS INFORMATION
where:
RNTC(25) = Resistance of the NTC resistor at 25°C
ß = Material-specific constant of NTC resistor.
Specified at two temperatures such as
ß25/85. If more than two ßs are specified,
use the most appropriate for the application.
T = Absolute temperature in Kelvin
T25 = Room temperature in Kelvin (298.15K)
SWITCH CURRENT LIMIT (CSP-CSN CURRENT
SENSING)
The external current sense resistor (RSENSE) sets the maxi-
mum peak current. The maximum voltage across RSENSE
is 50mV (typical) at very low switch duty cycles, and then
slope compensation decreases the current limit as the duty
cycle increases (see the Max Current Limit vs Duty Cycle
(CSP-CSN) plot in the Typical Performance Characteristics).
The equation below gives the switch current limit for a given
duty cycle and current sense resistor (find VCSPN at the
operating duty cycle in the plot mentioned).
ISW LIMIT
( )
=
V
CSPN
R
SENSE
To provide a desired load current for any given application,
RSENSE must be sized appropriately. The equation below
calculates RSENSE for a desired output current:
RSENSE ≤0.74 • η•
V
CSPN
IOUT
• 1– DCMAX
( )
• 1–
i
RIPPLE
2
⎛
⎝
⎜
⎞
⎠
⎟
η = Converter efficiency (assume ~90%)
VCSPN = Max current limit voltage (see Max Current
Limit vs Duty Cycle (CSP-CSN) plot in the
Typical Performance Characteristics)
IOUT = Converter load current
DCMAX = Switching duty cycle at minimum VIN (see
Power Switch Duty Cycle in Appendix)
iRIPPLE = Peak-to-peak inductor ripple current percent-
age at minimum VIN (recommended to use
25%)
ISP-ISN CURRENT SENSING
CSP/CSN current sensing is used in switching regulator
peak current control.
ISP/ISN current sensing monitors the current of the rec-
tifier switch and helps protect the circuit from overload
conditions.
The ISP-ISN circuitry delays switching if the rectifier switch
current goes too high. This mechanism also protects
the part during short-circuit and overload conditions by
keeping the current through the inductor under control.
Let’s see a buck mode example.
8711 F09
BIAS
INTVEE
TG
CSP
CSN
ISP
ISN
RTBG
GND
EN/FBIN
EXTVCC
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
RFB2
COUT
CIN
LT8711
FB
VOUT
M1
M2
L1 RSENSE
VIN
Figure9. ISP-ISN Current Sensing Example
A potential controllability problem could occur under
short-circuit conditions without rectifier switch current
sensing. If the power supply output is short circuited, the
feedback amplifier (EA) responds to the low output voltage
by raising the control voltage, VC, to its peak current limit
value. Ideally, the top switch would be turned on, and then
turned off as its current exceeded the value indicated by
VC. However, there is finite response time involved in both
the current comparator and turnoff of the top switch. These
result in a minimum on time, tON(MIN). When combined
with high VIN, the potential exists for a loss of control.
LT8711
21
Rev A
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APPLICATIONS INFORMATION
Expressed mathematically the requirement to maintain
control is:
f • tON ≤
V
R(SENSE)_L
+V
DS_NMOS
+I • R
V
IN
where:
f = switching frequency
tON = switch minimum on time
VR(SENSE)_L = voltage drop on high side sense resistor
VDS_NMOS = voltage drop on high side PMOS switch
VIN = Input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at IPK, but will cycle-by-cycle ratchet up to some
higher value. With rectifier switch current sensing, the
current through the inductor would be controlled under
the whole clock cycle. The switching will only resume once
rectifier switch current has fallen below IPK.
ISP-ISN current sensing is also used in reverse current
detecting for DCM operation.
CURRENT SENSE FILTERING
Certain applications may require filtering of the current
sense signals due to excessive switching noise that can
appear across RSENSE1 and/or RSENSE2. Higher operating
voltages, higher inductor current, higher values of RSENSE,
and more capacitive MOSFETs will all contribute additional
noise across RSENSE when MOSFETs transition. The CSP/
CSN and/or the ISP/ISN sense signals can be filtered by
adding one of the RC networks shown in Figure10. The
filter shown in Figure10a filters out differential noise,
whereas the filter in Figure10b filters out the differential
and common mode noise at the expense of an additional
capacitor and approximately twice the capacitance value.
It is recommended to Kelvin tie the ground connection
directly to the paddle of the LT8711 if using the filter in
Figure10b. The filter network should be placed as close
as possible to the LT8711. Resistors greater than 10Ω
should be avoided as this can Increase the offset voltages
at the CSP/CSN and ISP/ISN pins.
Table6. CSP/CSN, ISP/ISN Bias Current:
VCM = 0V VCM > 3V
I_CSP (typ) 0µA 4µA ~ 25µA
I_CSN (typ) –4µA ~ –25µA 110µA
I_ISP (typ) 0µA 4µA ~ 25µA
I_ISN (typ) –4µA ~ –25µA 220µA
When VCM changes from 0V to 3V, bias current changes
gradually from low side values to high side values as
shown in Table 6.
CSN/ISN bias current at high side is proportional to tem-
perature (see the CSN/ISN Bias Current vs Temperature
plots in the Typical Performance Characteristics).
Positive bias currents flow into the pins. Negative bias
currents flow out of the pins.
Bias current of 4µA ~ 25µA and –4µA ~ –25µA in the
table changes according to the VC voltage. 4µA (–4µA)
corresponds to the minimum VC voltage. 25µA (–25µA)
corresponds to the maximum VC voltage.
8710 F10a
RSENSE1, RSENSE2 2.2nF
5.1Ω
5.1Ω
CSP OR ISP
LT8711
CSN OR ISN
Figure10a. Differential RC Filter on CSP/CSN and/or ISP/ISN Pins
8711 F10b
RSENSE1, RSENSE2
4.7nF
5.1Ω
5.1Ω
CSP OR ISP
LT8711
CSN OR ISN
4.7nF
Figure10b. Differential and Common Mode RC Filter on CSP/
CSN and/or ISP/ISN Pins
SWITCHING FREQUENCY
The LT8711 uses a constant frequency architecture whose
frequency can be between 100kHz and 750kHz. The fre-
quency can be set using the internal oscillator or can be
synchronized to an external clock source. Selection of
LT8711
22
Rev A
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APPLICATIONS INFORMATION
the switching frequency is a trade-off between efficiency
and component size. Low frequency operation increases
efficiency by reducing MOSFET switching losses, but
requires larger inductance and/or capacitance to maintain
low output ripple voltage. For high power applications,
consider operating at lower frequencies to minimize
MOSFET heating from switching losses. The switching
frequency can be set by placing an appropriate resistor
from the RT pin to ground and tying the SYNC pin low. The
frequency can also be synchronized to an external clock
source driven into the SYNC pin. The following sections
provide more details.
Oscillator Timing Resistor (RT)
The operating frequency of the LT8711 can be set by the
internal free-running oscillator. When the SYNC pin is
driven low (< 0.4V), the frequency of operation is set by a
resistor from the RT pin to ground. The oscillator frequency
is calculated using the following formula:
f=
25000
R
T
+2
where f is in kHz and RT is in kΩ. Conversely, RT can be
calculated from the desired frequency using:
RT=25000
f
– 2
Clock Synchronization
An external source can set the operating frequency of
the LT8711 by providing a digital clock signal into the
SYNC pin (RT resistor still required). The LT8711 will
operate at the SYNC clock frequency. The LT8711 will
revert to its internal free-running oscillator clock when
the SYNC pin is driven below 0.4V for a few free-running
clock periods. The LT8711 will operate in FCM mode with
internal free-running oscillator clock if driving SYNC high
for an extended period of time.
The duty cycle of the SYNC signal must be between 20%
and 80% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
1. SYNC may not toggle outside the frequency range of
140kHz to 750kHz unless it is stopped below 0.4V to
enable the free-running oscillator.
2. The SYNC frequency can always be higher than the free-
running oscillator frequency (as set by the RT resistor),
fOSC, but should not be less than 20% below fOSC.
LDO REGULATORS
The LT8711 has two linear regulators to run the BG and
TG gate drivers. The INTVCC LDO regulates 5V (typical)
above ground, and the INTVEE regulator regulates 5.15V
(typical) below the BIAS pin.
INTVCC LDO Regulator
The INTVCC LDO is used as the top rail for the BG gate
driver. An external capacitor greater than 2.2μF must be
placed from the INTVCC pin to ground. The capacitor should
have low ESR, such as a ceramic capacitor.
The INTVCC LDO can run off VIN or EXTVCC and will
intelligently select to run off the best rail for minimizing
chip power loss, but at the same time, select the proper
input for maintaining INTVCC as close to 5V as possible.
For example, Figure11 is a plot that shows how VIN or
EXTVCC is selected.
Overcurrent protection circuitry typically limits the maxi-
mum current draw from the LDO to ~50mA. If the selected
input voltage is greater than 24V (typical), then the current
limit of the LDO reduces linearly with input voltage to limit
the maximum power in the INTVCC pass device. See the
INTVCC Current Limit vs VIN or EXTVCC plot in the Typical
Performance Characteristics.
POWERED BY VIN
POWERED BY EXTVCC
VIN
EXTVCC
0
40V
5.5V
0
8711 F11
40V5.5V
VIN, EXTVCC POWER SELECTION
Figure11. INTVCC Input Voltage Selection
LT8711
23
Rev A
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APPLICATIONS INFORMATION
Power dissipated in the INTVCC LDO should be minimized to
improve efficiency and prevent overheating of the LT8711.
The current limit reduction with input voltage circuit helps
prevent the part from overheating, but these guidelines
should be followed. The maximum current drawn through
the INTVCC LDO occurs under the following conditions:
1. Large (capacitive) MOSFETs being driven at high
frequencies
2. The converter’s switch voltage (VIN for BUCK, VOUT
for BOOST and BUCK-BOOST, VIN + VOUT for SEPIC
converters) is high, thus requiring more charge to
turn the MOSFET gates on and off.
In general, use appropriately sized MOSFETs and lower
the switching frequency for higher voltage applications to
keep the INTVCC current at a minimum.
INTVEE LDO Regulator
The BIAS and INTVEE voltages are used for the top and
bottom rails of the TG gate driver respectively. An external
capacitor greater than 2.2μF must be placed between the
BIAS and INTVEE pins. The capacitor should have low
ESR, such as ceramic capacitor.
Overcurrent protection circuitry typically limits the maxi-
mum current draw from the regulator to ~80mA. If the
BIAS voltage is greater than 15V (typical), then the current
limit of the regulator reduces linearly with input voltage
to limit the maximum power in the INTVEE pass device.
See the INTVEE Current Limit vs BIAS plot in the Typical
Performance Characteristics.
The same thermal guidelines from the INTVCC LDO Regula-
tor section apply to the INTVEE regulator as well.
NONSYNCHRONOUS CONVERTER
It may be desirable in some applications to replace the
external PFET with a Schottky diode to make a nonsyn-
chronous converter. One example would be a high output
voltage application because the voltage drop across the
rectifier has a small effect on the efficiency of the converter.
In fact, for high output voltage applications, replacing
the PFET with a Schottky may result in higher efficiency
because the LT8711 doesn’t have to supply gate drive to
the PFET. Figure12 shows the recommended connec-
tions for using the LT8711 as a nonsynchronous boost
converter, however the same concept can be used for any
other converter topology.
VOUT
BIAS
INTVEE
BG
GND
CSP
ISP
ISN
CSN
FB
EN/FBIN
EXTVCC
VIN
OPMODE
INTVCC RFB1
RFB2
COUT
VOUT
CIN
VIN
LT8711
VOUT
M1
L1
RSENSE
8711 F12
Figure12. Simplified Schematic of a Nonsynchronous
Boost Converter
LAYOUT GUIDELINES FOR BUCK, BOOST, SEPIC, ZETA
AND BUCK-BOOST TOPOLOGIES
General Layout Guidelines
• To optimize thermal performance, solder the ex-
posed pad of the LT8711 to the ground plane with
multiple vias around the pad connecting to additional
ground planes.
• High speed switching path (see specific topology
below for more information) must be kept as short
as possible.
• The FB, VC and RT components should be placed as
close to the LT8711 as possible, while being far away
as practically possible from switching nodes. The
ground for these components should be separated
from the switch current path.
• Place bypass capacitors for the VIN and EXTVCC pins
(1μF or greater) as close as possible to the LT8711.
• Place bypass capacitors for the INTVCC and INTVEE
(between BIAS and INTVEE) pins (2.2μF or greater) as
close as possible to the LT8711.
LT8711
24
Rev A
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APPLICATIONS INFORMATION
• The load should connect directly to the positive and
negative terminals of the output capacitor for best
load regulation.
BUCK Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path)
governing MN, MP, CIN, and ground return as short
as possible to minimize parasitic inductive spikes at
the switch node during switching.
8711 F13
LT8711
NFET
PFET
CIN1
CIN2
VIN VOUT
GND
GND
COUT1
COUT2
L
RSENSE
Figure13. Suggested Component Placement for Buck Topology
Boost Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov-
erning MN, MP, COUT, and ground return as short as
possible to minimize parasitic inductive spikes at the
switch node during switching.
8711 F13
LT8711
NFET
PFET
CIN1
CIN2
VIN VOUT
GND
GND
COUT1
COUT2
L
RSENSE
Figure14. Suggested Component Placement for Boost Topology
SEPIC Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path)
governing RSENSE1, MN, C1, MP, RSENSE2, COUT, and
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
C1
8711 F15
LT8711
NFET
PFET
CIN1
CIN2
VIN VOUT
GND
GND
COUT1
COUT2
L
RSENSE2
RSENSE1
Figure15. Suggested Component Placement for SEPIC Topology
ZETA Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path)
governing RSENSE1, MN, C1, MP, RSENSE2, CIN, and
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
8711 F16
LT8711
NFET
PFET
CIN1
CIN2
VIN VOUT
GND
GND
COUT1
COUT2
L
RSENSE2
RSENSE1
C
Figure16. Suggested Component Placement for ZETA Topology
LT8711
25
Rev A
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APPLICATIONS INFORMATION
Buck-Boost Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path)
governing RSENSE1, DIO1, MP, CIN, and ground return
as short as possible to minimize parasitic inductive
spikes at the switch node during switching.
• Keep length of loop (high speed switching path) gov-
erning RSENSE2, MN, DIO2, COUT, and ground return
as short as possible to minimize parasitic inductive
spikes at the switch node during switching.
8711 F17
LT8711
NFET
PFET
CIN1
CIN2
VIN VOUT
GND
GND
COUT1
COUT2
L
RSENSE1
RSENSE2
DI01 DI02
Figure17. Suggested Component Placement for Buck-Boost Topology
Current Sense Resistor Layout Guidelines
• Route the CSP/CSN and ISP/ISN lines differentially
(close together) from the chip to the current sense
resistor as shown in Figure17.
• Place the vias that connect the CSP/CSN and ISP/ISN
lines directly at the terminals of the current sense
resistor as shown in Figure17.
8705 F20
RSENSE1, 2
TO
CURRENT
SENSE
PINS
Figure18. Suggested Routing and Connections of
CSP/CSN and ISP/ISN Lines
THERMAL CONSIDERATIONS
Overview
The primary components on the board that consume the
most power and produce the most heat are the power
switches, MN and MP, the power inductor, the Schottky
diodes in the nonsynchronous buck-boost converter and
the LT8711 IC. It is imperative that a good thermal path
be provided for these components to dissipate the heat
generated within the packages. This can be accomplished
by taking advantage of the thermal pads on the underside
of the packages. It is recommended that multiple vias in
the printed circuit board be used to conduct heat away
from each of these components and into a copper plane
with as much area as possible. For the case of the power
switches, the copper area of the drain connections shouldn’t
be too big as to create a large EMI surface that can radiate
noise around the board.
Power MOSFET Loss and Thermal Calculations
The LT8711 requires two external power MOSFETs, an
NFET switch for the BG gate driver and a PFET switch for
the TG gate driver. Important parameters for estimating
the power dissipation in the MOSFETs are:
1. On-resistance (RDS(ON))
2. Gate-to-drain charge (QGD)
3. PFET body diode forward voltage (VBD)
4. VDS of the FETs during their Off-Time
5. Switch current (ISW)
6. Switching frequency (f)
The power loss in each power switch has a DC and AC
term. The DC term is when the power switch is fully on,
and the AC term is when the power switch is transitioning
from on-off or off-on.
LT8711
26
Rev A
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The following applies for both the NFET and PFET power
switches. Below are the equations for the power loss in
MN and MP.
P
MOSFET
=P
I2R
+P
SWITCHING
P
MN =IN2• RDS ON
( )
+V
DS •IN• f • tRF +P
RR–N
P
MP =IP2•RDS ON
( )
+V
BD • IPK +IVY
1.6
⎛
⎝
⎜⎞
⎠
⎟• f • 140nx +P
RR–N
I
PK =ISW +iRIPPLE
2; IVY =ISW –iRIPPLE
2
P
RR–N ≈V
DS •IRR • tRR • f
2
P
RR–P ≈V
DS •IRR • tRR • f
2
where:
f = Switching Frequency
IN = NFET RMS Current
IP = PFET RMS Current
tRF = Average of the rise and fall times of the NFET’s
drain voltage
ISW = Average switch current during its on-time
IPK = Peak inductor current
IVY = Valley inductor current
iRIPPLE = Inductor ripple current
DC = Switch duty cycle (see Power Switch Duty Cycle
section in Appendix)
VBD = PFET body diode forward voltage at ISW
VDS = Voltage across the FET when it’s off.
PRR-N = PFET body diode reverse recovery power loss
in the NFET
PRR-P = PFET body diode reverse recovery power loss
in the PFET
IRR = Current needed to remove the PFET body diode
charge
tRR = Reverse recovery time of PFET body diode
Typical values for tRF are 10ns to 40ns depending on the
MOSFET capacitance and drain voltage. In general, the
lower the QGD of the MOSFET, the faster the rise and fall
times of its drain voltage. For best calculations, measure
the rise and fall times in the application.
PFET body diode reverse recovery power loss is depen-
dent on many factors and can be difficult to quantify in
an application. In general, this power loss increases with
higher VDS and/or higher switching frequency.
Chip Power and Thermal Calculations
Power dissipation in the LT8711 chip comes from three
primary sources: INTVCC and INTVEE LDOs providing gate
drive to the BG and TG pins and the chip quiescent cur-
rent. The average current through each LDO is determined
by the gate charge of the power switches, MN and MP
,
and the switching frequency. Below are the equations for
calculating the chip power loss.
The INTVCC LDO primarily supplies voltage for the BG
gate driver. The BIAS and INTVEE voltages supply the top
and bottom rails of the TG gate driver respectively. The
chip Q current comes from INTVCC. Below are the chip
power equations:
PINTVCC_BG = QMN • f • VSELECT
PINTVCC_Q = 2mA • VSELECT
PINTVEE = QMP • f • VBIAS
where:
f = Switching frequency
QMN = Total gate charge of NFET power switch (MN)
QMP = Total gate charge of PFET power switch (MP)
VSELECT = INTVCC LDO selected input
voltage, VIN or EXTVCC (see LDO Regulators
section)
Thermal Lockout
If the die temperature reaches ~165°C, the part will go
into shutdown, so the power switches turn off and the
soft-start capacitor will be discharged. The LT8711 will
come out of shutdown when the die temperature drops
by ~5°C (typical).
APPLICATIONS INFORMATION
LT8711
27
Rev A
For more information www.analog.com
APPENDIX
POWER SWITCH DUTY CYCLE
The external power main switch (PFET in the Block Dia-
gram) cannot remain off for 100% of each clock cycle, and
will turn on for a minimum on time (MinOnTime) when in
regulation. This MinOnTime governs the minimum allow-
able duty cycle given by:
DCMIN =
(MinOnTime)
T
P
•100%
where TP is the clock period and MinOnTime (found in
the Electrical Characteristics) is 100ns (typ).
The application should be designed such that the operating
duty cycle is higher than DCMIN.
Duty cycle equations for different topologies are given
below.
For the Buck topology (see Figure3):
DCBUCK ≅
V
OUT
V
IN
For the Boost topology (see Figure4):
DCBOOST ≅1–
V
IN
V
OUT
For the SEPIC topology (see Figures 6):
DCSEPIC ≅
V
OUT
V
IN
+V
OUT
For the ZETA topology (see Figures 7):
DCZETA ≅
V
OUT
V
IN
+V
OUT
For the Buck-Boost topology (see Figures 8):
DCBUCK−BOOST ≅
V
OUT
V
IN +VOUT
INDUCTOR SELECTION
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses.
Additionally, choose inductors with more volume for a given
inductance. The inductor should have low DCR (copper-
wire resistance) to reduce I2R losses, and must be able
to handle the peak inductor current without saturating.
Note that in some applications, the current handling
requirements of the inductor can be lower, such as in the
SEPIC topology where each inductor carries a fraction of
the total switch current. Molded chokes or chip inductors
do not have enough core area to support peak inductor
currents in the 5A to 15A range. To minimize radiated
noise, use a toroidal or shielded inductor. See Table7 for
a list of inductor manufacturers.
Table7. Inductor Manufacturers
Coilcraft MSS1278, XAL1010, and
MSD1278 Series www.coilcraft.com
Cooper
Bussmann DRQ127, DR127, and
HCM1104 Series www.cooperbussmann.com
Vishay IHLP Series www.vishay.com
Würth WE-DCT Series
WE-CFWI Series www.we-online.com
Minimum Inductance
Although there can be a trade-off with efficiency, it is
often desirable to minimize board space by choosing
smaller inductors. When choosing an inductor, there are
two conditions that limit the minimum inductance; (1)
providing adequate load current, and (2) avoidance of
subharmonic oscillation.
Adequate Load Current
Small value inductors result in increased ripple currents
and thus, due to the limited peak switch current, decrease
the average current that can be provided to the load.
Avoiding Subharmonic Oscillations
The LT8711’s internal slope compensation circuit will
prevent subharmonic oscillations that can occur when
the duty cycle is greater than 50%, provided that the in-
ductance exceeds a minimum value. In applications that
operate with duty cycles greater than 50%, the inductance
must be at least:
LMIN ≥V
IN •RSENSE • 2 •DC – 1
( )
40m •DC • f
, Buck Topology
LMIN ≥V
IN •RSENSE • 2 •DC – 1
( )
40m • DC • f • 1– DC
( )
, Other Topologies
LT8711
28
Rev A
For more information www.analog.com
APPENDIX
where
LMIN = L1 for buck, boost and buck-boost topologies
LMIN = L1 = L2 for coupled dual inductor topologies
(SEPIC and ZETA)
LMIN = L1 || L2 for uncoupled dual inductor topologies
(SEPIC and ZETA)
Inductor Current Rating
The inductor(s) must have a rating greater than its (their)
peak operating current to prevent inductor saturation,
which would result in efficiency losses.
POWER MOSFET SELECTION
The LT8711 requires two external power MOSFETs, an
NFET switch for the BG gate driver and a PFET switch for
the TG gate driver. It is important to select MOSFETs for
optimizing efficiency. For choosing an NFET and PFET, the
important device parameters are:
1. Breakdown voltage (BVDSS)
2. Gate threshold voltage (VGSTH)
3. On-resistance (RDS(ON))
4. Total gate charge (QG)
5. Turn-off delay time (tD(OFF))
6. Package has exposed paddle
If operating close to the BVDSS rating of the MOSFET, check
the leakage specifications on the MOSFET because leakage
can decrease the efficiency of the converter.
The NFET and PFET gate-to-source drive is 5V typical.
The BG gate driver can begin switching when the INTVCC
voltage exceeds ~4.1V, so ensure the selected NFET is in
the linear mode of operation with 4.1V of gate-to-source
drive to prevent possible damage to the NFET.
The TG gate driver can begin switching when the BIAS-
INTVEE voltage exceeds ~3.85V, so it is optimal that the
PFET be in the linear mode of operation with 3.85V of
gate-to-source drive. Try to choose a PFET with a low body
diode reverse recovery time to minimize stored charge in
the PFET. The stored charge in the PFET body diode gets
removed when the NFET switch turns on and can lead to
efficiency hits especially in applications where the VDS of
the PFET (during off-time) is high. For these applications, it
may be beneficial to put a Schottky diode across the PFET
to reduce the amount of charge in the PFET body diode.
Power MOSFET on-resistance and total gate charge go
hand-in-hand and are typically inversely proportional to
each other; the lower the on-resistance, the higher the
total gate charge. Choose MOSFETs with an on-resistance
to give a voltage drop to be less than 300mV at the peak
current. At the same time, choose MOSFETs with a lower
total gate charge to reduce LT8711 power dissipation and
MOSFET switching losses.
The turn-off delay time (tD(OFF)) of available NFETs is
generally smaller than the LT8711’s non-overlap time.
However, the turn-off time of the available PFETs should
be looked at before deciding on a PFET for a given applica-
tion. The turn-off time must be less than the non-overlap
time of the LT8711 or else the NFET and PFET could be
on at the same time and damage to external components
may occur. If the PFET turn-off delay time as specified in
the data sheet is less than the LT8711 non-overlap time,
then the PFET is good to use. If the turn-off delay time is
longer than the non-overlap time, it doesn’t necessarily
mean it can’t be used. It may be unclear how the PFET
manufacturer measures the turn-off delay time, so it is
best to measure the PFET turn-off delay time with respect
to the PFET gate voltage.
Finally, both the NFET and PFET power MOSFETs should
be in a package with an exposed paddle for the drain
connection to be able to dissipate heat. The on-resistance
of MOSFETs is proportional to temperature, so it’s more
efficient if the MOSFETs are running cool with the help
of the exposed paddle. See Table8 for a list of power
MOSFET manufacturers.
Table8. Power MOSFET (NFET and PFET) Manufacturers
Fairchild Semiconductor www.fairchildsemi.com
On-Semiconductor www.onsemi.com
Vishay www.vishay.com
Diodes Inc. www.diodes.com
LT8711
29
Rev A
For more information www.analog.com
INPUT AND OUTPUT CAPACITOR SELECTION
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out of the regulator. A parallel combination of
capacitors is typically used to achieve high capacitance and
low ESR (equivalent series resistance). Tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
noise. A minimum 1μF ceramic capacitor should also be
placed from VIN to GND and from EXTVCC to GND as close
to the LT8711 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce ripple voltage and help reduce power loss in the
higher ESR bulk capacitors. X5R or X7R dielectrics are
preferred, as these materials retain their capacitance over
wide voltage and temperature ranges. Many ceramic ca-
pacitors, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired operating voltage.
COMPENSATION – ADJUSTMENT
To compensate the feedback loop of the LT8711, a series
resistor capacitor network in parallel with an optional single
capacitor should be connected from the VC pin to GND. For
most applications, choose a series capacitor in the range
of 0.47nF to 10nF with 2.2nF being a good starting value.
The optional parallel capacitor should range in value from
47pF to 220pF with 100pF being a good starting value.
The compensation resistor, RC, is usually in the range
of 10k to 100k. A good technique to compensate a new
application is to use a 100k potentiometer in place of the
series resistor RC. With the series and parallel capacitors
at 2.2nF and 100pF respectively, adjust the potentiometer
while observing the transient response and the optimum
value for RC can be found. The series capacitor can be
reduced or increased from 2.2nF to speed up the converter
or slow down the converter, respectively.
APPENDIX
LT8711
30
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
400kHz, 5V–40V Input to 3.3V/6.5A Buck
LOAD CURRENT (A)
0.001
0.01
0.1
1
7
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
8711 TA02a
BIAS
INTVEE
TG
CSP
CSN
ISP
ISN
2.2µF
2.2µF
RT 60.4k
51k
47nF
68pF
1.5nF
BG
GND
EN/FBIN
EXTVCC
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
1M
RFB2
316k
COUT
100µF
×2
VOUT
3.3V, 6.5A
CIN
10µF
×5
VIN
5V TO
40V
LT8711
FB
VOUT
M1
M2
L1
4.7µH RSENSE
5mΩ
L1: COILCRAFT 4.7µH XAL7070-472
M1: ST STL42P6LLF6
M2: FAIRCHILD FDMC86520L
CIN: 10µF, 50V, X7R
ADDITIONAL 47µF, 50V ELECTROLYTIC CAP ON VIN
COUT: 100µF, 6.3V, X7R
ADDITIONAL 470µF, 16V ELECTROLYTIC CAP ON VOUT
VIN
200µs/DIV
LOAD STEP
5A/DIV
VOUT
200mV/DIV
IL1
5A/DIV
8711 TA02c
Efficiency vs Load Current Transient Response with 2A to 5.5A to 2A Output Load Step
LT8711
31
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
400kHz, 12V Input to 24V/3A Boost Converter
VOUT
BIAS
INTVEE
BG
GND
CSP
ISP
ISN
CSN
2.2µF
2.2µF
RT
60.4k
187k
330nF
42pF
1nF
TG
EN/FBIN
EXTVCC
VIN
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
1M
RFB2
34k
COUT
6.8µF
×4
VOUT
24V, 3A
CIN
10µF
×6
VIN
10.8V TO
13.2V
LT8711
FB
VOUT
M1
M2
L1
8.2µH
RSENSE
4mΩ
8711 TA03a
L1: WÜRTH 8.2µH WE-HCI 7443550820
M1: INFINEON BSC026N04
M2: ST STL60P4LLF6
CIN: 10µF, 50V, X7R
ADDITIONAL 47µF, 50V ELECTROLYTIC CAP ON VIN
COUT: 6.8µF, 50V, X7R
ADDITIONAL 270µF, 50V ELECTROLYTIC CAP ON VOUT
LOAD CURRENT (A)
0.001
0.01
0.1
1
3
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
VIN = 5V
VIN = 12V
VIN = 20V 500µs/DIV
LOAD STEP
2A/DIV
VOUT
500mV/DIV
IL1
5A/DIV
8711 TA03c
Efficiency vs Load Current Transient Response with 1A to 2.5A to 1A
Output Load Step (VIN=12V)
LT8711
32
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
200kHz, 4.5V–40V Input to 12V/4A SEPIC
VOUT
BIAS
INTVEE
BG
CSP
CSN
GND
2.2µF
2.2µF
C1
10µF ×3
RT 118k
49.9k
470nF
100pF
4.7nF TG
EN/FBIN
EXTVCC
VIN
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
1M
RFB2
71.5k
COUT
22µF
×3
VOUT
12V, 4A (VIN > 5V)
CIN
10µF
×2
VIN
4.5V TO
40V
LT8711
FB
VOUT
M1
M2
RSENSE2
2mΩ
L1
8.2µH
L2
15µH
RSENSE1
2mΩ
8711 TA04a
L1: COILCRAFT 8.2µH XAL1510-822ME
L2: COILCRAFT 15µH XAL1510-153ME
M1: VISHAY SiR826ADP
M2: ST STL42P6LLF6
CIN: 10µF, 50V, X7R
ADDITIONAL 56µF, 50V ELECTROLYTIC CAP ON VIN
COUT: 22µF, 25V, X7R
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON VOUT
ISP
ISN
LOAD CURRENT (A)
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V 500µs/DIV
LOAD STEP
2A/DIV
VOUT
500mV/DIV
IL1
5A/DIV
8711 TA04c
Efficiency vs Load Current Transient Response with 2A to 4A to 2A
Output Load Step (VIN=12V)
LT8711
33
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
200kHz, 5V–40V Input to 12V/3.5A ZETA Converter
BIAS
INTVEE
TG
ISN
ISP
CSP
CSN
2.2µF
2.2µF C1
10µF ×3
RT
118k
62k
330nF
100pF
1nF
BG
EN/FBIN
EXTVCC
VIN
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
1M
RFB2
69.8k
COUT
22µF ×4
VOUT
12V, 3.5A (VIN > 16V)
2.5A (9V < VIN < 16V)
1.5A (VIN < 9V)
CIN
10µF
×6
VIN
5V TO
40V
LT8711
FB
VOUT
RSENSE2
3.5mΩ
L1B
10µH
L1A
10µH
RSENSE1
3.5mΩ
8711 TA05a
L1: COILCRAFT 10µH MSD1583-103
M1: VISHAY SiR826ADP
M2: VISHAY Si7461DP
CIN: 10µF, 50V, X7R
ADDITIONAL 56µF, 50V ELECTROLYTIC CAP ON VIN
COUT: 22µF, 25V, X7R
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON VOUT
M1
M2
GND
CSP
CSN
CSP
CSN
LOAD CURRENT (A)
0.001
0.01
0.1
1
4
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
VIN = 6V
VIN = 12V
VIN = 24V
400µs/DIV
LOAD STEP
2A/DIV
VOUT
200mV/DIV
IL1
2A/DIV
8711 TA05c
Efficiency vs Load Current Transient Response with 1.5A to 3A to 1.5A
Output Load Step (VIN=16V)
LT8711
34
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
400kHz, 5V–40V Input to 12V/3.5A Buck-Boost Converter
BIAS
INTVEE
TG
BG
CSP
CSN
2.2µF
2.2µF
100pF
RT 60.4k
110k
330nF
100pF
2.2nF
ISN
ISP
GND
EN/FBIN
EXTVCC
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
1M
RSENSE2
4mΩ
RFB2
69.8k
COUT
100µF ×2
VOUT
12V, 3.5A (VIN >16V)
2.5A (9V < VIN < 16V)
1.5A (VIN < 9V)
CIN
10µF ×6
VIN
5V TO
40V
LT8711
FB
VIN
VOUT
M1
D1 L1
4.7µH D2
M2
RSENSE1
4mΩ
8711 TA06a
L1: COILCRAFT 4.7µH XAL8080-472ME
M1: ST STL60P4LLF6
M2: FAIRCHILD FDMC86520L
D1, D2: VISHAY SS10P6M3
CIN: 10µF, 50V, X7R
ADDITIONAL 47µF, 50V ELECTROLYTIC CAP ON VIN
COUT: 100µF, 16V, X7R
ADDITIONAL 390µF, 16V ELECTROLYTIC CAP ON VOUT
10nF 10nF
10Ω
10Ω
LOAD CURRENT (A)
0.001
0.01
0.1
1
3
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V 500µs/DIV
LOAD STEP
2A/DIV
VOUT
200mV/DIV
IL1
5A/DIV
8711 TA06c
Efficiency vs Load Current Transient Response with 1.5A to 3A to 1.5A
Output Load Step (VIN=9V)
LT8711
35
Rev A
For more information www.analog.com
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8711#packaging for the most recent package drawings.
FE20 (CB) TSSOP REV K 0913
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10
DETAIL A
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation CB
DETAIL A
0.60
(.024)
REF
0.28
(.011)
REF
LT8711
36
Rev A
For more information www.analog.com
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8711#packaging for the most recent package drawings.
3.00 ±0.10 1.50 REF
4.00 ±0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
19 20
1
2
BOTTOM VIEW—EXPOSED PAD
2.50 REF
0.75 ±0.05
R = 0.115
TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UDC20) QFN 1106 REV Ø
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
2.50 REF
3.10 ±0.05
4.50 ±0.05
1.50 REF
2.10 ±0.05
3.50 ±0.05
PACKAGE OUTLINE
R = 0.05 TYP
1.65 ±0.10
2.65 ±0.10
1.65 ±0.05
2.65 ±0.05
0.50 BSC
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
LT8711
37
Rev A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 04/18 Changed from 25mV to 27mV in last sentence. 13
LT8711
38
Rev A
For more information www.analog.com
ANALOG DEVICES, INC. 2017-2018
D16855-0-4/18(A)
www.analog.com
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LT3757A Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
3mm×3mm DFN-10 and MSOP-10E
LT3758A Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency,
3mm×3mm DFN-10 and MSOP-10E
LT3957A Boost, Flyback, SEPIC and Inverting Converter
with 5A, 40V Switch 3V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
5mm×6mm QFN
LT3958 Boost, Flyback, SEPIC and Inverting Converter
with 3.3A, 84V Switch 5V ≤ VIN ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency,
5mm×6mm QFN
LT8705A 80V VIN and VOUT Synchronous 4-Switch Buck-Boost
DC/DC Controller 2.8V ≤ VIN ≤ 80V, 100kHz to 400kHz Programmable Operating Frequency,
5mm×7mm QFN-38 and TSSOP-38
LT8709 Negative Input Synchronous Multitopology DC/DC
Control –80V ≤ VIN ≤ –4.5V, Up to 400kHz Programmable Operating Frequency,
TSSOP-20
LT8710 Synchronous SEPIC/Inverting/Boost Controller with
Output Current Control 4.5V ≤ VIN ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency,
TSSOP-20
LT8714 Bipolar Output Synchronous Controller with
Seamless Four Quadrant Operation 4.5V ≤ VIN ≤ 80V, Output Can Source or Sink Current for Any Output Voltage,
Switching Frequency Up to 750kHz, 20-Lead TSSOP
VOUT
BIAS
INTVEE
BG
GND
CSP
ISP
ISN
CSN
2.2µF
2.2µF
RT
100k
100k
330nF
100pF
2.2nF
TG
EN/FBIN
EXTVCC
VIN
OPMODE
INTVCC
RT
SYNC
SS
VC
RFB1
560k
RFB2
55k
COUT
22µF
×4
VOUT
9VMIN, 3A
CIN
10µF
×6
VIN
3V TO
36V
LT8711
FB
VOUT
M1
M2
D1
L1
5.6µH
RSENSE
3.5mΩ
8711 TA07a
L1: WÜRTH 5.6µH WE-HCI 7443557560
M1: FAIRCHILD FDS8447
M2: FAIRCHILD FDD4141
D1: FAIRCHILD MBRS340
CIN: 10µF, 50V, X7R
ADDITIONAL 56µF, 50V ELECTROLYTIC CAP ON VIN
COUT: 22µF, 25V, X7R
ADDITIONAL 270µF, 25V ELECTROLYTIC CAP ON VOUT
2Ω
2Ω
Boost Pre-Regulator for Automotive Stop-Start/Idle
INPUT VOLTAGE (V)
0
5
10
15
20
25
30
35
0
30
60
90
120
150
INPUT CURRENT (µA)
8711 TA07b
10ms/DIV
VOUT
5V/DIV
VIN
5V/DIV
0V
8711 TA07c
No-Load Supply Current Transient VIN and VOUT Waveforms