AS7C164L-12PC - Alliance Semiconductor

ALLIANCE SEMICONDUCTOR

High Performance

8K×8

CMOS SRAM

AS7C164

AS7C164L

8K×8 CMOS SRAM (Common I/O)

Features

• Organization: 8,192 words × 8 bits

•High speed

- 8/10/12/15/20 ns address access time

- 3/3/3/4/5 ns output enable access time

• Low power consumption

- Active: 633 mW max (10 ns cycle)

- Standby:11 mW max, CMOS I/O

1.1 mW max, CMOS I/O, L version

• Very low DC component in active power

• 2.0V data retention (L version)

• Equal access and cycle times

• Very fast 3 ns output enable access time

• Easy memory expansion with CE1, CE2, OE inputs

• TTL-compatible, three-state I/O

• 28-pin JEDEC standard packages

• 300 mil PDIP and SOJ

• ESD protection > 2000 volts

• Latch-up current > 200 mA

Logic block diagram

128×64×8

Array

(65,536)

Input buffer

A10

A11

A12

I/O0

I/O7

Vcc

GND

CE1

Column decoder

Row decoder

Control

Circuit

Sense amp

CE2

Pin arrangement

Vcc

CE2

A11

A10

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

A12

I/O0

I/O1

I/O2

GND

DIP, SOJ

AS7C164

Selection guide

7C164-8 7C164-10 7C164-12 7C164-15 7C164-20 Unit

Maximum address access time 8 10 12 15 20 ns

Maximum output enable access time 3 3 3 4 5 ns

Maximum operating current 120 115 110 100 90 mA

Maximum CMOS standby current 2.0 2.0 2.0 2.0 2.0 mA

L - 0.2 0.2 0.2 0.2 mA

AS7C164

AS7C164L

Functional description

The AS7C164 is a high performance CMOS 65,536-bit Static Random Access Memory (SRAM) organized as 8,192 words × 8

bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 8/10/12/15/20 ns with output enable access times (tOE) of 3/3/3/4/

5 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion

with multiple-bank memory systems.

When CE1 is HIGH or CE2 is LOW the device enters standby mode. The standard AS7C164 is guaranteed not to exceed 11.0

mW power consumption in standby mode; the L version is guaranteed not to exceed 1.1 mW, and typically requires only 250

µW. The L version also offers 2.0V data retention, with maximum power of 120 µW.

A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-

I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid

bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write

enable (WE).

A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE)

HIGH. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable

is inactive, or write enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C164 is packaged in all

high volume industry standard packages.

Absolute maximum ratings

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-

tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

Truth table

Key: X = Don’t Care, L = LOW, H = HIGH

Parameter Symbol Min Max Unit

Voltage on any pin relative to GND Vt–0.5 +7.0 V

Power dissipation PD–1.0W

Storage temperature (plastic) Tstg –55 +150 oC

Temperature under bias Tbias –10 +85 oC

DC output current Iout –20mA

CE1 CE2 WE OE Data Mode

HXXXHigh ZStandby (I

SB, ISB1)

XLXXHigh ZStandby (I

SB, ISB1)

L H H H High Z Output disable

LHHLD

out Read

LHLXD

in Write

AS7C164

AS7C164L

Recommended operating conditions Applicable to all portions of this specification unless otherwise noted.

DC operating characteristics

Capacitance f = 1 MHz, Ta = room temperature

Key to switching waveforms

* VIL min = –3.0V for pulse width less than tRC/2.

Parameter Symbol Min Typ Max Unit

Supply voltage VCC 4.5 5.0 5.5 V

GND 0.0 0.0 0.0 V

Input voltage VIH 2.2 – VCC+1 V

VIL –0.5*–0.8V

Ambient operating temperature Ta0–70

Parameter Symbol Test Conditions

-8 -10 -12 -15 -20

UnitMin Max Min Max Min Max Min Max Min Max

Input leakage

current |ILI|VCC = Max,

Vin = GND to VCC –1–1–1–1–1µA

Output

leakage

current |ILO|CE1 = VIH or CE2 = VIL,

VCC = Max,

Vout = GND to VCC

–1–1–1–1–1µA

Operating

power

supply

current

ICC CE1 = VIL, CE2 = VIH,

f = fmax, Iout = 0 mA

–120–115–110–100– 90mA

L – 110 – 110 – 105 – 95 – 95 mA

Standby

power

supply

current

ISB CE1 = VIH or CE2 = VIL,

f = fmax

–40–35–30–25–25mA

L–30–30–25–20–20mA

SB1

CE1 ≥ VCC–0.2V or CE2 ≤

0.2V,

Vin ≤ 0.2V or Vin ≥ VCC–

0.2V, f = 0

–2.0–2.0–2.0–2.0–2.0mA

L – 0.2 – 0.2 – 0.2 – 0.2 – 0.2 mA

Output

voltage

VOL IOL = 8 mA, VCC = Min –0.4–0.4–0.4–0.4–0.4V

OH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – 2.4 – V

Parameter Symbol Signals Test Conditions Max Unit

Input Capacitance CIN A, CE1, CE2, WE, OE Vin = 0V 5 pF

I/O Capacitance CI/O I/O Vin = Vout = 0V 7 pF

AAAA

AAA

AAAA

AAA

Undefined output/don’t care

AAAA

AAA

AAAA

AAA

Falling input

AAAA

AAA

AAAA

AAA

Rising input

AS7C164

AS7C164L

Read cycle

Timing waveform of read cycle 1 3, 6, 7, 9, 12 Address controlled

Timing waveform of read cycle 2 3, 6, 8, 9, 12 CE1 and CE2 controlled

Parameter Symbol

-8 -10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max Min Max

Read cycle time tRC 8 – 10 – 12 – 15 – 20 – ns

Address access time tAA – 8 – 10 – 12 – 15 – 20 ns 3

Chip enable (CE1) access time tACE1 – 8 – 10 – 12 – 15 – 20 ns 3, 12

Chip enable (CE2) access time tACE2 – 8 – 10 – 12 – 15 – 20 ns 3, 12

Output enable (OE) access time tOE –3–3–3–4–5ns

Output hold from address change tOH 3–3–3–3–3–ns

CE1 LOW to output in low Z tCLZ1 3–3–3–3–3–ns

4, 5, 12

CE2 HIGH to output in low Z tCLZ2 3–3–3–3–3–ns4, 5, 12

CE1 HIGH to output in high Z tCHZ1 –3–3–3–4–5ns

4, 5, 12

CE2 LOW to output in high Z tCHZ2 –3–3–3–4–5ns

4, 5, 12

OE LOW to output in low Z tOLZ 0–0–0–0–0–ns4, 5

OE HIGH to output in high Z tOHZ –3–3–3–4–5ns

4, 5

Power up time tPU 0–0–0–0–0–ns

4, 5, 12

Power down time tPD – 8 – 10 – 12 – 15 – 20 ns 4, 5, 12

AAAA

Address

Dout Data Valid

tOH

tAA

tRC

AAAA

current

Supply

CE2

Dout

tOE

tOLZ

tACE1, tACE2 tCHZ1, tCHZ2

tCLZ1, tCLZ2

tPU

tPD ICC

ISB

50% 50%

tOHZ

AAAA

AAA

Data Valid

AAAA

tRC1

CE1

AS7C164

AS7C164L

Write cycle

Timing waveform of write cycle 1 10, 11, 12 WE controlled

Timing waveform of write cycle 2 10, 11, 12 CE1 and CE2 controlled

Parameter Symbol

-8 -10 -12 -15 -20

Unit NotesMin Max Min Max Min Max Min Max Min Max

Write cycle time tWC 8 – 10 – 12 – 15 – 20 – ns

Chip enable (CE1) to write end tCW1 7–8–9–10–12–ns12

Chip enable (CE2) to write end tCW2 7–8–9–10–12–ns

Address setup to write end tAW 7–8–9–10–12–ns

Address setup time tAS 0–0–0–0–0–ns12

Write pulse width tWP 7–7–8–9–12–ns

Address hold from write end tAH 0–0–0–0–0–ns

Data valid to write end tDW 5–6–6–7–8–ns

Data hold time tDH 0–0–0–0–0–ns

4, 5

Write enable to output in high Z tWZ –5–5–5–5–5ns

4, 5

Output active from write end tOW 2–2–3–3–3–ns4, 5

tAW tAH

tWC

AAAA

Address

Dout

tDH

tOW

tDW

tWZ

tWP

tAS

Data Valid

Din

tAW

AAAA

AAA

Address

CE1

Dout

tCW1, tCW2

tWP

tDW tDH

tAH

tWZ

tWC

AAAA

AAA

tAS

CE2

Data ValidDin

AS7C164

AS7C164L

Data retention characteristics (L version)

Data retention waveform (L version)

AC test conditions

Notes

1During V

CC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.

2 This parameter is sampled and not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A, B, C.

CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.

5 This parameter is guaranteed but not tested.

6WE

is HIGH for read cycle.

7CE1

and OE are LOW and CE2 is HIGH for read cycle.

8 Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE1 or WE must be HIGH or CE2 LOW during address transitions.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1 and CE2 have identical timing.

Parameter Symbol Test Conditions Min Max Unit

VCC for data retention VDR VCC = 2.0V

CE1 ≥ VCC–0.2V or

CE2 ≤ 0.2V

2.0 – V

Data retention current ICCDR –60µA

Chip enable to data retention time tCDR 0–ns

Operation recovery time tRtRC –ns

AAAA

AAA

AAAA

AAA

CE1

tCDR

Data retention mode

4.5V 4.5V

VDR ≥ 2.0V

VIH VIH

VDR

255Ω

- Output load: see Figure B,

except for tCLZ and tCHZ see Figure C.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 5 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

5 pF*

480Ω

Dout

GND

+5V

168Ω

Thevenin equivalent:

Dout +1.728V

Figure C: Output Load for tCLZ, tCHZ

255Ω30 pF*

480Ω

Dout

GND

+5V

Figure B: Output Load

*including scope

10%

90%

10%

90%

GND

+3.0V

Figure A: Input Waveform

and jig capacitance

AS7C164

AS7C164L

Typical DC and AC characteristics

Supply voltage (V)

4.0 5.5 6.0

5.04.5

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply current ICC, ISB

Ambient temperature (°C)

–55 80 125

35–10

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply current ICC, ISB

vs. ambient temperature Ta

vs. supply voltage VCC

ICC

ISB

ICC

ISB

Ambient temperature (°C)

-55 80 125

35-10

0.2

0.04

625

Normalized ISB1 (log scale)

Normalized supply current ISB1

vs. ambient temperature Ta

VCC = 5.0V

Supply voltage (V)

4.0 5.5 6.0

5.04.5

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Normalized access time

Normalized access time tAA

Ambient temperature (°C)

–55 80 125

35–10

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Normalized access time

Normalized access time tAA

Cycle frequency (MHz)

075

100

5025

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC

Normalized supply current ICC

vs. ambient temperature Tavs. cycle frequency 1/tRC, 1/tWC

vs. supply voltage VCC

VCC = 5.0V

Ta = 25°C

VCC = 5.0VTa = 25°C

Output voltage (V)

0.0 3.75 5.0

2.51.25

100

120

140

Output source current (mA)

Output source current IOH

Output voltage (V)

0.0 3.75 5.0

2.51.25

Output sink current (mA)

Output sink current IOL

Capacitance (pF)

0750

1000

500250

Change in tAA (ns)

Typical access time change ∆tAA

vs. output voltage VOL vs. output capacitive loadingvs. output voltage VOH

100

120

140

VCC = 5.0V

Ta = 25°C

VCC = 5.0V

Ta = 25°C

VCC = 4.5V

ALLIANCE SEMICONDUCTOR

3099 North First Street San Jose, CA 95134

(408) 383-4900 Fax (408) 383-4999

AS7C164

AS7C164L

Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a

committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not

authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion® and the Alliance logo are registered trademarks

of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.

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Ordering codes

Part numbering system

Representatives, distributors, and sales offices

Package \ Access Time 8 ns 10 ns 12 ns 15 ns 20 ns

Plastic DIP, 300 mil -

AS7C164-10PC

AS7C164L-10PC

AS7C164-12PC

AS7C164L-12PC

AS7C164-15PC

AS7C164L-15PC

AS7C164-20PC

AS7C164L-20PC

Plastic SOJ, 300 mil AS7C164-8JC

AS7C164-10JC

AS7C164L-10JC

AS7C164-12JC

AS7C164L-12JC

AS7C164-15JC

AS7C164L-15JC

AS7C164-20JC

AS7C164L-20JC

AS7C 164 X –XX X C

SRAM Prefix Device

number

Blank = standard power

L = low power

Access

time

Package code:

P = PDIP 300 mil

J = SOJ 300 mil

Commercial temperature

range, 0°C to 70 °C