FUJITSU SEMICONDUCTOR DATA SHEET DS07-16705-1E 32-bit Proprietary Microcontrollers CMOS FR60 MB91319R Series MB91316/316A/F318R/F318S/FV319R DESCRIPTION The MB91319R series is the microcontrollers which use a high-performance 32-bit RISC-CPU and contains various types of I/O resources for the embedded control that requires high-performance and high-speed CPU processing. It is suitable for the embedded control in TV or PDP, requiring high-performance CPU processing power. This product is one of the FR60* family based on the FR30/40 family CPU with enhanced bus access. It is applicable to faster-speed application. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited. FEATURE * FR CPU * 32-bit RISC, load/store architecture with a five-stage pipeline * Operating frequency : 40 MHz (Use of PLL : Oscillation 10 MHz) * 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle * Embedded application optimized instructions : Memory-to-memory transfer, bit processing, barrel shift, and other instructions. * High-level language support instructions : Function entry/exit instructions, multiple register load/store instructions. * Register interlock functions: Facilitating coding in assemblers * Built-in multiplier with instruction-level support 32-bit multiplication with sign : 5 cycles 16-bit multiplication with sign : 3 cycles (Continued) Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright(c)2006 FUJITSU LIMITED All rights reserved MB91319R Series * * * * Interrupt (PC, PS save) : 6 cycles, 16 priority levels Harvard architecture allowing program access and data access to be executed simultaneously Instruction prefetch function implemented by a four-word queue in the CPU Instruction compatible with FR family * Bus interface This bus interface is used for internal macro IF (USB, OSDC) * CS1, CS2, and CS3 areas are connected as following : CS1 area : Reserved, CS2 area : USB function, CS3 area : OSDC * Built-in memory Memory RAM Memory for program Memory for font MB91FV319R MB91F318R/F318S MB91316/316A 48 Kbytes 48 Kbytes 32 Kbytes Flash memory : 1 Mbyte Flash memory : 1 Mbyte MASK ROM : 512 Kbytes Flash memory : 512 Kbytes MASK ROM : 384 Kbytes MASK ROM : 384 Kbytes * DMAC (DMA Controller) * 5 channels (ch.0 and ch.1 are connected to USB function. ) * Two transfer sources (internal peripherals/software) * Specifying of addressing mode 32-bit full address (increased/decreased/fixed) * Transfer modes (demand transfer, burst transfer, step transfer, block transfer) * Selectable transfer data size : 8, 16, or 32-bits * Bit search module (for REALOS) * Search for the position of the bit "1"/"0"-changed first in one word from the MSB * Reload timer (including a channel for REALOS) * 16-bit timer: 3 channels * The internal clock is selectable from 2/8/32 divisions. * UART * Full-duplex double buffer * 5 channels * Selectable parity ON/OFF * Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable * Built-in timer for dedicated baud rate * External clock can be used as transfer clock. * Assorted error detection functions (for parity, frame, and overrun errors) (Continued) 2 MB91319R Series * I2C Interface * * 4 channels (built-in bridge function) * Master/slave sending and receiving * Clock synchronization function * Detecting transmitting direction function * Bus error detection function * Standard mode (Max 100 kbps) /High speed mode (Max 400 kbps) supported * Built-in FIFO function with 16-byte data each for transmit/receive * Arbitration function * Slave address and general call address detection function * Start condition repeated generation and detection * 10-bit/7-bit slave address * Interrupt controller * Total of external interrupt pin is 5. (one non-maskable interrupt pin (NMI) and four normal interrupt pins (INT3 to INT0) ) * Interrupt from internal peripheral * Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt * At the STOP, available use for Wake Up * A/D converter * 10-bit resolution, 10 channels * Successive approximation type converter. Conversion time: Approx. 10 s * Conversion modes (one-shot conversion mode, scanning conversion mode) * Activation trigger (software / external trigger) * PPG * 4 channels are incorporated. * 16-bit down counter, 16-bit data register with buffer for setting cycles * The internal clock is selectable from 1/4/16/64 divisions. * PWC * 1 channel (1 input) is incorporated. * 16-bit up counter * Easy digital low pass filter * Multi function timer * 4 channels are incorporated. * Low pass filter eliminating noise below the clock setting * Capable of pulse width measurement according to fine settings using seven types of clock signals * Event count function from pin input * Interval timer function using seven kinds of clock and external input clock * USB function * Full speed * double buffer of USB2.0 version * CONTROL IN/OUT, BULK IN/OUT, INTERRUPT IN (Continued) 3 MB91319R Series (Continued) * OSDC function * RGB: each 3 bits (16 colors available among 512 colors) * Analog RGB output: Max 50 MHz * Digital RGB output: Max 90 MHz * A font in 24 x 32 dots can be displayed up to 80 x 32. * Two-layered display of MAIN/CC (Font in CC layer is fixed at 18 dots in horizontal axis) * 4096 characters at the maximum (including 16 characters for font RAM) * Closed caption decoder function * 2 channels are incorporated. * CC decode function * ID-1 (480i/480p) decode function * PLL for video clock * 3 PLLs generating dot clock and VBI clock * Other interval timer * 16-bit timer : 3 channels * Watchdog timer * I/O port * Max 88 ports * Other features * Built-in oscillation circuit as clock source * INIT is prepared as a reset pin. * Watchdog timer reset and software reset are also available. * Stop mode and sleep mode are supported as low-power consumption mode. * Gear function * Built-in time-base timer * Package : LQFP-176, 0.5mm pitch, 24 mm x 24 mm * CMOS technology : 0.18 m * Power supply voltage : 3.3 V 0.3 V, 1.8 V 0.15 V 2-power supply * : "Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips." 4 MB91319R Series PIN ASSIGNMENT 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VSYNC DCKI DCKO FH VOB1 VOB2 VDDI R2 R1 R0 G2 G1 G0 B2 B1 B0 UDP UDM VDDE X0B VSS X1B VDDI PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 P17 P16/ATRG P15/PPG3 P14/PPG2 P13/PPG1 P12/PPG0 P11/TMO3 P10/TMO2 P07/TMO1 P06/TMO0 P05/TO2 P04/TO1 P03/TO0 (TOP VIEW) HSYNC1 HSYNC2 HSYNC3 VDDE VSS VGS1/VCI1 CPO1 VSSP1 VDDP1 VGS2/VCI2 CPO2 VSSP2 VDDP2 VGS3/VCI3 CPO3 VSSP3 VDDP3 VDDR VREF VR0 ROUT VSSR VDDG GOUT VSSG VDDB BOUT VSSB VIN0 VIN1 VDDIS VSSS VDDI AVCC AVRH AVSS/AVRL PC0/AN0 PC1/AN1 PC2/AN2 PC3/AN3 PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 P02/SCK4/TIN2 P01/SO4/TIN1 P00/SI4/TIN0 P74 P73 P72 P71 P70 VDDE VSS VDDI P57 P56 P55 P54 P53 P52/SCK3 P51/SO3 P50/SI3 P47/SCK2 P46/SO2 P45/SI2 P44/SDA4 P43/SDA3 P42/SCL4 P41/SCL3 P40/SDA2 P37/SCL2 P36/TRG3 P35/TRG2 P34/TRG1 P33/TRG0 NMI PA2/INT3 PA1/INT2 PA0/INT1 VDDI X1A VSS X0A VDDE P97/INT0 P96/TMI3 P95/TMI2 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 P94/TMI1 P93/TMI0 P92/RIN P91/SCK1 P90/SO1 P87/SI1 P86/SCK0 P85/SO0 P84/SI0 P83/SDA1 P82/SCL1 P81/SDA0 P80/SCL0 INIT MD3 MD2 MD1 MD0 ICD3 ICD2 ICD1 ICD0 ICS2 ICS1 ICS0 IBREAK ICLK TRST VDDI X1 VSS X0 VDDE P32 P31 P30 P27 P26 P25 P24 P23 P22 P21/AN9 P20/AN8 (FPT-176P-M07) 5 MB91319R Series PIN DESCRIPTION Pin No. Pin Name I/O Circuit type* Function 1 HSYNC1 G Vertical synchronous input 1 2 HSYNC2 G Vertical synchronous input 2 3 HSYNC3 G Vertical synchronous input 3 4 VDDE I/O power supply 5 VSS Ground 6 VGS1/VCI1 Guard band ground 7 CPO1 K Charge pump output 8 VSSP1 Dot clock PLL ground 9 VDDP1 Dot clock PLL power supply 10 VGS2/VCI2 Guard band ground 11 CPO2 K Charge pump output 12 VSSP2 Dot clock PLL ground 13 VDDP2 Dot clock PLL power supply 14 VGS3/VCI3 Guard band ground 15 CPO3 K Charge pump output 16 VSSP3 Dot clock PLL ground 17 VDDP3 Dot clock PLL power supply 18 VDDR D/A power supply for R 19 VREF K Power supply reference input 20 VR0 K Resistor connection pin 21 ROUT K R output (analog) 22 VSSR D/A ground for R 23 VDDG D/A power supply for G 24 GOUT K G output (analog) 25 VSSG D/A ground for G 26 VDDB D/A power supply for B 27 BOUT K B output (analog) 28 VSSB D/A ground for B 29 VIN0 K Data slicer input 0 30 VIN1 K Data slicer input 1 31 VDDIS Data slicer power supply 32 VSSS Data slicer ground 33 VDDI Internal logic power supply 34 AVCC A/D power supply 35 AVRH A/D reference power supply (Continued) 6 MB91319R Series Pin No. Pin Name I/O Circuit type* 36 AVSS/AVRL 37 38 39 40 41 42 43 44 45 46 PC0 AN0 PC1 AN1 PC2 AN2 PC3 AN3 PC4 AN4 PC5 AN5 PC6 AN6 PC7 AN7 P20 AN8 P21 AN9 E E E E E E E E E E Function A/D ground General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input 47 P22 C General-purpose port 48 P23 C General-purpose port 49 P24 C General-purpose port 50 P25 C General-purpose port 51 P26 C General-purpose port 52 P27 C General-purpose port 53 P30 C General-purpose port 54 P31 C General-purpose port 55 P32 C General-purpose port 56 VDDE 3.3 V power supply 57 X0 A 10 MHz oscillation pin 58 VSS Ground 59 X1 A 10 MHz oscillation pin 60 VDDI Internal logic power supply (Continued) 7 MB91319R Series Pin No. Pin Name I/O Circuit type* Function 61 TRST B DSU tool reset (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 62 ICLK M DSU clock (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 63 IBREAK L DSU break (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 64 ICS0 O DSU status (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 65 ICS1 O DSU status (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 66 ICS2 O DSU status (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 67 ICD0 P DSU data (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 68 ICD1 P DSU data (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 69 ICD2 P DSU data (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 70 ICD3 P DSU data (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) 71 MD0 F Mode pin 72 MD1 F Mode pin 73 MD2 F Mode pin 74 MD3 L Mode pin 75 INIT B Initial (reset) pin 76 77 78 79 80 81 P80 SCL0 P81 SDA0 P82 SCL1 P83 SDA1 P84 SI0 P85 SO0 J J J J C C General-purpose port I2C clock pin General-purpose port I2C data pin General-purpose port I2C clock pin General-purpose port I2C data pin General-purpose port UART0 serial input General-purpose port UART0 serial output (Continued) 8 MB91319R Series Pin No. 82 83 84 85 86 87 88 89 90 91 Pin Name P86 SCK0 P87 SI1 P90 SO1 P91 SCK1 P92 RIN P93 TMI0 P94 TMI1 P95 TMI2 P96 TMI3 P97 INT0 I/O Circuit type* C C C C C C C C C O Function General-purpose port UART0 clock input/output General-purpose port UART1 serial input General-purpose port UART1 serial output General-purpose port UART1 clock input/output General-purpose port PWC input General-purpose port Multi-functional timer 0 input General-purpose port Multi-functional timer 1 input General-purpose port Multi-functional timer 2 input General-purpose port Multi-functional timer 3 input General-purpose port External interrupt input 0 92 VDDE 3.3 V power supply 93 X0A A 32 kHz oscillation pin 94 VSS Ground 95 X1A A 32 kHz oscillation pin 96 VDDI Internal logic power supply 97 98 99 100 101 PA0 INT1 PA1 INT2 PA2 INT3 NMI P33 TRG0 O O O B C General-purpose port External interrupt input 1 General-purpose port External interrupt input 2 General-purpose port External interrupt input 3 NMI input General-purpose port PPG0 trigger input (Continued) 9 MB91319R Series Pin No. 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 Pin Name P34 TRG1 P35 TRG2 P36 TRG3 P37 SCL2 P40 SDA2 P41 SCL3 P42 SCL4 P43 SDA3 P44 SDA4 P45 SI2 P46 SO2 P47 SCK2 P50 SI3 P51 SO3 P52 SCK3 I/O Circuit type* C C C N N N N N N C C C C C C Function General-purpose port PPG1 trigger input General-purpose port PPG2 trigger input General-purpose port PPG3 trigger input General-purpose port I2C clock pin General-purpose port I2C data pin General-purpose port I2C clock pin General-purpose port I2C clock pin General-purpose port I2C data pin General-purpose port I2C data pin General-purpose port UART2 serial input General-purpose port UART2 serial output General-purpose port UART2 clock output General-purpose port UART3 serial input General-purpose port UART3 serial output General-purpose port UART3 clock output 117 P53 C General-purpose port 118 P54 C General-purpose port 119 P55 C General-purpose port 120 P56 C General-purpose port 121 P57 C General-purpose port (Continued) 10 MB91319R Series Pin No. Pin Name I/O Circuit type* 122 VDDI Internal logic power supply 123 VSS Ground 124 VDDE 3.3 V power supply 125 P70 C General-purpose port 126 P71 C General-purpose port 127 P72 C General-purpose port 128 P73 C General-purpose port 129 P74 C General-purpose port P00 130 131 132 SI4 General-purpose port C 134 135 136 137 138 139 140 141 UART4 serial input TIN0 Reload timer 0 trigger input P01 General-purpose port SO4 C UART4 serial output TIN1 Reload timer 1 trigger input P02 General-purpose port SCK4 C TIN2 133 Function P03 TO0 P04 TO1 P05 TO2 P06 TMO0 P07 TMO1 P10 TMO2 P11 TMO3 P12 PPG0 P13 PPG1 UART4 clock input Reload timer 2 trigger input C C C C C C C C C General-purpose port Reload timer 0 output General-purpose port Reload timer 1 output General-purpose port Reload timer 2 output General-purpose port Multi-functional timer 0 output General-purpose port Multi-functional timer 1 output General-purpose port Multi-functional timer 2 output General-purpose port Multi-functional timer 3 output General-purpose port PPG0 output General-purpose port PPG1 output (Continued) 11 MB91319R Series (Continued) Pin No. 142 143 144 Pin Name P14 PPG2 P15 PPG3 P16 ATRG I/O Circuit type* C C C Function General-purpose port PPG2 output General-purpose port PPG3 output General-purpose port A/D conversion trigger input 145 P17 C General-purpose port 146 PB0 C General-purpose port 147 PB1 C General-purpose port 148 PB2 I General-purpose port 149 PB3 C General-purpose port 150 PB4 C General-purpose port 151 PB5 C General-purpose port 152 PB6 H General-purpose port 153 PB7 C General-purpose port 154 VDDI Internal power supply 155 X1B A 48 MHz oscillation pin 156 VSS Ground 157 X0B A 48 MHz oscillation pin 158 VDDE 3.3 V power supply 159 UDM 160 UDP 161 B0 D RGB digital output 162 B1 D RGB digital output 163 B2 D RGB digital output 164 G0 D RGB digital output 165 G1 D RGB digital output 166 G2 D RGB digital output 167 R0 D RGB digital output 168 R1 D RGB digital output 169 R2 D RGB digital output 170 VDDI Internal logic power supply 171 VOB2 D Translucent color period output 172 VOB1 D OSD display period output 173 FH D Horizontal synchronous output 174 DCKO D Dot clock output 175 DCKI G Dot clock input 176 VSYNC G Vertical synchronous output USB USB function USB function * : For the I/O circuit type, refer to " I/O CIRCUIT TYPE". 12 MB91319R Series I/O CIRCUIT TYPE Type Circuit type Remarks X1 Clock input A * Oscillation circuit * Feedback resistance X0 : 1 M X0A : 10 M X0 Standby control P-ch * CMOS level hysteresis input * With pull-up resistor P-ch N-ch B Digital input * CMOS level output * CMOS level hysteresis input * With standby control P-ch Digital output N-ch Digital output C Digital input Standby control (Continued) 13 MB91319R Series Type Circuit type Remarks * 2.5 V CMOS level output * CMOS level hysteresis input * With standby control 2.5 V P-ch Digital output N-ch D Digital output Digital input Standby control P-ch Digital output * * * * CMOS level output CMOS level hysteresis input With standby control With analog input switch N-ch Digital output E Analog input Control Digital input Standby control * CMOS level input * Without standby control P-ch F N-ch Digital input (Continued) 14 MB91319R Series Type Circuit type Remarks * CMOS level hysteresis input * Without standby control P-ch N-ch G Digital input Pull-down control P-ch Digital output * * * * CMOS level output CMOS level hysteresis input With standby control With pull-down resistor * * * * CMOS level output CMOS level hysteresis input With standby control With pull-up resistor N-ch Digital output N-ch H Digital input Standby control P-ch P-ch Digital output N-ch Digital output I Digital input Standby control (Continued) 15 MB91319R Series Type Circuit type Remarks * Open drain output * CMOS level hysteresis input * With standby control P-ch Open drain control N-ch J Digital output Digital input Standby control Analog pin P-ch K N-ch Analog input or Analog output * CMOS level hysteresis input * With pull-down resistor P-ch L N-ch N-ch Digital input CMOS level output P-ch Digital output M N-ch Digital output (Continued) 16 MB91319R Series Type Circuit type Remarks P-ch Open drain control * * * * 3 ports for I2C CMOS level hysteresis input CMOS level output With stop control N-ch Digital output Digital input } Control Digital input Control Open drain control N P-ch Digital output N-ch Digital input P-ch Open drain control N-ch Digital output * CMOS level output * CMOS level hysteresis input * Without standby control P-ch Digital output O N-ch Digital output Digital input (Continued) 17 MB91319R Series (Continued) Type Circuit type Remarks P-ch Digital output P N-ch N-ch Digital output Digital input 18 * * * * CMOS level output CMOS level hysteresis input Without standby control With pull-down resistor MB91319R Series HANDLING DEVICES * Preventing a Latch-up A latch-up can occur on a CMOS IC under following conditions. A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. - When a voltage higher than VDDE or VDDI or a voltage lower than VSS is applied to an input or output pin. - When a voltage higher than the rating is applied between VDDE or VDDI and VSS. * Handling of Unused Input Pins Do not leave an unused input pin open since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. * Power Supply Pins If more than one VDDE or VDDI or VSS pin exists, those that must be kept at the same potential are designed to be connected to one other inside the device to prevent malfunctions such as latch-up. Be sure to connect the pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation, prevent strobe signal malfunctions due to an increase in ground level, and conform to the total output current rating. Given consideration to connecting the current supply source to VDDE or VDDI and VSS pin of the device at the lowest impedance possible. It is also recommended that a ceramic capacitor of around 0.1 F be connected between VDDE or VDDI and VSS pin at circuit points close to the device as a bypass capacitor. * Crystal Oscillation Circuit Noise near the X0 or X1 pin may cause the device to malfunction. Design printed circuit boards so that X0, X1, the quartz oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as near to one another as possible. It is strongly recommended that printed circuit board artwork that surrounds the X0 and X1 pins with ground be used to increase the expectation of stable operation. Please ask the Oscillation maker to evaluate the oscillational characteristics of the crystal and this device. * Mode Pins (MD0 to MD3) In order to prevent mistakes due to noise, and sending them into test mode, connect these pins as close to VDDE and VSS pins, and at as low an impedance as possible. * Tool Reset Pins (TRST) Be sure to input the same signal as the INIT when this pin is not used for the tool. The same processing is executed for the mass product. * Power-on Immediately after power-on, be sure to apply setting initialization reset (INIT) with INIT pin. Also immediately after power-on, keep the INIT pin at the "L" level until the oscillator has reached the required oscillation stabilization wait time. (For initialization by INIT from the INIT pin, the oscillation stabilization wait time is set to the minimum value.) * Source Oscillation Input at Power-on At power-on, be sure to input a source clock until the oscillation stabilization wait time is reached. 19 MB91319R Series * Precautions at Power-On/Power-Off * Precautions when turning on and off VDDI pin and VDDE pin To ensure the reliability of LSI devices, do not continuously apply only VDDE pin for about a minute when VDDI is off. When VDDE pin is changed from off to on, the power noise may make it impossible to retain the internal state of the circuit. Power-on : Supply voltage of VDDI pin analog Supply voltage of VDDE pin signal Power-off : Signal Supply voltage of VDDE pin analog Supply voltage of VDDI pin * Indeterminate Output when the Power is Turned On When turning on the power, the output pin may remain indeterminate until internal power supply becomes stable. * Clock About the attention when the external clock is used When the external clock is used, in principle, supply a clock signal to the X0 (X0A, X0B) pin and an oppositephase clock signal to the X1 (X1A, X1B) pin at the same time. However, in this case the stop mode (oscillator stop mode) must not be used (This is because, in STOP mode, the X1 (X1A, X1B) pin stops at "H" output) . At 12.5 MHz or less, the device can be used with the clock signal supplied only to the X0 (X0A, X0B) pin. * Using an External Clock (normal) X0, X0A, X0B X1, X1A, X1B MB91319R Series Note: The STOP mode (oscillation stop mode) cannot be used. * Using an External Clock (available at 12.5 MHz or less) X0, X1A, X1A OPEN X1, X1A, X1B MB91319R Series Note : The X1 (X1A, X1B) pin must be designed to have a delay within 15 ns, at 10 MHz, from the signal to the X0 (X0A, X0B) pin. 20 MB91319R Series * Restrictions Common in MB91319R series (1) Clock control block Take the oscillation stabilization wait time during Low level input to the INIT pin. (2) Bit Search Module The 0-detection data register (BSD0) , 1-detection data register (BSD1) , and transition-detection data register (BSDC) are only word-accessible. (3) I/O port Ports are accessed only in bytes. (4) Low-power Consumption Mode * Be sure to use the following sequence to enter standby mode if synchronous standby mode is being used (the SYNCS bit (bit 8) of the TBCR (timebase counter control register) is set) : (LD1 #value_of_stanby, R0) (LD1 #_STCR, R12) STB R0, @R12 ; Write to standby control register (STCR) LDUB @R12, R0 ; STCR read for synchronous standby LDUB @R12, R0 ; Dummy re-read of STCR NOP ; NOP x 5 for adjusted timing NOP NOP NOP NOP (5) Notes on the PS register The PS register is processed prior to the execution of some instructions, which may cause the exception handling described below to trigger breakpoints in interrupt processing routines or to update the displayed contents of the PS register when the debugger is being used. In all of these situations, because the microcontroller has been designed to correctly perform reprocessing after returning from an EIT, the operation before and after the EIT is performed according to the specifications. * The following operations are performed if, in the instruction immediately before a DIVOU or DIVOS instruction, a user interrupt or an NMI occurs, single-step execution is performed, or break is selected from the emulator menu. (1)The D0 and D1 flags are updated in advance. (2)An EIT handling routine (user interrupt, NMI, or emulator) is executed. (3)Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as in (1) . * If the any of the ORCCR, STILM, MOV Ri or PS instructions is executed in order to enable interrupts when a user interrupt source or NMI source is in the interrupt occurred state, the following operations are performed. (1)The PS register is updated in advance. (2)An EIT handling routine (user interrupt and NMI) is executed. (3)Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1) . 21 MB91319R Series (6) Watchdog timer The watchdog timer that is built into this product monitors the program to see if it performs a reset delay operation within a fixed period of time. And, that resets the CPU if the reset delay operation is not performed due to a runaway program. As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops program execution. A watchdog reset may not be generated in the above situation caused by the system running out of control. In that case, reset (INIT) by external INIT pin. (7) Notes on using A/D The MB91319R series has built-in A/D converter. Do not supply a voltage higher than VDDE to the AVCC. * Software reset in synchronous mode When software reset in the synchronous mode is used, the following two conditions must be satisfied before setting the SRST bit of the STCR (standby control register) to 0. - Set the interrupt enable flag (I-Flag) to the interrupt disabled (I-Flag = 0). - Do not use NMI. (8) Simultaneous generation of software break and user interrupt/NMI (only for MB91FV319R) If a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may cause the following phenomena. * The debugger stops pointing to a location other than the programmed breakpoints. * The halted program is not re-executed correctly. If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has been used, avoid setting any break at the relevant location. (9) Step execution of RETI instruction In an environment where interrupts frequently occur during single-step execution, only the relevant interrupt processing routines are executed repeatedly during single-step execution of the RETI instruction. This will prevent the main routine and low-interrupt-level programs from being executed. To avoid it, do not singlestep RETI instructions. When the relevant interrupt routine no longer requires being debugged, disable the relevant interrupt and perform debugging. (10) About an operand break Do not apply a data event break to access to the area containing the address of a stack pointer. (11) Example of batch file for configuration To debug a program downloaded to internal RAM, be sure to execute the following batch file after executing RESET. #----------------------------------------------------------------------------------#Set MODR (0x7fd) = Enable In memory + 16-bit External Bus set mem/byte 0x7fd = 0x5 #---------------------------------------------------------------------------------(12) Address in the built-in Flash/ROM area (Flash memory for program : 1 Mbyte product) The address 0X0017FFF8 in the built-in Flash/ROM area has been reserved. You must configure the FE. 22 MB91319R Series BLOCK DIAGRAM FR60 CPU core 32 32 Flash 1 Mbyte*1 MASK ROM 512 Kbytes*1 Bit search RAM EVA, Flash 48 Kbytes, MASK ROM 32 Kbytes Bus Converter 32 to 16 Adapter External I/F DMAC 5 channels USB function Font Flash Clock control Interrupt controller Flash 512 Kbytes*2 MASK ROM 384 Kbytes*2 OSDC UART 5 channels I2C 4 channels A/D converter 10 channels PWC 1 channel PPG 4 channels Reload timer 3 channels CC Decoder 2 channels External interrupt Ports Multi-function 4 channels *1 : MB91FV319R and MB91F318R/F318S contain the program ROM of 1 Mbyte flash memory, and MB91316/316A contain that of 512 Kbytes MASK ROM. *2 : MB91FV319R contains the font ROM of 512 Kbytes flash memory, and MB91F318R/F318S, MB91316/316A contain that of 384 Kbytes MASK ROM. 23 MB91319R Series MEMORY SPACE The FR family has 4 GB of logical address space (232 addresses) available to the CPU by linear access. * Direct Addressing Areas The following address space area is used for I/O. This area is called the direct addressing area. The addresses of operands in this area may be specified directly in an instruction. The direct addressing area varies depending on the size of the data being accessed as follows. Byte data access : 000H to 0FFH Half word data access : 000H to 1FFH Word data access : 000H to 3FFH * Memory Map Single-chip mode 0000 0000H I/O 0000 0400H I/O 0001 0000H 0002 F800H 0003 C000H 0004 0000H 0005 0000H 0006 0000H Access prohibited Font RAM Built-in RAM*1 Access prohibited Access prohibited USB function 0007 0000H OSDC 0008 0000H 0018 0000H Flash ROM 1 1 Mbytes*2 Flash ROM 2 512 Kbytes*3 0020 0000H Access prohibited FFFF FFFFH *1 : Built-in RAM area of MB91F318R/F318S, MB91FV319R is 0003 4000H to 0003 FFFFH (48 Kbytes) . Built-in RAM area of MB91316/316A is 0003 8000H to 0003 FFFFH (32 Kbytes) . *2 : MB91316/316A is 0008 0000H to 000F FFFFH (MASK ROM 512 Kbytes). *3 : MB91F318R/F318S and MB91316/316A are 0018 0000H to 001F FFFFH (MASK ROM 384 Kbytes) . 24 MB91319R Series I/O MAP This shows the correspondence between the memory space area and various peripheral resource registers. [How to read the table] Register Address 00000000H +0 +1 +2 +3 PDR0 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR3 [R/W] XXXXXXXX Block T-unit Port Data Register Read/Write attribute Initial value of register after a reset Register name (First-column register at address 4n; second-column register at address 4n + 2) Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data.) Note : Initial values of register bits are represented as follows : "1" : Initial Value "1" "0" : Initial Value "0" "X" : Initial Value "X" " - " : No physical register at this location Address Register +0 +1 +2 +3 000000H to 00000FH 000010H PDR0[R/W] XXXXXXXX PDR1[R/W] XXXXXXXX PDR2[R/W] XXXXXXXX PDR3[R/W] XXXXXXXX 000014H PDR4[R/W] XXXXXXXX PDR5[R/W] XXXXXXXX PDR7[R/W] --XXXXXX 000018H PDR8[R/W] XXXXXXXX PDR9[R/W] XXXXXXXX PDRA[R/W] -----XXX PDRB[R/W] XXXXXXXX 00001CH PDRC[R/W] XXXXXXXX 000020H ADCTH[R/W] XXXXXX00 ADCTL[R/W] 00000X00 Block Reserved R-bus Port Data Register ADCH[R/W] 00000000 00000000 000024H ADAT0[R] XXXXXX00 00000000 ADAT1[R] XXXXXX00 00000000 000028H ADAT2[R] XXXXXX00 00000000 ADAT3[R] XXXXXX00 00000000 00002CH ADAT4[R] XXXXXX00 00000000 ADAT5[R] XXXXXX00 00000000 000030H ADAT6[R] XXXXXX00 00000000 ADAT7[R] XXXXXX00 00000000 10-bit A/D Converter (Continued) 25 MB91319R Series Address Register Block +0 +1 +2 +3 000034H to 00003CH 000040H EIRR [R/W] 00000000 ENIR [R/W] 00000000 ELVR [R/W] 00000000 Ext int 000044H DICR [R/W] -------0 HRCL [R/W] 0--11111 DLYI/I-unit TMRLR0 [W] XXXXXXXX XXXXXXXX TMR0 [R] XXXXXXXX XXXXXXXX 00004CH TMCSR0 [R/W] ----0000 00000000 000050H TMRLR1 [W] XXXXXXXX XXXXXXXX TMR1 [R] XXXXXXXX XXXXXXXX 000054H TMCSR1 [R/W] ----0000 00000000 000058H TMRLR2 [W] XXXXXXXX XXXXXXXX TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R/W] ----0000 00000000 000048H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H SSR0 [R/W] 00001-00 SIDR0 [R/W] XXXXXXXX UTIM0 [R] (UTIMR [W]) 00000000 00000000 SSR1 [R/W] 00001-00 SIDR1 [R/W] XXXXXXXX UTIM1 [R] (UTIMR [W]) 00000000 00000000 SSR2 [R/W] 00001-00 SIDR2 [R/W] XXXXXXXX UTIM2 [R] (UTIMR [W]) 00000000 00000000 SSR3 [R/W] 00001-00 SIDR3 [R/W] XXXXXXXX UTIM3 [R] (UTIMR [W]) 00000000 00000000 SSR4 [R/W] 00001-00 SIDR4 [R/W] XXXXXXXX UTIM4 [R] (UTIMR [W]) 00000000 00000000 Reserved Reload Timer 0 Reload Timer 1 Reload Timer 2 SCR0 [R/W] 00000100 SMR0 [R/W] 00--0-0- UART0 DRCL0 [W] -------- UTIMC0 [R/W] 0--00001 U-TIMER 0 SCR1 [R/W] 00000100 SMR1 [R/W] 00--0-0- UART1 DRCL1 [W] -------- UTIMC1 [R/W] 0--00001 U-TIMER 1 SCR2 [R/W] 00000100 SMR2 [R/W] 00--0-0- UART2 DRCL2 [W] -------- UTIMC2 [R/W] 0--00001 U-TIMER 2 SCR3 [R/W] 00000100 SMR3 [R/W] 00--0-0- UART3 DRCL3 [W] -------- UTIMC3 [R/W] 0--00001 U-TIMER 3 SCR4 [R/W] 00000100 SMR4 [R/W] 00--0-0- UART4 DRCL4 [W] -------- UTIMC4 [R/W] 0--00001 U-TIMER 4 (Continued) 26 MB91319R Series Address Register +0 000088H to 00008CH 000090H 000094H 000098H +1 +2 PWCCL[R/W] 0000--00 PWCCH[R/W] 00-00000 PWC PWC 00009CH PWCUD[R] XXXXXXXX XXXXXXXX 0000A0H to 0000ACH IFN0 [R] 00000000 IFRN0 [R/W] 00000000 0000B4H IBCR0 [R/W] 00000000 IBSR0 [R/W] 00000000 0000B8H ITMK0 [R/W] 00----11 11111111 Reserved Reserved 0000B0H IFCR0 [R/W] 00-00000 Reserved IFDR0 [R/W] 00000000 ITBA0 [R/W] ------00 00000000 ISMK0 [R/W] 01111111 ISBA0 [R/W] 00000000 0000BCH IDAR0 [R/W] 00000000 ICCR0 [R/W] 0-011111 IDBL0 [R/W] -------0 0000C0H IFN1 [R] 00000000 IFRN1 [R/W] 00000000 IFCR1 [R/W] 00-00000 IFDR1 [R/W] 00000000 0000C4H IBCR1 [R/W] 00000000 IBSR1 [R/W] 00000000 0000C8H ITMK1 [R/W] 00----11 11111111 ITBA1 [R/W] ------00 00000000 ISMK1 [R/W] 01111111 ISBA1 [R/W] 00000000 0000CCH IDAR1 [R/W] 00000000 ICCR1 [R/W] 0-011111 IDBL1 [R/W] -------0 0000D0H IFN2 [R] 00000000 IFRN2 [R/W] 00000000 IFCR2 [R/W] 00-00000 IFDR2 [R/W] 00000000 0000D4H IBCR2 [R/W] 00000000 IBSR2 [R/W] 00000000 0000D8H 0000DCH ITMK2 [R/W] 00----11 11111111 IDAR2 [R/W] 00000000 Block PWCD[R] XXXXXXXX XXXXXXXX PWCC2[R/W] 000----- +3 ITBA2 [R/W] ------00 00000000 ISMK2 [R/W] 01111111 ISBA2 [R/W] 00000000 ICCR2 [R/W] 0-011111 IDBL2 [R/W] -------0 I2C Interface 0 I2C Interface 1 I2C Interface 2 (Continued) 27 MB91319R Series Address Register +0 +1 +2 +3 0000E0H IFN3 [R] 00000000 IFRN3 [R/W] 00000000 IFCR3 [R/W] 00-00000 IFDR3 [R/W] 00000000 0000E4H IBCR3 [R/W] 00000000 IBSR3 [R/W] 00000000 0000E8H ITMK3 [R/W] 00----11 11111111 ITBA3 [R/W] ------00 00000000 ISMK3 [R/W] 01111111 ISBA3 [R/W] 00000000 0000ECH IDAR3 [R/W] 00000000 ICCR3 [R/W] 0-011111 IDBL3 [R/W] -------0 0000F0H T0LPCR [R/W] -----000 T0CCR [R/W] 0-010000 T0TCR [R/W] 00000000 T0R [R/W] ---00000 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H T0DRR [R/W] XXXXXXXX XXXXXXXX T1LPCR [R/W] -----000 T1CCR [R/W] 0-000000 T1DRR [R/W] XXXXXXXX XXXXXXXX T2LPCR [R/W] -----000 T2CCR [R/W] 0-000000 T2DRR [R/W] XXXXXXXX XXXXXXXX T3LPCR [R/W] -----000 T3CCR [R/W] 0-000000 Block I2C Interface 3 T0CRR [R/W] XXXXXXXX XXXXXXXX T1TCR[R/W] 00000000 T1R [R/W] ---00000 T1CRR [R/W] XXXXXXXX XXXXXXXX T2TCR [R/W] 00000000 T2R [R/W] ---00000 Multi function Timer T2CRR [R/W] XXXXXXXX XXXXXXXX T3TCR [R/W] 00000000 T3R [R/W] ---00000 00010CH T3DRR [R/W] XXXXXXXX XXXXXXXX T3CRR [R/W] XXXXXXXX XXXXXXXX 000110H TMODE [R/W] -------- -----0-- 000114H to 00011FH 000120H PTMR0 [R] 11111111 11111111 PCSR0 [W] XXXXXXXX XXXXXXXX 000124H PDUT0 [W] XXXXXXXX XXXXXXXX 000128H PTMR1 [R] 11111111 11111111 00012CH PDUT1 [W] XXXXXXXX XXXXXXXX 000130H PTMR2 [R] 11111111 11111111 000134H PDUT2 [W] XXXXXXXX XXXXXXXX PCNH0 [R/W] 00000000 Reserved PCNL0 [R/W] 00000000 PCSR1 [W] XXXXXXXX XXXXXXXX PCNH1 [R/W] 00000000 PCNL1 [R/W] 00000000 PCSR2 [W] XXXXXXXX XXXXXXXX PCNH2 [R/W] 00000000 PCNL2 [R/W] 00000000 PPG0 PPG1 PPG2 (Continued) 28 MB91319R Series Address Register +0 +1 000138H PTMR3 [R] 11111111 11111111 00013CH PDUT3 [W] XXXXXXXX XXXXXXXX +2 +3 PCSR3[W] XXXXXXXX XXXXXXXX PCNH3 [R/W] 00000000 PCNL3 [R/W] 00000000 Block PPG3 000140H to 00014CH Reserved 000150H to 00015CH Reserved 000160H DSLC00 0------- DSLC10 -011---- CCDC0 00-00011 VSEP0 00--0001 000164H CSYSEP0 -101-011 HMASK0 --100000 HCLR0 ---00110 FLD0 00100000 000168H HCNT0 00000000 C21H0 0-111111 CRIP0 11111111 CRIC0 000-0000 00016CH CSTB0 11111111 CDTH0 11111111 CDAT00 00000000 CDAT10 00000000 000170H ID1C0 0-----00 ID20H0 0-111111 IDREF0 0-111111 IDTH0 11111111 000174H IDSTB0 11111111 IDDAT00 --000000 IDDAT10 00000000 IDDAT20 --000000 000178H DSAC10 ---000-0 DSAC20 10110011 DSAC30 00-00-00 00017CH 000180H DSLC01 0------- DSLC11 -011---- CCDC1 00-00011 VSEP1 00--0001 000184H CSYTSEP1 -101-011 HMASK1 --100000 HCLR1 ---00110 FLD1 00100000 000188H HCNT1 00000000 C21H1 0-111111 CRIP1 11111111 CRIC1 000-0000 00018CH CSTB1 11111111 CDTH1 11111111 CDAT01 00000000 CDAT1 00000000 000190H ID1C1 0-----00 ID20H1 0-111111 IDREF1 0-111111 IDTH1 11111111 000194H IDSTB1 11111111 IDDAT01 --000000 IDDAT11 00000000 IDDAT21 --000000 000198H DSAC11 ---000-0 DSAC21 10110011 DSAC31 00-00-00 00019CH CC decoder 0 channel CC decoder 1 channel (Continued) 29 MB91319R Series Address Register +0 +1 +2 +3 Block 0001A0H to 0001FCH 000200H DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000204H DMACB0 [R/W] 00000000 00000000 00000000 00000000 000208H DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00020CH DMACB1 [R/W] 00000000 00000000 00000000 00000000 000210H DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214H DMACB2 [R/W] 00000000 00000000 00000000 00000000 000218H DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021CH DMACB3 [R/W] 00000000 00000000 00000000 00000000 000220H DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 [R/W] 00000000 00000000 00000000 00000000 000228H 00022CH to 00023CH Reserved 000240H DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX DMAC 000244H to 0002FCH 000300H to 0003ECH 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved DMAC DMAC Reserved Bit Search Module (Continued) 30 MB91319R Series Address Register +0 +1 +2 +3 000400H DDR0 [R/W] 00000000 DDR1 [R/W] 00000000 DDR2 [R/W] 00000000 DDR3 [R/W] 00000000 000404H DDR4 [R/W] 00000000 DDR5 [R/W] 00000000 DDR7 [R/W] --000000 000408H DDR8 [R/W] 00000000 DDR9 [R/W] 00000000 DDRA [R/W] -----000 DDRB [R/W] 00000000 00040CH DDRC [R/W] 00000000 000410H PFR0 [R/W] 0--00000 PFR1 [R/W] 00000000 PFR2 [R/W] 00000000 PFR3 [R/W] 00000000 000414H PFR4 [R/W] 0000--00 PFR5 [R/W] 11111111 PFR6 [R/W] 11111111 PFR7 [R/W] 11111111 000418H PFR8 [R/W] 11111111 PFR9 [R/W] 11111111 PFRA [R/W] 11111111 PFRB [R/W] 11111111 00041CH PFRC [R/W] 1111---1 PFRD [R/W] ---11111 000420H to 00043CH Block R-bus Port Direction Register R-bus Port Function Register Reserved 000440H ICR00 [R/W] ---11111 ICR01 [R/W] ---11111 ICR02[R/W] ---11111 ICR03 [R/W] ---11111 000444H ICR04 [R/W] ---11111 ICR05 [R/W] ---11111 ICR06 [R/W] ---11111 ICR07 [R/W] ---11111 000448H ICR08 [R/W] ---11111 ICR09 [R/W] ---11111 ICR10 [R/W] ---11111 ICR11 [R/W] ---11111 00044CH ICR12 [R/W] ---11111 ICR13 [R/W] ---11111 ICR14 [R/W] ---11111 ICR15 [R/W] ---11111 000450H ICR16 [R/W] ---11111 ICR17 [R/W] ---11111 ICR18 [R/W] ---11111 ICR19 [R/W] ---11111 000454H ICR20 [R/W] ---11111 ICR21 [R/W] ---11111 ICR22 [R/W] ---11111 ICR23 [R/W] ---11111 000458H ICR24 [R/W] ---11111 ICR25 [R/W] ---11111 ICR26 [R/W] ---11111 ICR27 [R/W] ---11111 00045CH ICR28 [R/W] ---11111 ICR29 [R/W] ---11111 ICR30 [R/W] ---11111 ICR31 [R/W] ---11111 000460H ICR32 [R/W] ---11111 ICR33 [R/W] ---11111 ICR34 [R/W] ---11111 ICR35 [R/W] ---11111 000464H ICR36 [R/W] ---11111 ICR37 [R/W] ---11111 ICR38 [R/W] ---11111 ICR39 [R/W] ---11111 000468H ICR40 [R/W] ---11111 ICR41 [R/W] ---11111 ICR42 [R/W] ---11111 ICR43 [R/W] ---11111 00046CH ICR44 [R/W] ---11111 ICR45 [R/W] ---11111 ICR46 [R/W] ---11111 ICR47 [R/W] ---11111 Interrupt Control Unit (Continued) 31 MB91319R Series Address Register +0 +1 000470H to 00047CH +2 +3 Block Reserved 000480H RSRR [R/W] 10000000*2 STCR [R/W] 00110011*2 TBCR [R/W] 00XXXX00*1 CTBR [W] XXXXXXXX 000484H CLKR [R/W] 00000000*1 WPR [W] XXXXXXXX DIVR0 [R/W] 00000011*1 DIVR1[R/W] 00000000*1 000488H OSCCR [R/W] XXXXXXX0 Reserved 00048CH WPCR [R/W] B 00---000 Watch Timer 000490H OSCR [R/W] B 00---000 Main Oscillation Stabilization Wait Timer Clock Control Unit 000494H to 0005FCH Reserved 000600H to 0007FCH Reserved 000800H to 000AFCH Reserved 000B00H ESTS0 [R/W] X0000000 ESTS1 [R/W] XXXXXXXX ESTS2 [R] 1XXXXXXX 000B04H ECTL0 [R/W] 0X000000 ECTL1 [R/W] 00000000 ECTL2 [W] 000X0000 ECTL3 [R/W] 00X00X11 000B08H ECNT0 [W] XXXXXXXX ECNT1 [W] XXXXXXXX EUSA [W] XXX00000 EDTC [W] 0000XXXX 000B0CH EWP1 [R] 00000000 00000000 000B10H EDTR0 [W] XXXXXXXX XXXXXXXX EDTR1 [W] XXXXXXXX XXXXXXXX 000B14H to 000B1CH 000B20H EIA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B24H EIA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DSU (Continued) 32 MB91319R Series Address Register +0 +1 +2 000B28H EIA2 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B2CH EIA3 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B30H EIA4 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B34H EIA5 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B38H EIA6 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B3CH EIA7 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B40H EDTA [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B44H EDTM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B48H EOA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B4CH EOA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B50H EPCR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B54H EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B58H EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B5CH EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B60H EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B64H EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B68H EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B6CH EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B70H to 000FFCH +3 Block DSU Reserved (Continued) 33 MB91319R Series (Continued) Address Register +0 +1 +2 001000H DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001004H DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001008H DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00100CH DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001010H DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001014H DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001018H DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00101CH DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001020H DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001024H DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001028H to 006FFCH Block DMAC Reserved 007000H FLCR [R/W] 0110X000 007004H FLWC [R/W] 00010011 007008H to 0070FFH +3 Program Flash I/F Reserved 007100H FNCR [R/W] 0110X000 007104H FNWT [R/W] 00010011 Font Flash I/F *1 : The initial value of the register varies with the reset level. The initial value shown is the one after an INIT level reset. *2 : The initial value of the register varies with the reset level. The initial value shown is the one after an INIT level reset by the INIT pin. 34 MB91319R Series Address Register +0 +1 +2 +3 Block 050000H to 050024H Reserved Reserved 050028H to 05FFFFH Reserved Reserved 060000H FIFO0o [R] XXXXXXXX XXXXXXXX FIFO0i [W] XXXXXXXX XXXXXXXX 060004H FIFO1 [R] XXXXXXXX XXXXXXXX FIFO2 [W] XXXXXXXX XXXXXXXX 060008H FIFO3 [R] XXXXXXXX XXXXXXXX 06000CH to 06001FH Reserved 060020H Reserved CONT1 [R/W] 000XX0XX XXX00000 060024H CONT2 [R/W] XXXXXXXX XXX00000 CONT3 [R/W] XXXXXXXX XXX00000 060028H CONT4 [R/W] XXXXXXXX XXX00000 CONT5 [R/W] XXXXXXXX XXXX00XX 06002CH CONT6 [R/W] XXXXXXXX XXXX00XX CONT7 [R/W] XXXXXXXX XXX00000 060030H CONT8 [R/W] XXXXXXXX XXX00000 CONT9 [R/W] 0XX0XXXX 0XXX0000 060034H CONT10 [R/W] 00000000 X00000XX TTSIZE [R/W] 00010001 00010001 060038H TRSIZE [R/W] 00010001 00010001 Reserved 06003CH Reserved 060040H RSIZE0 [R] XXXXXXXX XXXX0000 Reserved 060044H RSIZE1 [R] XXXXXXXX X0000000 Reserved 060048H to 06005FH 060060H 060064H USB Function Reserved ST1 [R/W] XXXXXX00 00000000 Reserved Reserved (Continued) 35 MB91319R Series Address Register +0 +1 +2 +3 060068H ST2 [R] XXXXXXXX X0000000 ST3 [R/W] 00XXXXXX X0000000 06006CH ST4 [R/W] XXXXX000 00000000 ST5 [R/W] 0XX00XXX XX000000 060070H to 06007FH Reserved 060080H to 06FFFFH Reserved Block USB Function Reserved 078000H OSD_VADR [W] XXXXXXXX XXXXXXXX OSD_CD1 [W] XXXXXXXX XXXXXXXX 078004H OSD_CD2 [W] XXXXXXXX XXXXXXXX OSD_RCD1 [W] XXXXXXXX XXXXXXXX 078008H OSD_RCD2 [W] XXXXXXXX XXXXXXXX OSD_SOC1 [W] XXXXXXXX 0000XXXX 07800CH OSD_SOC2 [W] XXXXXXXX XXXXXXXX OSD_VDPC [W] XXXXXXXX XXXXXXXX 078010H OSD_HDPC [W] XXXXXXXX XXXXXXXX OSD_CVSC [W] XXXXXXXX XXXXXXXX 078014H OSD_SBFCC [W] XXXXXXXX XXXXXXXX OSD_THCC [W] XXXXXXXX XXXXXXXX 078018H OSD_GFCC [W] XXXXXXXX XXXXXXXX OSD_SBCC1 [W] XXXXXXXX XXXXXXXX 07801CH OSD_SBCC2 [W] XXXXXXXX XXXXXXXX OSD_SPCC1 [W] XXXXXXXX XXXXXXXX 078020H OSD_SPCC2 [W] XXXXXXXX XXXXXXXX OSD_SPCC3 [W] XXXXXXXX XXXXXXXX 078024H OSD_SPCC4 [W] XXXXXXXX XXXXXXXX OSD_SYNCC [W] XXXXXXXX XXXXXXXX 078028H 07802CH OSD_IOC1 [W] XXXXXXXX XXXXXX00 078030H OSD_IOC2 [W] XXXXXXXX XXXXXXXX OSD_DPC1 [W] XXXXXXXX XXXXXXXX 078034H OSD_DPC2 [W] XXXXXXXX XXXXXXXX OSD_DPC3 [W] XXXXXXXX XXXXXXXX 078038H OSD_DPC4 [W] XXXXXXXX XXXXXXXX OSD_IRC [W] XXXXXXXX XXXXXXXX 07803CH OSD_PLT0 [W] XXXXXXXX XXXXXXXX OSD_PLT1 [W] XXXXXXXX XXXXXXXX OSDC (MAIN) (Continued) 36 MB91319R Series Address Register +0 +1 +2 +3 078040H OSD_PLT2 [W] XXXXXXXX XXXXXXXX OSD_PLT3 [W] XXXXXXXX XXXXXXXX 078044H OSD_PLT4 [W] XXXXXXXX XXXXXXXX OSD_PLT5 [W] XXXXXXXX XXXXXXXX 078048H OSD_PLT6 [W] XXXXXXXX XXXXXXXX OSD_PLT7 [W] XXXXXXXX XXXXXXXX 07804CH OSD_PLT8 [W] XXXXXXXX XXXXXXXX OSD_PLT9 [W] XXXXXXXX XXXXXXXX 078050H OSD_PLT10 [W] XXXXXXXX XXXXXXXX OSD_PLT11 [W] XXXXXXXX XXXXXXXX 078054H OSD_PLT12 [W] XXXXXXXX XXXXXXXX OSD_PLT13 [W] XXXXXXXX XXXXXXXX 078058H OSD_PLT14 [W] XXXXXXXX XXXXXXXX OSD_PLT15 [W] XXXXXXXX XXXXXXXX 07805CH OSD_ACT1 [W] XXXXXXXX XXXXXXXX OSD_ACT2 [W] XXXXXXXX XXXXXXXX 078060H OSD_PLACC11 [W] XXXXXXXX XXXXXXXX OSD_PLACC12 [W] XXXXXXXX XXXXXXXX 078064H OSD_PLACC2 [W] XXXXXXXX XXXXXXXX OSD_PLACC3 [W] XXXXXXXX XXXXXXXX 078068H OSD_PLBCC11 [W] XXXXXXXX XXXXXXXX OSD_PLBCC12 [W] XXXXXXXX XXXXXXXX 07806CH OSD_PLBCC2 [W] XXXXXXXX XXXXXXXX OSD_PLBCC3 [W] XXXXXXXX XXXXXXXX 078070H OSD_PLCC11[W] XXXXXXXX XXXXXXXX OSD_PLCC12[W] XXXXXXXX XXXXXXXX 078074H OSD_PLCC2[W] XXXXXXXX XXXXXXXX OSD_PLCC3[W] XXXXXXXX XXXXXXXX 078078H OSD_CSC1 [W] XXXXXXXX XXXXXXXX OSD_CSC2 [W] XXXXXXXX XXXXXXXX 07807CH to 0780FFH 078100H CCOSD_VADR [W] XXXXXXXX XXXXXXXX CCOSD_CD1 [W] XXXXXXXX XXXXXXXX 078104H CCOSD_CD2 [W] XXXXXXXX XXXXXXXX CCOSD_RCD1 [W] XXXXXXXX XXXXXXXX 078108H CCOSD_RCD2 [W] XXXXXXXX XXXXXXXX CCOSD_SOC1 [W] XXXXXXXX 0000XXXX 07810CH CCOSD_SOC2 [W] XXXXXXXX XXXXXXXX CCOSD_VDPC [W] XXXXXXXX XXXXXXXX Block OSDC (MAIN) Reserved OSDC (CC) (Continued) 37 MB91319R Series (Continued) Address +0 +1 +2 +3 078110H CCOSD_HDPC [W] XXXXXXXX XXXXXXXX CCOSD_CVSC [W] XXXXXXXX XXXXXXXX 078114H CCOSD_THCC [W] XXXXXXXX XXXXXXXX 078118H 07811CH 078120H 078124H 078128H 07812CH 078130H CCOSD_DPC1 [W] XXXXXXXX XXXXXXXX 078134H CCOSD_DPC2 [W] XXXXXXXX XXXXXXXX CCOSD_DPC3 [W] XXXXXXXX XXXXXXXX 078138H CCOSD_DPC4 [W] XXXXXXXX XXXXXXXX CCOSD_IRC [W] XXXXXXXX XXXXXXXX 07813CH CCOSD_PLT0 [W] XXXXXXXX XXXXXXXX CCOSD_PLT1 [W] XXXXXXXX XXXXXXXX 078140H CCOSD_PLT2 [W] XXXXXXXX XXXXXXXX CCOSD_PLT3 [W] XXXXXXXX XXXXXXXX 078144H CCOSD_PLT4 [W] XXXXXXXX XXXXXXXX CCOSD_PLT5 [W] XXXXXXXX XXXXXXXX 078148H CCOSD_PLT6 [W] XXXXXXXX XXXXXXXX CCOSD_PLT7 [W] XXXXXXXX XXXXXXXX 07814CH CCOSD_PLT8 [W] XXXXXXXX XXXXXXXX CCOSD_PLT9 [W] XXXXXXXX XXXXXXXX 078150H CCOSD_PLT10 [W] XXXXXXXX XXXXXXXX CCOSD_PLT11 [W] XXXXXXXX XXXXXXXX 078154H CCOSD_PLT12 [W] XXXXXXXX XXXXXXXX CCOSD_PLT13 [W] XXXXXXXX XXXXXXXX 078158H CCOSD_PLT14 [W] XXXXXXXX XXXXXXXX CCOSD_PLT15 [W] XXXXXXXX XXXXXXXX 07815CH 078160H to 07FFFFH 38 Register Reserved Block OSDC (CC) Reserved MB91319R Series INTERRUPT FACTORS, INTERRUPT VECTORS, AND INTERRUPT REGISTER Interrupt number Interrupt level Offset Address of TBR default RN 00 3FCH 000FFFFCH 1 01 3F8H 000FFFF8H System reserved 2 02 3F4H 000FFFF4H System reserved 3 03 3F0H 000FFFF0H System reserved 4 04 3ECH 000FFFECH System reserved 5 05 3E8H 000FFFE8H System reserved 6 06 3E4H 000FFFE4H Coprocessor absent trap 7 07 3E0H 000FFFE0H Coprocessor error trap 8 08 3DCH 000FFFDCH INTE instruction 9 09 3D8H 000FFFD8H System reserved 10 0A 3D4H 000FFFD4H System reserved 11 0B 3D0H 000FFFD0H Step trace trap 12 0C 3CCH 000FFFCCH NMI request (tool) 13 0D 3C8H 000FFFC8H Undefined instruction exception 14 0E 3C4H 000FFFC4H NMI request 15 0F 15 (FH) fixed 3C0H 000FFFC0H External interrupt 0 16 10 ICR00 3BCH 000FFFBCH External interrupt 1 17 11 ICR01 3B8H 000FFFB8H External interrupt 2 18 12 ICR02 3B4H 000FFFB4H External interrupt 3 19 13 ICR03 3B0H 000FFFB0H External interrupt 4 (USB function) 20 14 ICR04 3ACH 000FFFACH External interrupt 5 (OSDC-MAIN) 21 15 ICR05 3A8H 000FFFA8H External interrupt 6 (OSDC-CC) 22 16 ICR06 3A4H 000FFFA4H System reserved 23 17 ICR07 3A0H 000FFFA0H Reload timer 0 24 18 ICR08 39CH 000FFF9CH 8 Reload timer 1 25 19 ICR09 398H 000FFF98H 9 Reload timer 2 26 1A ICR10 394H 000FFF94H 10 UART0 (Reception completed) 27 1B ICR11 390H 000FFF90H 0 UART1 (Reception completed) 28 1C ICR12 38CH 000FFF8CH 1 UART2 (Reception completed) 29 1D ICR13 388H 000FFF88H 2 UART0 (Transmission completed) 30 1E ICR14 384H 000FFF84H 3 UART1 (Transmission completed) 31 1F ICR15 380H 000FFF80H 4 Interrupt factor Decimal Hexadecimal Reset 0 Mode vector (Continued) 39 MB91319R Series Interrupt number Interrupt factor Interrupt level Offset Address of TBR default RN Decimal Hexadecimal UART2 (Transmission completed) 32 20 ICR16 37CH 000FFF7CH 5 DMAC0 (end, error) 33 21 ICR17 378H 000FFF78H DMAC1 (end, error) 34 22 ICR18 374H 000FFF74H DMAC2 (end, error) 35 23 ICR19 370H 000FFF70H DMAC3 (end, error) 36 24 ICR20 36CH 000FFF6CH DMAC4 (end, error) 37 25 ICR21 368H 000FFF68H A/D converter 38 26 ICR22 364H 000FFF64H PPG0 39 27 ICR23 360H 000FFF60H PPG1 40 28 ICR24 35CH 000FFF5CH PPG2 41 29 ICR25 358H 000FFF58H PPG3 42 2A ICR26 354H 000FFF54H PWC 43 2B ICR27 350H 000FFF50H CCD0 44 2C ICR28 34CH 000FFF4CH CCD1 45 2D ICR29 348H 000FFF48H Main oscillation wait 46 2E ICR30 344H 000FFF44H Time-base timer overflow 47 2F ICR31 340H 000FFF40H System reserved 48 30 ICR32 33CH 000FFF3CH Watch timer 49 31 ICR33 338H 000FFF38H I2C ch.0 50 32 ICR34 334H 000FFF34H 2 51 33 ICR35 330H 000FFF30H 2 I C ch.2 52 34 ICR36 32CH 000FFF2CH I2C ch.3 53 35 ICR37 328H 000FFF28H UART3 (Reception completed) 54 36 ICR38 324H 000FFF24H UART4 (Reception completed) 55 37 ICR39 320H 000FFF20H UART3 (Transmission completed) 56 38 ICR40 31CH 000FFF1CH UART4 (Transmission completed) 57 39 ICR41 318H 000FFF18H Multi-functional timer 0 58 3A ICR42 314H 000FFF14H Multi-functional timer 1 59 3B ICR43 310H 000FFF10H Multi-functional timer 2 60 3C ICR44 30CH 000FFF0CH Multi-functional timer 3 61 3D ICR45 308H 000FFF08H System reserved 62 3E ICR46 304H 000FFF04H Delay interrupt factor bit 63 3F ICR47 300H 000FFF00H System reserved (Used by REALOS) 64 40 2FCH 000FFEFCH System reserved (Used by REALOS) 65 41 2F8H 000FFEF8H I C ch.1 (Continued) 40 MB91319R Series (Continued) Interrupt number Interrupt factor Interrupt level Offset Address of TBR default RN Decimal Hexadecimal System reserved 66 42 2F4H 000FFEF4H System reserved 67 43 2F0H 000FFEF0H System reserved 68 44 2ECH 000FFEECH System reserved 69 45 2E8H 000FFEE8H System reserved 70 46 2E4H 000FFEE4H System reserved 71 47 2E0H 000FFEE0H System reserved 72 48 2DCH 000FFEDCH System reserved 73 49 2D8H 000FFED8H System reserved 74 4A 2D4H 000FFED4H System reserved 75 4B 2D0H 000FFED0H System reserved 76 4C 2CCH 000FFECCH System reserved 77 4D 2C8H 000FFEC8H System reserved 78 4E 2C4H 000FFEC4H System reserved 79 4F 2C0H 000FFEC0H Used by INT instruction 80 to 255 50 to FF 2BCH to 000H 000FFEBCH to 000FFC00H 41 MB91319R Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Min Max VDDE (3.3 V) VSS - 0.5 VSS + 4.0 V VDDI (1.8 V) VSS - 0.3 VSS + 2.5 V AVCC VSS - 0.5 VSS + 4.0 V Input voltage * VI VSS - 0.5 VDDE + 0.5 V Analog pin input voltage * VIA VSS - 0.5 AVcc + 0.5 V Output voltage * VO VSS - 0.5 VCC + 0.5 V Tstg - 40 + 125 C Power supply voltage * Analog power supply voltage * Storage temperature * : The parameter is based on VSS =AVSS =0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 2. Recommended Operating Conditions (VSS = AVSS =0 V) Parameter Operating temperature Power supply voltage Analog power supply voltage Symbol Value Min Max Ta - 10 + 70 VDDE (3.3 V) 3.00 3.6 VDDI (1.8 V) 1.65 1.95 AVCC 3.00 VDDE Unit C V V WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 42 MB91319R Series 3. DC Characteristics (1) CPU * MB91FV319R, MB91F318R/F318S (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Current dissipation (upper : 1.8V lower : 3.3V) Symbol Conditions "H" level output voltage Typ Max 400 900 700 1000 140 180 140 190 Watch mode Ta = + 25 C, fclk = 32 kHz ICC Normal operation Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz Main sleep mode Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz 80 100 ICCS 80 110 ICCL Sub RUN mode Ta = + 25 C, fclk = 32 kHz 500 1200 900 1300 240 800 50 100 1900 8800 300 500 VCC x 0.8 VCC Main stop mode Ta = + 25 C, fclk = 0 kHz Ta = + 70 C, fclk = 0 kHz "L" level input voltage Min ICCT ICCH "H" level input voltage Value VIH VIL VOH VCC = 3.3 V VCC = 3.3 V, IOH = - 4 mA VSS VCC - 0.5 VCC x 0.2 VCC Unit Remarks A Dot clock PLL stop USB clock stop mA Dot clock at 90 MHz MB91F318R/F318S only mA Dot clock PLL stop A Dot clock PLL stop USB clock stop A A V V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, DCKI, VSYNC, HSYNC1 to HSYNC3 V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, B0 to B2, G0 to G2, R0 to R2, VOB1, VOB2, DCKO, FH (Continued) 43 MB91319R Series (Continued) Parameter "L" level output voltage Input leak current 44 Symbol Conditions Value Min Typ Max Unit Remarks P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, B0 to B2, G0 to G2, R0 to R2, VOB1, VOB2, DCKO, FH VOL VCC = 3.3 V, IOL = 4 mA VSS 0.4 V IIL -5 +5 A I2C bus switch connection resistor RBS 130 Between SCL2 and SCL3 Between SDA2 and SDA3 Between SCL3 and SCL4 Between SDA3 and SDA4 Analog RGB reference voltage VREF 1.05 1.10 1.15 V VREF Analog RGB reference resistor RREF 2.4 2.7 k Between VR0 and VSSR Analog RGB output impedance RL 150 160 ROUT, GOUT, BOUT MB91319R Series * MB91316/A Parameter Current dissipation (upper : 1.8V lower : 3.3V) (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Symbol Conditions "H" level output voltage Typ Max Watch mode Ta = + 25 C, fclk = 32 kHz 300 600 700 1000 Normal operation Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz 110 130 ICC 110 140 Main sleep mode Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz 70 90 ICCS 70 100 ICCL Sub RUN mode Ta = + 25 C, fclk = 32 kHz 400 800 900 1300 Main stop mode Ta = + 25 C, fclk = 0 kHz 150 500 50 100 1200 5500 300 500 VCC x 0.8 VCC Ta = + 70 C, fclk = 0 kHz "L" level input voltage Min ICCT ICCH "H" level input voltage Value VIH VIL VOH VCC = 3.3 V VCC = 3.3 V, IOH = - 4 mA VSS VCC - 0.5 VCC x 0.2 VCC Unit A Remarks Dot clock PLL stop USB clock stop mA Dot clock at 90 MHz mA Dot clock PLL stop A Dot clock PLL stop USB clock stop A A V V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, DCKI, VSYNC, HSYNC1 to HSYNC3 V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, B0 to B2, G0 to G2, R0 to R2, VOB1, VOB2, DCKO, FH (Continued) 45 MB91319R Series (Continued) Parameter "L" level output voltage Input leak current 46 Symbol Conditions Value Min Typ Max Unit Remarks P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, B0 to B2, G0 to G2, R0 to R2, VOB1, VOB2, DCKO, FH VOL VCC = 3.3 V, IOL = 4 mA VSS 0.4 V IIL -5 +5 A I2C bus switch connection resistor RBS 130 Between SCL2 and SCL3 Between SDA2 and SDA3 Between SCL3 and SCL4 Between SDA3 and SDA4 Analog RGB reference voltage VREF 1.05 1.10 1.15 V VREF Analog RGB reference resistor RREF 2.4 2.7 k Between VR0 and VSSR Analog RGB output impedance RL 150 160 ROUT, GOUT, BOUT MB91319R Series (2) USB * DC Characteristics (1) (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin "H" level output voltage VOH IOH = - 100 A "L" level output voltage VOL IOL = 100 A "H" level output current IOH Conditions Value Unit Remarks Min Typ Max VDDE - 0.2 VDDE V 0 0.2 V At Full Speed Mode VOH = VDDE - 0.4 V - 20 mA At Low Speed Mode VOH = VDDE - 0.4 V -6 mA At Full Speed Mode VOL = 0.4 V 20 mA At Low Speed Mode VOL = 0.4 V 6 mA "L" level output current IOL Output shortcircuit current IOS 300 mA *1 Input leak current ILZ 5 A *2 *1 : About the output short-circuit current IOS Output short-circuit current IOS is the maximum current that flows when the output pin is connected to VDDE or VSS (within the maximum rating) . Monitor the short-circuit current "H" level "H" output Short-circuited at GND level 3-State Enable "L" Short-circuited at VDDE level "L" level "L" output Monitor the short-circuit current 3-State Enable "L" About the output short-circuit current : The current is "the short-circuit current per differential output pin". As the USB I/O buffer is a differential output, the short-circuit current should be considered for both of the output pins. (Continued) 47 MB91319R Series (Continued) *2 : About measurement of "Z" leakage current ILZ Input leakage current ILZ is measured with the USB I/O buffer in the high-impedance state when the VDDE or VSS voltage is applied to the bidirectional pin. Monitor the leakage current "Z" output 0 V and VDD level applied to output pin 3-State Enable "H" 48 MB91319R Series * DC Characteristics (2) Conform to the USB Specification Revision 2.0 Full speed. (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Value Min Max Unit Remarks Input Voltage : High (driven) VIH 2.0 V *1 Low VIL 0.8 V *1 Differential Input Sensitivity VDI 0.2 V *2 Common Mode Input Voltage VCM 0.8 2.5 V *2 Low VOL 0.0 0.3 V *3 High (driven) VOH 2.8 3.6 V *3 Differential Output Signal Voltage VCRS 1.3 2.0 V *4 Pull-Up Resistor on Upstream Port RPU 1.425 1.575 k 1.5 k 5% Pull-Down Resistor on Downstream Port RPD 1.425 1.575 k 1.5 k 5% VTERM 3.0 3.6 V Output Voltage : Terminations : Termination voltage for upstream port pull-up *5 *1 : About input voltage VIH, VIL The switching threshold voltage of the USB I/O buffer's single-end receiver is set within the range from VIL (Max) = 0.8 V to VIH (Min) = 2.0 V (TTL input standard) . For VIH and VIL, the LSI has some hysteresis to reduce noise susceptibility. Minimum operating input sensitivity (V) *2 : About input voltage VDI, VCM A differential receiver is used to receive USB differential data signals. The differential receiver has a differential input sensitivity of 200 mV when the differential data input falls within the range from 0.8 V to 2.5 V with respect to the local ground reference level. The above voltage range is referred to as common-mode input voltage range. 1.0 0.2 0.8 2.5 Common mode input voltage (V) (Continued) 49 MB91319R Series (Continued) *3 : About output voltage VOL, VOH The output driving performance levels of the driver are 0.3 V or less (to 3.6 V, 1.5 k load) in the low state (VOL) and 2.8 V or more (to ground, 1.5 k load) in the high state (VOH) . *4 : About output voltage VCRS The cross voltage of the external differential output signals (D+ and D-) for the USB I/O buffer falls within the range from 1.3 V to 2.0 V. D+ Max 2.0 (V) VCRS standard range Max 1.3 (V) D- *5 : About terminations VTERM VTERM indicates the pull-up voltage at the upstream port. 50 MB91319R Series 4. AC Characteristics (1) Clock Timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin Conditions Clock frequency fC X0, X1 fCP Internal operating clock frequency fCPP fCPT Value Min Max Unit Remarks 9.0 10.2 PLL system (operation at a maximum MHz internal speed of 40 MHz by quadrupling a self-oscillation frequency of 10 MHz via PLL) 2.25* 40.8 MHz CPU system (tCP = 1/fCP) 2.25* 20.4 MHz Peripheral system (tCPP = 1/fCPP) 2.25* 20.4 MHz External bus system (tCPT = 1/fCPT) * : The numeric value when inputting the 9 MHz (the minimum clock frequency) to X0 and using the PLL system and the gear ratio 1/16 of the oscillation circuit. (2) Reset Input (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin Value Conditions INIT input time (at power-on) INIT input time (other than at power-on) tINTL INIT INIT input time (at returning from stop) Unit Min Max 20 + s tCP x 10 ns 20 + s Note: tCP is the internal clock time. Refer to "(1) Clock Timing". tINTL INIT 0.2 VCC 51 MB91319R Series (3) UART Timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin Conditions Serial clock cycle time tSCYC SCK0 to SCK4 SCK SO delay time tSLOV SCK0 to SCK4, SO0 to SO4 Valid SIN SCK tIVSH SCK0 to SCK4, SI0 to SI4 SCK valid SI hold time tSHIX Serial clock "H" pulse width Value Max 8 tCPP ns - 80 + 80 ns 100 ns SCK0 to SCK4, SI0 to SI4 60 ns tSHSL SCK0 to SCK4 4 tCPP ns Serial clock "L" pulse width tSLSH SCK0 to SCK4 4 tCPP ns SCK SO delay time tSLOV SCK0 to SCK4, SO0 to SO4 150 ns Valid SI SCK tIVSH SCK0 to SCK4, SI0 to SI4 60 ns Valid SCK valid SI hold time tSHIX SCK0 to SCK4, SI0 to SI4 60 ns Internal shift lock mode External shift lock mode Notes : * tCPP indicates the peripheral clock cycle time. Refer to "(1) Clock Timing". * The above specifications are for the CLK synchronous mode. * Internal shift clock mode tSCYC SCK0 to SCK4 VOH VOL VOL tSLOV VOH VOL SO0 to SO4 tIVSH tSHIX VOH VOL VOH VOL SI0 to SI4 * External shift clock mode tSLSH tSHSL VOH SCK0 to SCK4 VOH VOH VOH tSLOV SO0 to SO4 VOH VOL tIVSH SI0 to SI4 52 Unit Min VOH VOL tSHIX VOH VOL MB91319R Series (4) Reload timer clock , PPG timer input, multi-functional timer input timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin Conditions tTIWH tTIWL TIN0 to TIN2, PPG0 to PPG3, TRG0 to TRG3, TMI0 to TMI3 Input pulse width Value Min Max 2 tCPP Unit ns Note : tCPP indicates the peripheral clock cycle time. Refer to "(1) Clock Timing". tTIWL tTIWH (5) Trigger Input Timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter A/D activation trigger input time Symbol Pin Conditions tATGX ATRG Value Min Max 5 tCPP Unit ns Note : tCPP indicates the peripheral clock cycle time. Refer to "(1) Clock Timing". tATGX ATRG 53 MB91319R Series (6) USB interface (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Input clock frequency Pin Conditions X0B, X1B tUCYC X0B Value Min Typ Max Unit 48*1 MHz Remarks Self-oscillation 500 ppm accuracy *1 tUCYC = 1 / fUCYC External input 500 ppm accuracy *1 tUCYC = 1 / fUCYC Rise Time tUTFR UDP/ UDM At Full Speed Mode 4 20 ns *2 Fall Time tUTFF UDP/ UDM At Full Speed Mode 4 20 ns *2 Differential Rise and Fall Timing Matching UDP/ UDM At Full Speed Mode 90 111.11 % *2 Driver Output Resistor UDP, UDM 28 44 *3 tUCYC X0B (X1B) UDP UDM 90% 90% 10% 10% tUTFR tUTFF *1 : The AC characteristics of the USB interface conform to USB Specification Revision 2.0 Full speed. *2 : About driver characteristics tUTFR, tUTFF, tUTFRFM These items specify the differential data signal rise (Rise Time) and fall (Fall time) times. These are defined as the times between 10% to 90% of the output signal voltage. For the full-speed buffer, tUTFR and tUTFF are specified such that the tUTFR/tUTFF ratio falls within 10% to minimize RFI radiation. (Continued) 54 MB91319R Series (Continued) *3 : About driver characteristics ZDRV USB full-speed connection is performed via a shielded twisted-pair cable at a characteristic impedance of 90 15%. The USB Standard stipulates that the USB driver's output impedance must be within the range of 28 to 44 . The USB Standard also stipulates that a discrete serial resistor (Rs) must be added to have balance while satisfying the above standard. The output impedance of the USB I/O buffer on this LSI is about 3 to 19 . Therefore, serial resistor RS to be added must be 25 to 30 (27 recommended) . Rs 28 to 44 Equiv. Imped TxD+ Rs TxD- 28 to 44 Equiv. Imped 3-State Driver output impedance 3 to 19 Rs serial resistor: 25 to 30 Add a serial resistor of preferably 27 55 MB91319R Series (7) Analog RGB (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin Conditions Analog RGB output delay tVAD ROUT, GOUT, BOUT Analog RGB output settling time tVAS ROUT, GOUT, BOUT VREF = 1.1 V, VDDR = VDDG = VDDB = 2.5 V, VRO* = 2.7 k Value 56 20 ns 1 LSB tVAS 50 MHz (Max) 12 1 LSB BOUT ns DCKI GOUT Max * Display signal output timing ROUT Remarks Typ * : VRO is an external resistor for DAC. tVAD Unit Min MB91319R Series (8) Digital RGB Vertical synchronous, horizontal synchronous, and display output control signal input timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Horizontal sync signal cycle time tHCYC Horizontal sync signal pulse width tWH Horizontal sync signal setup time tDHST Horizontal sync signal hold time tDHHD Vertical sync signal setup time tHVST Vertical sync signal hold time tHVHD Input sync signal rise/fall time tDR tDF Value Pin Min HSYNC1 to HSYNC3 100 + tWH HSYNC1 to HSYNC3 Unit Dot clock 20 Dot clock 6 s 4 ns 0 ns 5 2 1H* - 5 Dot clock 3 H*2 2 ns HSYNC1 to HSYNC3 VSYNC HSYNC1 to HSYNC3, VSYNC Max Remarks *1 *1 : During the horizontal sync signal pulse period, the device stops its internal OSDC operation, disabling writing to the internal VRAM. Therefore, set the horizontal sync signal pulse width and VRAM write cycle to ensure that : horizontal sync signal pulse width < VRAM write cycle. Precisely, adjust the command issuance interval not to issue command 2 or command 4 (VRAM write command) more than twice in the horizontal sync signal pulse width period. If the above condition is not satisfied, the device may fail writing to VRAM. *2 : 1H is assumed to be one horizontal sync signal period. * Horizontal sync signal, display output control signal input timing 0.8 VDD DCKI 0.2 VDD tDHST tDHHD 0.8 VDD 0.8 VDD 0.2 VDD 0.2 VDD HSYNC1 to HSYNC3 tDR, tDF 57 MB91319R Series * Horizontal sync signal input tHCYC tWH tDF 0.8 VDD HSYNC1 to HSYNC3 tDR 0.8 VDD 0.8 VDD 0.2 VDD 0.2 VDD * Vertical sync signal input timing * VSYNC detection at the leading edge of HSYNC tDF HSYNC1 to HSYNC3 tWH tDR 0.8 VDD 0.8 VDD 0.2 VDD 0.2 VDD tHVST tDF tHVHD 0.8 VDD tDR 0.8 VDD VSYNC 0.2 VDD 0.2 VDD * VSYNC detection at the trailing edge of HSYNC tWH tDF HSYNC1 to HSYNC3 tDR 0.8 VDD 0.8 VDD 0.2 VDD 0.2 VDD tDF tHVST 0.8 VDD VSYNC 58 tHVHD tDR 0.8 VDD 0.2 VDD 0.2 VDD MB91319R Series (9) Display signal timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin tDIF DCKI Dot clock cycle time Dot clock pulse time Dot clock output delay time 1 Display signal output delay time I1 Display signal output delay time O1 tDIWH DCKI tDIWL Value Unit Remarks 90 MHz *1 5 ns 5 ns Min Max 11 *1 tPDCS DCKO 3 8 ns *2 tPDI1 R0 to R2, B0 to B2, G0 to G2, VOB1, VOB2 2 8 ns *2 tPDO1 R0 to R2, B0 to B2, G0 to G2, VOB1, VOB2 -4 +5 ns *2 *1 : Input a continuous dot clock signal without a break. *2 : Output load 16 pF Note : The actual display output varies depending on how the display output/position is controlled for each display layer. * Display signal output timing tDIF tDIWH DCKI 0.8 VDD tDIWL 0.8 VDD 0.2 VDD tPDCS 0.2 VDD tPDCS 0.8 VDD DCKO tPDO1 0.2 VDD tPDI1 R0 to R2 B0 to B2 G0 to G2 VOB1, VOB2 0.8 VDD 0.2 VDD 59 MB91319R Series (10-a) External circuit for data slicer (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin VVIN VIN0, VIN1 Video signal input level Value Min Typ Max 1.0 1.5 Unit Vp-p (10-b) External circuit for data slicer (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter 60 Symbol Pin Coupling capacitor for VIN pin CVIN Clamping resistor Value Unit Remarks 0.1 F Ceramic capacitor with B rating or higher, 10% tolerance 1 M 5% tolerance 0 5% tolerance 82 pF Ceramic capacitor with B rating or higher, 10% tolerance CBP VDDIS, VSSS 0.1 F Ceramic capacitor Resistor for video signal input buffer R1 2.2 k 5% tolerance Video signal input level correcting resistor R2 4.7 k 5% tolerance Video signal input level correcting resistor R3 10 12 k 5% tolerance Min Typ Max VIN0, VIN1 RCL VIN0, VIN1 Input resistor for VIN pin RIN VIN0, VIN1 Low-pass filter capacitor for VIN C1 Power supply bypass capacitor MB91319R Series External recommended circuit for data slicer (1) When the input composite video signals have been DC clamped 2.5 V VDDIS CBP 5V VSSS R1 RIN CVIN VIN0, VIN1 R2 2SB709A equivalent RCL R3 Composite video signal (2 Vp-p) C1 (2) When the input composite video signals have not been DC clamped 2.5 V VDDIS Add this resistor CBP 5V VSSS R1 RIN 10 k (5% tolerance) CVIN VIN0, VIN1 RCL 2SB709A equivalent R2 R3 C1 Composite video signal (2 Vp-p) 61 MB91319R Series (11) I2C timing * At master mode operating (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Conditions Typical mode High-speed mode*3 Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz "L" period of SCL clock tLOW 4.7 1.3 s "H" period of SCL clock tHIGH 4.0 0.6 s Bus free time between [STOP condition] and [START condition] tBUS 4.7 1.3 s SCL SDA output delay time tDLDAT 5 x M*1 5 x M*1 ns Setup time of [repeat START condition] SCL SDA tSUSTA 4.7 0.6 s Hold time of [repeat START condition] SDA SCL tHDSTA 4.0 0.6 s Setup time of [STOP condition] SCL SDA tSUSTO 4.0 0.6 s SDA data input hold time (vs. SCL) tHDDAT 2 x M*1 2 x M*1 s SDA data input setup time (vs. SCL) tSUDAT 250 100*2 ns R = 1 k C = 50 pF*4 Remarks After that, the first clock pulse is generated. *1 : M = Resource clock cycle (ns) *2 : A Fast-mode I2C bus device can be used for a standard mode I2C bus system as long as the device satisfies a requirement of "tSUDAT 250 ns". When the device does not extend the "L" period of the SCL signal, the next data must be outputted to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released. *3 : For use at over 100 kHz, set the resource clock to at least 6 MHz. *4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines. 62 MB91319R Series * At slave mode operating (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Conditions Typical mode High-speed mode*3 Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz "L" period of SCL clock tLOW 4.7 1.3 s "H" period of SCL clock tHIGH 4.0 0.6 s SCL SDA output delay time tDLDAT 5 x M*1 5 x M*1 ns tBUS 4.7 1.3 s 2 x M*1 2 x M*1 s 250 100*2 ns Bus free time between [STOP condition and START condition] SDA data input hold time (vs. SCL) tHDDAT SDA data input setup time (vs. SCL) tSUDAT Setup time of [repeat START condition] SCL SDA tSUSTA 4.7 0.6 s Hold time of [repeat START condition] SDA SCL tHDSTA 4.0 0.6 s Setup time of [STOP condition] SCL SDA tSUSTO 4.0 0.6 s R = 1 k C = 50 pF*4 Remarks After that, the first clock pulse is generated. *1 : M = Resource clock cycle (ns) *2 : A Fast-mode I2C bus device can be used for a standard mode I2C bus system as long as the device satisfies a requirement of "tSUDAT 250 ns". When the device does not extend the "L" period of the SCL signal, the next data must be outputted to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released. *3 : For use at over 100 kHz, set the resource clock to at least 6 MHz. *4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines. 63 MB91319R Series 5. Power-on Sequence * The power supplies must be turned on in the VDDI AVCC, AVRH, VDDE order and off in the VDDE AVCC, AVRH, VDDI order. * Turn on VDDE before applying on the analog power supply AVCC and the analog signal. 6. Electrical Characteristics for the A/D Converter (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, VSSE = VSSI = AVSS = 0 V, AVRH = 3.0 V to 3.6 V) Value Parameter Resolution Total error*1 Unit Min Typ Max 10 bit - 5.5 + 5.5 LSB - 3.5 + 3.5 LSB 1 - 2.0 + 2.0 LSB Zero transition voltage*1 - 4.0 + 6.0 LSB Full transition voltage*1 AVRH - 5.5 AVRH + 3.0 LSB 8.5*2 s Power supply voltage (analog + digital) 3.3 mA Reference power supply current (between AVRH and AVRL) 100 A Analog input capacitance 27 pF Interchannel disparity 4 LSB Nonlinear error*1 Differential linear error* Conversion time *1 : Measured in the CPU sleep state *2 : Depends on the clock cycle of the clock signal supplied to peripheral resources. 64 Remarks AVCC = 3.3 V, AVRH = 3.3 V (at CPU sleep) MB91319R Series * About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Analog input circuit R Comparator Analog input During sampling : ON C R 5 k (Max) MB91316/316A/F318R MB91F318S/FV319R C 27 pF (Max) Note : The values are reference values. * The relationship between the external impedance and minimum sampling time [External impedance = 0 k to 100 k] [External impedance = 0 k to 20 k] MB91316/316A/F318R/F318S/FV319A MB91316/316A/F318R/F318S/FV319A 20 External impedance (k) External impedance (k) 100 90 80 70 60 50 40 30 20 10 18 16 14 12 10 8 6 4 2 0 0 0 5 10 15 20 25 30 Minimum sampling time (s) 35 0 1 2 3 4 5 6 7 8 Minimum sampling time (s) * About errors * As |AVRH - AVSS| becomes smaller, values of relative errors grow larger. 65 MB91319R Series Definition of A/D Converter Terms * Resolution Indicates the ability of the A/D converter to discriminate analog variation * Linear error Expresses the deviation between actual conversion characteristics and a straight line connecting the device's zero transition point (00 0000 000000 0000 0001) and full scale transition point (11 1111 1110 11 1111 1111) * Differential linear error Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output code. [Differential linear error] [Linear Error] 3FFH Actual variation Theoretical 3FEH N - 1H 3FDH VFST (measured value) VNT (measured value) 004H 003H Actual variation Actual variation Digital output Digital output {1 LSB x (N - 1) + VTO} N - 2H V(N - 1)T (measured value) N - 1H VNT (measured value) 002H Theoretical values 001H N - 2H Actual variation VTO (measured value) AVRL AVRH AVRL AVRH Analog input Analog input = Linear error in digital output N Differential linear error in digital output N = 1 LSB = 1 LSB" = N VFST - VOT 1022 VNT - {1 LSB x (N - 1) + VOT} 1 LSB [LSB] V (N + 1) T - VNT 1 LSB [LSB] -1 [V] AVRH - AVRL 1024 [V] (theoretical value) : A/D converter digital output value VOT : Voltage at which the digital output transitions from "000"H to "001"H. VFST : Voltage at which the digital output transitions from "3FE"H to "3FF"H. VNT : Voltage at which the digital output transitions from (N-1) to N. 66 MB91319R Series * Total error Expresses the difference between actual and theoretical values as error, including zero transition error, fullscale error, and linearity error. [Total error] 3FFH Actual variation 1.5 LSB 3FEH {1 LSB x (N - 1) + 0.5 LSB Digital output 3FDH VNT (measured value) 004H 003H Actual variation 002H theoretical value 001H 0.5 LSB AVRL AVRH Analog input Total error in digital output N = VNT - {1 LSB" x (N - 1) + 0.5 LSB"} [LSB] 1 LSB" N : A/D converter digital output value VOT" (theoretical value) = AVRL + 0.5 LSB" [V] VFST" (theoretical value) = AVRH - 1.5 LSB" [V] VNT : Voltage at which digital output transitions from (N-1) to N. 67 MB91319R Series FLASH MEMORY PROGRAM/ERASE CHARACTERISTICS (VCC = 3.3 V, Ta = + 25 C) Parameter Unit Remarks 2.0 s Excludes 00H programming prior erasure. 6 100 s Excludes system-level overhead. 3.4 56 s Excludes system-level overhead. 10000 cycle Min Typ Max Sector erase time 0.5 Byte programming time Chip programming time Erase/program cycle 68 Value MB91319R Series ORDERING INFORMATION Part number Package Remarks MB91FV319RPMC-ESE1 176-pin plastic LQFP (FPT-176P-M07) For development tool MB91F318RPMC-G-XXXE1 176-pin plastic LQFP (FPT-176P-M07) With CC decoder. Without Fujitsu Flash programming. MB91F318RPMC-GXXX-XXXXE1 176-pin plastic LQFP (FPT-176P-M07) With CC decoder. With Fujitsu Flash programming. MB91F318SPMC-G-XXXE1 176-pin plastic LQFP (FPT-176P-M07) Without CC decoder. Without Fujitsu Flash programming. MB91F318SPMC-GXXX-XXXXE1 176-pin plastic LQFP (FPT-176P-M07) Without CC decoder. With Fujitsu Flash programming. MB91316PMC-G-XXXE1 176-pin plastic LQFP (FPT-176P-M07) Without CC decoder. MB91316APMC-G-XXXE1 176-pin plastic LQFP (FPT-176P-M07) With CC decoder. 69 MB91319R Series PACKAGE DIMENSION 176-pin plastic LQFP Lead pitch 0.50 mm Package width x package length 24.0 x 24.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LQFP-0176-2424-0.50 (FPT-176P-M07) 176-pin plastic LQFP (FPT-176P-M07) Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness Note 3) Pins width do not include tie bar cutting remainder. 26.000.20(1.024.008)SQ *24.000.10(.945.004)SQ 0.1450.055 (.006.002) 132 89 133 88 0.08(.003) Details of "A" part +0.20 1.50 -0.10 +.008 (Mounting height) .059 -.004 0~8 0.100.10 (.004.004) (Stand off) INDEX 176 45 "A" LEAD No. 1 44 0.50(.020) C 0.220.05 (.009.002) 0.08(.003) 0.25(.010) M 2004 FUJITSU LIMITED F176013S-c-1-1 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 70 0.500.20 (.020.008) 0.600.15 (.024.006) Dimensions in mm (inches). Note: The values in parentheses are reference values. MB91319R Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. 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