CD4027BCNX - Fairchild Semiconductor

October 1987

Revised March 2002

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

CD4027BC

Dual J-K Master/Slave Flip-Flop with Set and Reset

General Description

The CD4027BC dual J-K flip-flops are monolithic comple-

mentary M OS (CMOS ) integr ated circuits c onstruc ted with

N- and P-channel enhancement mode transistors. Each

flip-flop has independent J, K, se t, reset, and clock inp uts

and buffered Q and Q outputs. These flip-flops are edge

sensitive to the clock input and change state on the posi-

tive-going transition of the clock pulses. Set or reset is

independent of the clock and is accomplished by a high

level on the respect i ve input.

All inputs are protected against damage due to static dis-

charge by diode clamps to VDD and VSS.

Features

■Wide supply voltage rang e: 3.0V to 15V

■High noise immunity: 0.45 VDD (typ.)

■Low power TTL compatibility: Fan out of 2 driving 74L

or 1 driving 74LS

■Low power: 50 nW (typ.)

■Medium speed operation: 12 MHz (typ.) with 10V

supply

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the orderin g c ode.

Connection Diagram

Top View

Truth Table

I = HIGH Level

O = LOW Level

X = Don't Care



= LOW-to-HIGH



= HIGH-to-LOW

Note 1: tn−1 refers to the t i me inte r val p r i or to th e p osi tive cloc k pulse

transition

Note 2: tn refers to the time intervals after the positive clock pulse

transition

Note 3: Level Change

Order Number Package Number Package Description

CD4027BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4027BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Inputs tn−1

(Note 1) Outputs tn

(Note 2)

(Note 3) JKSRQQ Q



I XOOO I O



XOOO I I O



OXOOOO I



XIOOIO I



X X O O X (No Change)

XXXIOXI O

XXXOIXO I

XXXIIXI I

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CD4027BC

Logic Diagram

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CD4027BC

Absolute Maximum Ratings(Note 4)

(Note 5) Recommended Operating

Conditions (Note 5)

Note 4: “Absolute Maximum Ratings” are those va lues beyond which the

safety of the device cannot be guaranteed. They are not meant to imply

that the devices should be operated at these limits. The table of “Recom-

mended Operating Conditions” and “Electrical Characteristics” provides

conditions for actual device operation.

Note 5: VSS = 0V unles s ot herwise s pecified .

DC Electrical Characteristics (Note 6)

Note 6: VSS = 0V unless otherwise specified.

Note 7: IOH and IOL are tes t ed one ou tp ut at a ti m e.

DC Supply Voltage (VDD)−0.5 VDC to +18 VDC

Input Voltage (VIN)−0.5V to VDD +0.5 VDC

Storage Temperature Range (TS)−65°C to +150°C

Power D is sipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260°C

DC Supply Voltage (VDD) 3V to 15 VDC

Input Voltage (VIN) 0V to VDD VDC

Operating Temperature Range (TA)−55°C to +125°C

Symbol Parameter Conditions −55°C+25°C+125°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device Current VDD = 5V, VIN = VDD or VSS 1130

µAVDD = 10V, VIN = VDD or VSS 2260

VDD = 15V, VIN = VDD or VSS 44120

VOL LOW Level |IO| < 1 µA

Output Voltage VDD = 5V 0.05 0 0.05 0.05 VVDD = 10V 0.05 0 0.05 0.05

VDD = 15V 0.05 0 0.05 0.05

VOH HIGH Level |IO| < 1 µA

Output Voltage VDD = 5V 4.95 4.95 5 4.95 VVDD = 10V 9.95 9.95 10 9.95

VDD = 15V 14.95 14.95 15 14.95

VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 VInput Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0

VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0

VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 VInput Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0

VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0

IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mACurrent (Note 7) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9

VDD = 15V, VO = 1.5V 4.2 3 .4 8.8 2.4

IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 mACur rent (Note 7) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9

VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4

IIN Input Current VDD = 15V, VIN = 0V −0.1 −10−5−0.1 −1.0 µA

VDD = 15V, VIN = 15V 0.1 10−50.1 1.0

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CD4027BC

AC Electrical Characteristics (Note 8)

TA = 25°C, CL = 50 pF, trCL = tfCL = 20 ns, unless otherwise specified

Note 8: AC Parameters are guara nt eed by DC c orrelat ed testing.

Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application

note, AN-90.

Typical Applications

Ripple Binary Counters

Shift Reg i st ers

Symbol Parameter Conditions Min Typ Max Units

tPHL or tPLH Propagation Delay Time VDD = 5V 200 400 nsfrom Clock to Q or Q VDD = 10V 80 160

VDD = 15V 65 130

tPHL or tPLH Propagation Delay Time VDD = 5V 170 340 nsfrom Set to Q or Reset to Q VDD = 10V 70 140

VDD = 15V 55 110

tPHL or tPLH Propagation Delay Time VDD = 5V 110 220 nsfrom Set to Q or VDD = 10V 50 100

Reset to Q VDD = 15V 40 80

tSMinimum Data Setup Time VDD = 5V 135 270 nsVDD = 10V 55 110

VDD = 15V 45 90

tTHL or tTLH Transition Time VDD = 5V 100 200 nsVDD = 10V 50 100

VDD = 15V 40 80

fCL Maximum Clock Frequency VDD = 5V 2.5 5 MHz(Toggle Mode) VDD = 10V 6.2 12.5

VDD = 15V 7.6 15.5

trCL or tfCL Maximum Clock Rise VDD = 5V 15 µsand Fall Time VDD = 10V 10

VDD = 15V 5

tWMinimum Clock Pulse VDD = 5V 100 200 nsWidth (tWH = tWL)V

DD = 10V 40 80

VDD = 15V 32 65

tWH Minimum Set and VDD = 5V 80 160 nsReset Pu lse Width VDD = 10V 30 60

VDD = 15V 25 50

CIN Average Input Capacitance Any Input 5 7.5 pF

CPD Power Dissipation Capacity Per Flip-Flop 35 pF

(Note 9)

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CD4027BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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CD4027BC Dual J-K Master/Slave Fli p-Flop with Set and Reset

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.