CDC2509A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS603A – APRIL 1998 – REVISED JUNE 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Spread Spectrum Clock Compatible
D
100 MHz Maximum Frequency
D
Available in Plastic 24-Pin TSSOP
D
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
D
Separate Output Enable for Each Output
Bank
D
External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
D
On-Chip Series Damping Resistors
D
No External RC Network Required
D
Operates at 3.3-V VCC
description
The CDC2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2509A operates at 3.3-V VCC and provides
integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can
be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low
state.
Unlike many products containing PLLs, the CDC2509A does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2509A requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDC2509A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS OUTPUTS
1G 2G CLK 1Y
(0:4) 2Y
(0:3) FBOUT
X X L L L L
LLHLLH
LHHLHH
HLHHLH
H H H H H H
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CLK
AVCC
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
2G
FBIN
1
2
3
4
5
6
7
8
9
10
11
12
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
1G
FBOUT
24
23
22
21
20
19
18
17
16
15
14
13
PW PACKAGE
(TOP VIEW)
CDC2509A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS603A – APRIL 1998 – REVISED JUNE 1998
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
1Y2
1Y1
1Y0
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PLL
FBIN
AVCC
2G
CLK
1G
2Y2
2Y1
2Y0
2Y3
FBOUT
1Y3
1Y4
11
14
24
13
23
3
4
5
8
9
21
20
17
16
12
AVAILABLE OPTIONS
PACKAGE
TASMALL OUTLINE
(PW)
0°C to 70°C CDC2509APWR
CDC2509A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS603A – APRIL 1998 – REVISED JUNE 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME NO.
TYPE
DESCRIPTION
CLK 24 I
Clock input. CLK provides the clock signal to be distributed by the CDC2509A clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
FBIN 13 IFeedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally
zero phase error between CLK and FBIN.
1G 11 IOutput bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low , outputs 1Y(0:4) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same
frequency as CLK.
2G 14 IOutput bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low , outputs 2Y(0:3) are
disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
FBOUT 12 OFeedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK.
When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has and
integrated 25-Ω series-damping resistor.
1Y (0:4) 3, 4, 5, 8, 9 OClock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the
1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each
output has an integrated 25-Ω series-damping resistor.
2Y (0:3) 16, 17, 20, 21 OClock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the
2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each
output has an integrated 25-Ω series-damping resistor.
AVCC 23 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can
be used to bypass the PLL for test purposes. When A VCC is strapped to ground, PLL is bypassed and
CLK is buffered directly to the device outputs.
AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.
VCC 2, 10, 15, 22 Power Power supply
GND 6, 7, 18, 19 Ground Ground
CDC2509A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS603A – APRIL 1998 – REVISED JUNE 1998
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, AVCC (see Note 1) AVCC < VCC +0.7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 2) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state,
VO (see Notes 2 and 3) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 4) 0.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. AVCC must not exceed VCC.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS T echnology Data
Book
, literature number SCBD002.
recommended operating conditions (see Note 5)
MIN MAX UNIT
VCC, AVCC Supply voltage 3 3.6 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIInput voltage 0 VCC V
IOH High-level output current –12 mA
IOL Low-level output current 12 mA
TAOperating free-air temperature 0 70 °C
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
CDC2509A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS603A – APRIL 1998 – REVISED JUNE 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC, AVCC MIN TYP‡MAX UNIT
VIK II = –18 mA 3 V –1.2 V
IOH = –100 µAMIN to MAX VCC–0.2
VOH IOH = –12 mA 3 V 2.1 V
IOH = –6 mA 3 V 2.4
IOL = 100 µAMIN to MAX 0.2
VOL IOL = 12 mA 3 V 0.8 V
IOL = 6 mA 3 V 0.55
IIVI = VCC or GND 3.6 V ±5µA
ICC§VI = VCC or GND, IO = 0, Outputs: low or high 3.6 V 10 µA
∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V 500 µA
CiVI = VCC or GND 3.3 V 4 pF
CoVO = VCC or GND 3.3 V 6 pF
‡For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§For ICC of AVCC, see Figure 5.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
fclk Clock frequency 80 100 MHz
Input clock duty cycle 40% 60%
Stabilization time†1 ms
†T ime required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Note 6 and Figures 1 and 2)‡
PARAMETER FROM
(INPUT)/CONDITION
TO
(OUTPUT)
VCC, AVCC = 3.3 V
±0.165 V VCC, AVCC = 3.3 V
±0.3 V UNIT
(INPUT)/CONDITION
(OUTPUT)
MIN TYP MAX MIN TYP MAX
tphase error, reference
(see Note 7, Figure 3) 80 MHz < CLKIN↑ ≤ 100 MHz FBIN↑–700 –300 ps
tphase error, – jitter
(see Note 8) CLKIN↑ = 100 MHz FBIN↑–750 –350 –540 ps
tsk(o)§Any Y or FBOUT Any Y or FBOUT 200 ps
Jitter(pk-pk)
(see Figure 4) Clkin = 100 MHz Any Y or FBOUT –150 150 ps
Duty cycle F(clkin > 80 MHz) Any Y or FBOUT 45% 55%
trAny Y or FBOUT 1.3 1.9 0.8 2.1 ns
tfAny Y or FBOUT 1.7 2.5 1.2 2.7 ns
‡These parameters are not production tested.
§The tsk(o) specification is only valid for equal loading of all outputs.
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. This is considered as static phase error.
8. Phase error does not include jitter. The total phase error is –900 ps to –200 ps for the 5% VCC range.
CDC2509A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS603A – APRIL 1998 – REVISED JUNE 1998
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
LOAD CIRCUIT FOR OUTPUTS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tpd
50% VCC
3 V
0 V
VOH
VOL
Input
0.4 V
2 V
trtf
0.4 V
2 V
Output
500
W
50% VCC
30 pF
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
tsk(o)
tsk(o)
tphase error
CLKIN
FBIN
Any Y
Any Y
Any Y
FBOUT
Figure 2. Phase Error and Skew Calculations
CDC2509A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS603A – APRIL 1998 – REVISED JUNE 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 3
fclk – Clock Frequency – MHz
Static Phase Error – ps
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
60 70 80 90 120110100
–500
–600
–700
–750
–550
–650
–300
130
AVCC, VCC = 3.3 V
TA = 25°C
–350
–450
–400
Figure 4
fclk – Clock Frequency – MHz
Jitter (Peak-to-Peak) – ps
JITTER (PEAK-TO-PEAK)
vs
CLOCK FREQUENCY
60 70 80 90 120110100
350
250
150
100
300
200
550
130
AVCC, VCC = 3.3 V
RL = 500 Ω
CL = 30 pF
TA = 25°C
All Outputs Switching
500
400
450
fclk – Clock Frequency – MHz
AI
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
30 50 70 90 110
10
6
2
0
8
4
130
12
14
CC– Analog Supply Current – mA
AVCC, VCC = 3.3 V
TA = 25°C
Figure 5
CDC2509A
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS603A – APRIL 1998 – REVISED JUNE 1998
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040064/E 08/96
14 PIN SHOWN
Seating Plane
0,05 MIN
1,20 MAX
1
A
7
14
0,19
4,50
4,30
8
6,20
6,60
0,30
0,75
0,50
0,25
Gage Plane
0,15 NOM
0,65 M
0,10
0°–8°
0,10
PINS **
A MIN
A MAX
DIM
2,90
3,10
8
4,90
5,10
14
6,60
6,404,90
5,10
16
7,70
20
7,90
24
9,60
9,80
28
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
